Syed Mohsin Abbas

30 papers C 3Misc 1Journal 17Unranked 9
YearRankTypeTitle / Venue / Authors
2025 — conf
High Level Synthesis Design for Soft-Input GRAND.
IEEECONF
Tuomas Aaltonen, Mikko Valkama, Syed Mohsin Abbas
2025 J jnl
Improved Step-GRAND: Low-Latency Soft-Input Guessing Random Additive Noise Decoding.
IEEE Trans. Very Large Scale Integr. Syst.
Syed Mohsin Abbas, Marwan Jalaleddine, Chi-Ying Tsui, Warren J. Gross
2025 C conf
Reconfigurable Image Acquisition and Processing Subsystem for MPSoCs.
ISCAS
Mohamed Soliman, Antti Nurmi, Syed Mohsin Abbas
2025 — conf
Revisiting GRAND via High Level Synthesis.
SiPS
Tuomas Aaltonen, Mikko Valkama, Syed Mohsin Abbas
2024 J jnl
Confinement Specific Design of SOI Rib Waveguides with Submicron Dimensions and Single Mode Operation.
CoRR
Abdurrahman Javid Shaikh, Abdul Ghani Abro, Mirza Muhammad Ali Baig, Muhammad Adeel Ahmad Siddiqui, Syed Mohsin Abbas
2023 J jnl
List-GRAND: A Practical Way to Achieve Maximum Likelihood Decoding.
IEEE Trans. Very Large Scale Integr. Syst.
Syed Mohsin Abbas, Marwan Jalaleddine, Warren J. Gross
2023 — conf
Step-GRAND: A Low Latency Universal Soft-Input Decoder.
GLOBECOM (Workshops)
Syed Mohsin Abbas, Chi-Ying Tsui, Marwan Jalaleddine, Warren J. Gross
2023 J jnl
Step-GRAND: A Low Latency Universal Soft-input Decoder.
CoRR
Syed Mohsin Abbas, Marwan Jalaleddine, Chi-Ying Tsui, Warren J. Gross
2022 — conf
GRAND for Rayleigh Fading Channels.
GLOBECOM (Workshops)
Syed Mohsin Abbas, Marwan Jalaleddine, Warren J. Gross
2022 J jnl
GRAND for Rayleigh Fading Channels.
CoRR
Syed Mohsin Abbas, Marwan Jalaleddine, Warren J. Gross
2022 J jnl
Hardware Architecture for Guessing Random Additive Noise Decoding Markov Order (GRAND-MO).
J. Signal Process. Syst.
Syed Mohsin Abbas, Marwan Jalaleddine, Warren J. Gross
2022 J jnl
High-Throughput and Energy-Efficient VLSI Architecture for Ordered Reliability Bits GRAND.
IEEE Trans. Very Large Scale Integr. Syst.
Syed Mohsin Abbas, Thibaud Tonnellier, Furkan Ercan, Marwan Jalaleddine, Warren J. Gross
2021 — conf
High-Throughput VLSI Architecture for GRAND Markov Order.
SiPS
Syed Mohsin Abbas, Marwan Jalaleddine, Warren J. Gross
2021 J jnl
High-Throughput VLSI Architecture for GRAND Markov Order.
CoRR
Syed Mohsin Abbas, Marwan Jalaleddine, Warren J. Gross
2021 Misc conf
High-Throughput VLSI Architecture for Soft-Decision Decoding with ORBGRAND.
ICASSP
Syed Mohsin Abbas, Thibaud Tonnellier, Furkan Ercan, Marwan Jalaleddine, Warren J. Gross
2021 J jnl
High-Throughput VLSI architecture for Soft-Decision decoding with ORBGRAND.
CoRR
Syed Mohsin Abbas, Thibaud Tonnellier, Furkan Ercan, Marwan Jalaleddine, Warren J. Gross
2021 J jnl
High-Throughput and Energy-Efficient VLSI Architecture for Ordered Reliability Bits GRAND.
CoRR
Syed Mohsin Abbas, Thibaud Tonnellier, Furkan Ercan, Marwan Jalaleddine, Warren J. Gross
2021 J jnl
List-GRAND: A practical way to achieve Maximum Likelihood Decoding.
CoRR
Syed Mohsin Abbas, Marwan Jalaleddine, Warren J. Gross
2021 — conf
Reduced Complexity RPA Decoder for Reed-Muller Codes.
ISTC
Jiajie Li, Syed Mohsin Abbas, Thibaud Tonnellier, Warren J. Gross
2020 — conf
High-Throughput VLSI Architecture for GRAND.
SiPS
Syed Mohsin Abbas, Thibaud Tonnellier, Furkan Ercan, Warren J. Gross
2020 J jnl
High-Throughput VLSI Architecture for GRAND.
CoRR
Syed Mohsin Abbas, Thibaud Tonnellier, Furkan Ercan, Warren J. Gross
2017 J jnl
Concatenated LDPC-Polar Codes Decoding Through Belief Propagation.
CoRR
Syed Mohsin Abbas, YouZhe Fan, Ji Chen, Chi-Ying Tsui
2017 C conf
Concatenated LDPC-polar codes decoding through belief propagation.
ISCAS
Syed Mohsin Abbas, YouZhe Fan, Ji Chen, Chi-Ying Tsui
2017 J jnl
High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder.
IEEE Trans. Very Large Scale Integr. Syst.
Syed Mohsin Abbas, YouZhe Fan, Ji Chen, Chi-Ying Tsui
2016 — conf
Approximate Matrix Inversion for Linear Pre-coders in Massive MIMO.
VLSI-SoC (Selected Papers)
Syed Mohsin Abbas, Chi-Ying Tsui
2016 C conf
Low-latency approximate matrix inversion for high-throughput linear pre-coders in massive MIMO.
VLSI-SoC
Syed Mohsin Abbas, Chi-Ying Tsui
2015 J jnl
FSNoC: A Flit-Level Speedup Scheme for Network on-Chips Using Self-Reconfigurable Bidirectional Channels.
IEEE Trans. Very Large Scale Integr. Syst.
Zhiliang Qian, Syed Mohsin Abbas, Chi-Ying Tsui
2015 J jnl
Low Complexity Belief Propagation Polar Code Decoders.
CoRR
Syed Mohsin Abbas, YouZhe Fan, Ji Chen, Chi-Ying Tsui
2015 — conf
Low complexity belief propagation polar code decoder.
SiPS
Syed Mohsin Abbas, YouZhe Fan, Ji Chen, Chi-Ying Tsui
2014 J jnl
An Efficient Multiple Cell Upsets Tolerant Content-Addressable Memory.
IEEE Trans. Computers
Syed Mohsin Abbas, Soonyoung Lee, Sanghyeon Baeg, Sungju Park