Syed M. Alam

33 papers C 1Journal 13Unranked 17
YearRankTypeTitle / Venue / Authors
2025 — conf
STT-MRAM Antifuse Macro for Memory, SoC, and FPGA Chips.
IMW
Syed M. Alam, X. Zhang, H. Xu, M. Sadd, M. DeHerrera, S. Ikegawa, Fred B. Mancoff, K. Nagel, Y. Kim, S. Aggarwal
2023 J jnl
Adiabatic/MTJ-Based Physically Unclonable Function for Consumer Electronics Security.
IEEE Trans. Consumer Electron.
Zachary Kahleifeh, Himanshu Thapliyal, Syed M. Alam
2022 — conf
Persistent xSPI STT-MRAM with up to 400MB/s Read and Write Throughput.
IMW
Syed M. Alam, Dimitri Houssameddine, F. Neumeyer, I. Rahman, M. DeHerrera, S. Ikegawa, P. Sanchez, X. Zhang, Y. Wang, J. Williams, Dietmar Gogl, H. Xu, M. Farook, D. Aceves, H. K. Lee, Fred B. Mancoff, M. Chou, CH. Tan, B. Huang, S. Mukherjee, M. Lu, A. Shah, K. Nagel, Y. Kim, S. Aggarwal
2021 — conf
Commercialization of 1Gb Standalone Spin-Transfer Torque MRAM.
IMW
J. J. Sun, M. DeHerrera, B. Hughes, S. Ikegawa, H. K. Lee, Fred B. Mancoff, K. Nagel, G. Shimon, Syed M. Alam, D. Houssameddine, S. Aggarwal
2014 J jnl
Nano Magnetic STT-Logic Partitioning for Optimum Performance.
IEEE Trans. Very Large Scale Integr. Syst.
Jayita Das, Syed M. Alam, Sanjukta Bhanja
2014 — ch.
STT-Based Non-Volatile Logic-in-Memory Framework.
Field-Coupled Nanocomputing
Jayita Das, Syed M. Alam, Sanjukta Bhanja
2013 — conf
ST-MRAM fundamentals, challenges, and applications.
CICC
Thomas W. Andre, Syed M. Alam, Dietmar Gogl, C. K. Subramanian, Hal Lin, W. Meadows, X. Zhang, Nicholas D. Rizzo, Jason Janesky, D. Houssameddine, Jon M. Slaughter
2013 — conf
Welcome to ISQED 2013.
ISQED
Mark M. Budnik, Rasit Onur Topaloglu, Pallab Chatterjee, Keith A. Bowman, Kamesh V. Gadepally, Paul Wesling, Syed M. Alam, Rajiv V. Joshi
2012 — conf
Non-destructive variability tolerant differential read for non-volatile logic.
MWSCAS
Jayita Das, Syed M. Alam, Sanjukta Bhanja
2012 J jnl
Ultra-Low Power Hybrid CMOS-Magnetic Logic Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jayita Das, Syed M. Alam, Sanjukta Bhanja
2011 J jnl
Low Power Magnetic Quantum Cellular Automata Realization Using Magnetic Multi-Layer Structures.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Jayita Das, Syed M. Alam, Sanjukta Bhanja
2011 J jnl
Maximum error modeling for fault-tolerant computation using maximum a posteriori (MAP) hypothesis.
Microelectron. Reliab.
Karthikeyan Lingasubramanian, Syed M. Alam, Sanjukta Bhanja
2011 — conf
Mitigating TSV-induced substrate noise in 3-D ICs using GND plugs.
ISQED
Nauman H. Khan, Syed M. Alam, Soha Hassoun
2011 J jnl
Power Delivery Design for 3-D ICs Using Different Through-Silicon Via (TSV) Technologies.
IEEE Trans. Very Large Scale Integr. Syst.
Nauman H. Khan, Syed M. Alam, Soha Hassoun
2011 J jnl
Thermal-electrical co-optimisation of floorplanning of three-dimensional integrated circuits under manufacturing and physical design constraints.
IET Comput. Digit. Tech.
Ankur Jain, Syed M. Alam, Scott Pozder, Robert E. Jones
2010 J jnl
BIST to Detect and Characterize Transient and Parametric Failures.
IEEE Des. Test Comput.
Alodeep Sanyal, Syed M. Alam, Sandip Kundu
2010 J jnl
Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits.
Microelectron. J.
Ioannis Savidis, Syed M. Alam, Ankur Jain, Scott Pozder, Robert E. Jones, Ritwik Chatterjee
2010 J jnl
Interstratum Connection Design Considerations for Cost-Effective 3-D System Integration.
IEEE Trans. Very Large Scale Integr. Syst.
Syed M. Alam, Robert E. Jones, Scott Pozder, Ritwik Chatterjee, Shahid Rauf, Ankur Jain
2009 — conf
Die/wafer stacking with reciprocal design symmetry (RDS) for mask reuse in three-dimensional (3D) integration technology.
ISQED
Syed M. Alam, Robert E. Jones, Scott Pozder, Ankur Jain
2009 J jnl
Study of Circuit-Specific Error Bounds for Fault-Tolerant Computation using Maximum a posteriori (MAP) Hypothesis
CoRR
Karthikeyan Lingasubramanian, Syed M. Alam, Sanjukta Bhanja
2009 — conf
System-level comparison of power delivery design for 2D and 3D ICs.
3DIC
Nauman H. Khan, Syed M. Alam, Soha Hassoun
2009 — conf
Through-Silicon Via (TSV)-induced noise characterization and noise mitigation using coaxial TSVs.
3DIC
Nauman H. Khan, Syed M. Alam, Soha Hassoun
2008 J jnl
A 180 Kbit Embeddable MRAM Memory Module.
IEEE J. Solid State Circuits
Joseph J. Nahas, Thomas W. Andre, Brad Garni, Chitra K. Subramanian, Hal Lin, Syed M. Alam, Ken Papworth, William L. Martino
2008 C conf
A Built-In Self-Test Scheme for Soft Error Rate Characterization.
IOLTS
Alodeep Sanyal, Syed M. Alam, Sandip Kundu
2008 — conf
Technology, CAD tools, and designs for emerging 3D integration technology.
ACM Great Lakes Symposium on VLSI
Syed M. Alam, Mike Ignatowski, Yuan Xie
2007 — conf
A 180 Kbit Embeddable MRAM Memory Module.
CICC
Joseph J. Nahas, Thomas W. Andre, Chitra K. Subramanian, Hal Lin, Syed M. Alam, Ken Papworth, William L. Martino
2007 — conf
Inter-Strata Connection Characteristics and Signal Transmission in Three-Dimensional (3D) Integration Technology.
ISQED
Syed M. Alam, Robert E. Jones, Shahid Rauf, Ritwik Chatterjee
2007 J jnl
Reliability computer-aided design tool for full-chip electromigration analysis and comparison with different interconnect metallizations.
Microelectron. J.
Syed M. Alam, Chee Lip Gan, Carl V. Thompson, Donald E. Troxel
2005 — conf
Electromigration Reliability Comparison of Cu and Al Interconnects.
ISQED
Syed M. Alam, Frank L. Wei, Chee Lip Gan, Carl V. Thompson, Donald E. Troxel
2005 — conf
Thermal aware cell-based full-chip electromigration reliability analysis.
ACM Great Lakes Symposium on VLSI
Syed M. Alam, Donald E. Troxel, Carl V. Thompson
2004 — conf
Circuit Level Reliability Analysis of Cu Interconnects.
ISQED
Syed M. Alam, Chee Lip Gan, Carl V. Thompson, Donald E. Troxel
2004 — —
Design tool and methodologies for interconnect reliability analysis in integrated circuits.
Syed M. Alam
2002 — conf
A Comprehensive Layout Methodology and Layout-Specific Circuit Analyses for Three-Dimensional Integrated Circuits.
ISQED
Syed M. Alam, Donald E. Troxel, Carl V. Thompson