Syed Ershad Ahmed

44 papers C 2Misc 3Journal 21Unranked 18
YearRankTypeTitle / Venue / Authors
2026 J jnl
Exploring Posit Multiplication: A Comprehensive Review of Booth and Logarithmic Mantissa Methods.
IET Comput. Digit. Tech.
Thalla Narasimha Swetha, Uppugunduru Anil Kumar, Syed Ershad Ahmed
2025 J jnl
A Power-Efficient Gaussian Filter Architecture Using Adder Compressors for Edge Detection Application.
Circuits Syst. Signal Process.
Sahith Guturu, Anil Kumar Uppugunduru, Apoorva Sharma, Syed Ershad Ahmed
2025 J jnl
Addressing Adversarial Attacks in IoT Using Deep Learning AI Models.
IEEE Access
Sesibhushana Rao Bommana, Sreehari Veeramachaneni, Syed Ershad Ahmed, M. B. Srinivas
2025 J jnl
Design of Approximate Adder With Reconfigurable Accuracy.
IEEE Access
Aalelai Vendhan, Syed Ershad Ahmed, S. Gurunarayanan
2025 J jnl
Energy-Efficient Decoding and Encoding Hardware for Optimized Posit Arithmetic.
IEEE Embed. Syst. Lett.
Aditya Anirudh Jonnalagadda, Rishi Thotli, Sreehari Veeramachaneni, Uppugunduru Anil Kumar, Syed Ershad Ahmed
2025 J jnl
Implementation of exact and approximate adder based divider for error resilient applications.
Discov. Comput.
Veerabadra Chary Rasoju, Anil Kumar Uppugunduru, Abhay Shriram, Sreehari Veeramachaneni, Syed Ershad Ahmed
2024 J jnl
ADEPNET: A Dynamic-Precision Efficient Posit Multiplier for Neural Networks.
IEEE Access
Aditya Anirudh Jonnalagadda, Uppugunduru Anil Kumar, Rishi Thotli, Satvik Sardesai, Sreehari Veeramachaneni, Syed Ershad Ahmed
2024 — conf
Energy Efficient Approximate Ternary Adder for Image Processing Applications.
ISED
Dhananjay Rao Thallikar Shyam, Uppugunduru Anil Kumar, Subham Prasad Dash, Syed Ershad Ahmed
2024 J jnl
Energy Efficient Ternary Multi-trit Multiplier Design Using Novel Adders.
Circuits Syst. Signal Process.
Aalelai Vendhan, Syed Ershad Ahmed, S. Gurunarayanan
2024 — conf
Energy-Efficient Ternary Multiplier.
AICAS
Rishi Agrawal, Narayanabhatla Savyasachi Abhijith, Uppugunduru Anil Kumar, Sreehari Veeramachaneni, Syed Ershad Ahmed
2024 J jnl
HEAD: High-Speed Approximate HEterogeneous ADder for Error-Resilient Applications.
J. Circuits Syst. Comput.
Sahith Guturu, Uppugunduru Anil Kumar, Shruti Verma, Syed Ershad Ahmed
2023 J jnl
A General Methodology to Optimize Flagged Constant Addition.
J. Circuits Syst. Comput.
Aroondhati Bhure, P. Smriti, Vinay Dhanote, Uppugunduru Anil Kumar, Syed Ershad Ahmed
2023 J jnl
CAAM: Compressor-Based Adaptive Approximate Multiplier for Neural Network Applications.
IEEE Embed. Syst. Lett.
Uppugunduru Anil Kumar, S. Vignesh Bharadwaj, Avinash Bhat Pattaje, Suresh Nambi, Syed Ershad Ahmed
2023 J jnl
Design methodology for highly accurate approximate multipliers for error resilient applications.
Comput. Electr. Eng.
Sahith Guturu, Uppugunduru Anil Kumar, S. Vignesh Bharadwaj, Syed Ershad Ahmed
2023 — conf
Design of Energy Efficient Posit Multiplier.
ACM Great Lakes Symposium on VLSI
Aditya Anirudh Jonnalagadda, Anil Kumar Uppugunduru, Sreehari Veeramachaneni, Syed Ershad Ahmed
2023 — conf
Highly Accurate Approximate Ternary Multipliers for Error Resilient Applications.
ISED
Shalini Burri, Gowtham Sri Harsha Kudulla, Pavan Kumar Jogi, Anantha Sai Satwik Vysyaraju, Uppugunduru Anil Kumar, Syed Ershad Ahmed, Sreehari Veeramachaneni
2023 J jnl
Improved approximate multiplier architecture for image processing and neural network applications.
Microprocess. Microsystems
Pramod Alamuri, Uppugunduru Anil Kumar, Vallepu Vannuru, Syed Ershad Ahmed
2023 — conf
Low Power Approximate Divider and Square Root Circuits for Error Resilient Applications.
ISED
Uppugunduru Anil Kumar, Viren Ramchandani, Syed Shakeel Hashmi, Sanjay Dubey, Syed Ershad Ahmed
2023 — conf
Low-Power Approximate Multiplier Architecture for Error Resilient Applications.
ISED
Apurva Kumari, Ch. Vandana, Chowta Mallikharjuna Rao, Uppugunduru Anil Kumar, Syed Ershad Ahmed
2023 — conf
Power Efficient Approximate Ternary Subtractor for Image Processing Applications.
iSES
Sangireddy Tharuni, Basani Harshavardhan Reddy, Bhukya Mamatha, Uppugunduru Anil Kumar, Syed Ershad Ahmed, Sreehari Veeramachaneni
2022 J jnl
A High-Speed and Power-Efficient Approximate Adder for Image Processing Applications.
J. Circuits Syst. Comput.
Uppugunduru Anil Kumar, G. Sahith, Sumit K. Chatterjee, Syed Ershad Ahmed
2022 J jnl
Compressor based hybrid approximate multiplier architectures with efficient error correction logic.
Comput. Electr. Eng.
Anil Kumar Uppugunduru, S. Vignesh Bharadwaj, Syed Ershad Ahmed
2022 J jnl
Design and exploration of low-power SAD architectures using approximate compressors for Integer Motion Estimation.
Microprocess. Microsystems
Uppugunduru Anil Kumar, Sahith Guturu, Syed Ershad Ahmed
2022 J jnl
Low-Power Compressor-Based Approximate Multipliers With Error Correcting Module.
IEEE Embed. Syst. Lett.
Uppugunduru Anil Kumar, Sumit K. Chatterjee, Syed Ershad Ahmed
2021 J jnl
An Efficient Hardware Approach for Approximate Logarithmic Computation.
J. Circuits Syst. Comput.
Syed Ershad Ahmed, Yerasuri Mohana Sri Krishna
2021 — conf
Approximate Multiplier Architectures for Error Resilient Applications.
iSES
Uppugunduru Anil Kumar, Ratna Kumari Chintakunta, Sandeep Kumar, K. Jamal, Syed Ershad Ahmed
2021 J jnl
DeBAM: Decoder-Based Approximate Multiplier for Low Power Applications.
IEEE Embed. Syst. Lett.
Suresh Nambi, Uppugunduru Anil Kumar, Kavya Radhakrishnan, Mythreye Venkatesan, Syed Ershad Ahmed
2021 — conf
Lower part OR based Approximate Multiplier for Error Resilient Applications.
iSES
Uppugunduru Anil Kumar, Goli Naga Sandesh, Dhoti Ojusteja, Syed Ershad Ahmed
2021 — conf
Power-Efficient MLOA for error resilient applications.
iSES
Sahith Guturu, Anil Kumar Uppugunduru, Sridhar Thota, Syed Ershad Ahmed
2020 — conf
Evaluation of Multiplier-Less DCT Transform Using In-Exact Computing.
MIND (2)
Uppugunduru Anil Kumar, Nishant Jain, Sumit K. Chatterjee, Syed Ershad Ahmed
2019 J jnl
An Improved Logarithmic Multiplier for Media Processing.
J. Signal Process. Syst.
Syed Ershad Ahmed, M. B. Srinivas
2018 J jnl
Improved designs of digit-by-digit decimal multiplier.
Integr.
Syed Ershad Ahmed, Ch. Santosh Varma, M. B. Srinivas
2016 Misc conf
A Hybrid Energy Efficient Digital Comparator.
VLSID
Syed Ershad Ahmed, S. Sweekruth Srinivas, M. B. Srinivas
2016 C conf
An Iterative Logarithmic Multiplier with Improved Precision.
ARITH
Syed Ershad Ahmed, Sanket Kadam, M. B. Srinivas
2014 Misc conf
A Decimal/Binary Multi-operand Adder Using a Fast Binary to Decimal Converter.
VLSID
Ch. Santosh Varma, Syed Ershad Ahmed, M. B. Srinivas
2014 — conf
A unified flagged prefix constant addition-subtraction scheme for design of area and power efficient binary floating-point and constant integer arithmetic circuits.
APCCAS
Soumya Ganguly, Abhishek Mittal, Syed Ershad Ahmed, M. B. Srinivas
2012 — conf
A Modified Twin Precision Multiplier with 2D Bypassing Technique.
ISED
Syed Ershad Ahmed, Sibi Abraham, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
2012 — conf
Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders.
ISVLSI
Chetan Kumar Vudadha, P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, Mandalika B. Srinivas
2012 — conf
Design of Prefix-Based Optimal Reversible Comparator.
ISVLSI
Chetan Kumar Vudadha, P. Sai Phaneendra, Sreehari Veeramachaneni, Syed Ershad Ahmed, N. Moorthy Muthukrishnan, Mandalika B. Srinivas
2012 Misc conf
Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs.
VLSI Design
Chetan Kumar Vudadha, Goutham Makkena, M. Venkata Swamy Nayudu, P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
2011 — conf
A Prefix Based Reconfigurable Adder.
ISVLSI
Chetan Kumar V., Sai Phaneendra P., Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
2011 — conf
A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with Improved Decision Block.
ISED
Chetan Kumar V., P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
2011 C conf
A Unified Architecture for BCD and Binary Adder/Subtractor.
DSD
Chetan Kumar V., P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
2011 — conf
Increment/decrement/2's complement/priority encoder circuit for varying operand lengths.
ISCIT
P. Sai Phaneendra, Chetan Kumar Vudadha, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas