Swarup Bhunia

402 papers A* 15A 50B 2C 15Misc 31Journal 186Unranked 98
YearRankTypeTitle / Venue / Authors
2026 J jnl
ASTRA: Automated Insertion of Distributed Entropy Sources for Robust Authentication.
IEEE Trans. Very Large Scale Integr. Syst.
Atri Chatterjee, Habibur Rahaman, Swarup Bhunia
2026 J jnl
COVERT: Trojan Detection in COTS Hardware via Statistical Activation of Microarchitectural Events.
CoRR
Mahmudul Hasan, Sudipta Paria, Swarup Bhunia, Tamzidul Hoque
2026 J jnl
Fortifying AI Systems: Emerging Threats and Security Countermeasures.
SN Comput. Sci.
Habibur Rahaman, Atri Chatterjee, Swarup Bhunia
2026 J jnl
Harnessing the Power of LLMs for Enhancing Hardware Security.
SN Comput. Sci.
Sudipta Paria, Swarup Bhunia
2026 J jnl
Look-Up Table-Based Energy-Efficient Architecture for Neural Accelerators (LANA).
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ovishake Sen, Chukwufumnanya Ogbogu, Peyman Dehghanzadeh, Janardhan Rao Doppa, Swarup Bhunia, Partha Pratim Pande, Baibhab Chatterjee
2026 A conf
PROM: Protection against Reverse Engineering Attacks through Programmable Logic Macros.
FPGA
Pravin Gaikwad, Aritra Dasgupta, Sudipta Paria, Peyman Dehghanzadeh, Jonathan Cruz, Swarup Bhunia
2025 J jnl
A Wearable Dual-Mode Probe for Image-Guided Closed-Loop Ultrasound Neuromodulation.
IEEE Trans. Biomed. Circuits Syst.
Junjun Huan, Vida Pashaei, Steve J. A. Majerus, Swarup Bhunia, Soumyajit Mandal
2025 Misc conf
CLIP: A Structural Approach to Cut Points Matching for Logic Equivalence Checking.
VTS
Dinesh Reddy Ankireddy, Sudipta Paria, Aritra Dasgupta, Sandip Ray, Swarup Bhunia
2025 J jnl
DAASH: A Meta-Attack Framework for Synthesizing Effective and Stealthy Adversarial Examples.
CoRR
Abdullah Al Nomaan Nafi, Habibur Rahaman, Zafaryab Haider, Tanzim Mahfuz, Fnu Suya, Swarup Bhunia, Prabuddha Chakraborty
2025 J jnl
Enhancing Test Efficiency through Automated ATPG-Aware Lightweight Scan Instrumentation.
CoRR
Sudipta Paria, Md Rezoan Ferdous, Aritra Dasgupta, Atri Chatterjee, Swarup Bhunia
2025 C conf
FV-PAL: Scalable Formal Verification through Partitioning and LLM-Guided Property Generation.
ICCD
Sudipta Paria, Aritra Dasgupta, Dinesh Reddy Ankireddy, Prabuddha Chakraborty, Swarup Bhunia
2025 J jnl
Fusion Intelligence: A Paradigm for Merging Natural and Artificial Intelligence.
IEEE Internet Things J.
Rohan Reddy Kalavakonda, Peyman Dehghanzadeh, Junjun Huan, Soumyajit Mandal, Swarup Bhunia
2025 J jnl
HAMLOCK: HArdware-Model LOgically Combined attacK.
CoRR
Sanskar Amgain, Daniel Lobo, Atri Chatterjee, Swarup Bhunia, Fnu Suya
2025 J jnl
HIPR: Hardware IP Protection through Low-Overhead Fine-Grain Redaction.
IACR Cryptol. ePrint Arch.
Aritra Dasgupta, Sudipta Paria, Swarup Bhunia
2025 J jnl
HIPR: Hardware IP Protection through Low-Overhead Fine-Grain Redaction.
IACR Trans. Cryptogr. Hardw. Embed. Syst.
Aritra Dasgupta, Sudipta Paria, Swarup Bhunia
2025 J jnl
Intelligent Graybox Fuzzing via ATPG-Guided Seed Generation and Submodule Analysis.
CoRR
Raghul Saravanan, Sudipta Paria, Aritra Dasgupta, Swarup Bhunia, Sai Manoj PD
2025 J jnl
LASA: Enhancing SoC Security Verification with LLM-Aided Property Generation.
CoRR
Dinesh Reddy Ankireddy, Sudipta Paria, Aritra Dasgupta, Sandip Ray, Swarup Bhunia
2025 — conf
LASSO: LLM-Aided Security Property Generation for Assertion-based SoC Verification.
MLCAD
Dinesh Reddy Ankireddy, Sudipta Paria, Aritra Dasgupta, Sandip Ray, Swarup Bhunia
2025 J jnl
LATTE: Library Attack for Evaluating Hardware IP Protections Against Reverse Engineering.
IEEE Des. Test
Aritra Dasgupta, Sudipta Paria, Christopher Sozio, Swarup Bhunia
2025 A conf
LITE: ATPG-Aware Lightweight Scan Instrumentation for Enhancing Test Efficiency.
ITC
Sudipta Paria, Md Rezoan Ferdous, Aritra Dasgupta, Atri Chatterjee, Swarup Bhunia
2025 J jnl
LUNA-CiM: A Programmable Compute-in-Memory Fabric for Neural Network Acceleration.
IEEE Trans. Computers
Peyman Dehghanzadeh, Ovishake Sen, Baibhab Chatterjee, Swarup Bhunia
2025 J jnl
Library-Attack: Reverse Engineering Approach for Evaluating Hardware IP Protection.
CoRR
Aritra Dasgupta, Sudipta Paria, Christopher Sozio, Andrew Lukefahr, Swarup Bhunia
2025 Misc conf
MARVEL-PUF: A Robust Multi-Bit Memory PUF for FPGA-based Embedded Systems Security.
CODES+ISSS
Atri Chatterjee, Habibur Rahman, Swarup Bhunia
2025 J jnl
MBM PUF: A Multi-Bit Memory-Based Physical Unclonable Function.
IEEE Trans. Circuits Syst. I Regul. Pap.
Peyman Dehghanzadeh, Soumyajit Mandal, Swarup Bhunia
2025 A* conf
POLARIS: Explainable Artificial Intelligence for Mitigating Power Side-Channel Leakage.
DAC
Tanzim Mahfuz, Sudipta Paria, Tasneem Suha, Swarup Bhunia, Prabuddha Chakraborty
2025 J jnl
POLARIS: Explainable Artificial Intelligence for Mitigating Power Side-Channel Leakage.
CoRR
Tanzim Mahfuz, Sudipta Paria, Tasneem Suha, Swarup Bhunia, Prabuddha Chakraborty
2025 A conf
PROFUZZ: Directed Graybox Fuzzing via Module Selection and ATPG-Guided Seed Generation.
ICCAD
Raghul Saravanan, Sudipta Paria, Aritra Dasgupta, Swarup Bhunia, Sai Manoj P. D.
2025 J jnl
Runtime Detection of Adversarial Attacks in AI Accelerators Using Performance Counters.
CoRR
Habibur Rahaman, Atri Chatterjee, Swarup Bhunia
2025 Misc conf
SALTY: Explainable Artificial Intelligence Guided Structural Analysis for Hardware Trojan Detection.
VTS
Tanzim Mahfuz, Pravin Gaikwad, Tasneem Suha, Swarup Bhunia, Prabuddha Chakraborty
2025 J jnl
SALTY: Explainable Artificial Intelligence Guided Structural Analysis for Hardware Trojan Detection.
CoRR
Tanzim Mahfuz, Pravin Gaikwad, Tasneem Suha, Swarup Bhunia, Prabuddha Chakraborty
2025 J jnl
Secure and Storage-Efficient Deep Learning Models for Edge AI Using Automatic Weight Generation.
CoRR
Habibur Rahaman, Atri Chatterjee, Swarup Bhunia
2025 J jnl
Security Enclave Architecture for Heterogeneous Security Primitives for Supply-Chain Attacks.
CoRR
Kshitij Raj, Atri Chatterjee, Patanjali SLPSK, Swarup Bhunia, Sandip Ray
2025 J jnl
SynFuzz: Leveraging Fuzzing of Netlist to Detect Synthesis Bugs.
CoRR
Raghul Saravanan, Sudipta Paria, Aritra Dasgupta, Venkat Nitin Patnala, Swarup Bhunia, Sai Manoj PD
2025 Misc conf
Towards Automated Verification of IP and COTS: Leveraging LLMs in Pre- and Post-Silicon Stages.
VTS
Sudipta Paria, Aritra Dasgupta, Swarup Bhunia
2025 J jnl
X-DFS: Explainable Artificial Intelligence Guided Design-for-Security Solution Space Exploration.
IEEE Trans. Inf. Forensics Secur.
Tanzim Mahfuz, Swarup Bhunia, Prabuddha Chakraborty
2024 J jnl
A Self-Aware Digital Memory Framework Powered by Artificial Intelligence.
IEEE Trans. Artif. Intell.
Prabuddha Chakraborty, Swarup Bhunia
2024 — conf
An Intelligent Memory Framework for Resource Constrained IoT Systems.
ISVLSI
Prabuddha Chakraborty, Swarup Bhunia
2024 — conf
Compressed Plane-Wave Compounding for Efficient Imaging on Portable Ultrasound Devices.
BioCAS
Deepanshu Trivedi, Junjun Huan, Arjuna Madanayake, Swarup Bhunia, Soumyajit Mandal
2024 — conf
DiSPEL: A Framework for SoC Security Policy Synthesis and Distributed Enforcement.
HOST
Sudipta Paria, Aritra Dasgupta, Swarup Bhunia
2024 J jnl
FDPUF: Frequency-Domain PUF for Robust Authentication of Edge Devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shubhra Deb Paul, Aritra Dasgupta, Swarup Bhunia
2024 J jnl
Fusion Intelligence: Confluence of Natural and Artificial Intelligence for Enhanced Problem-Solving Efficiency.
CoRR
Rohan Reddy Kalavakonda, Junjun Huan, Peyman Dehghanzadeh, Archit Jaiswal, Soumyajit Mandal, Swarup Bhunia
2024 J jnl
IOLock: An Input/Output Locking Scheme for Protection Against Reverse Engineering Attacks.
IEEE Trans. Very Large Scale Integr. Syst.
Christopher Vega, Patanjali SLPSK, Swarup Bhunia
2024 — conf
IP Security in Structured ASIC: Challenges and Prospects.
ISVLSI
Rasheed Almawzan, Sudipta Paria, Aritra Dasgupta, Kostas Amberiadis, Swarup Bhunia
2024 — conf
LATENT: Leveraging Automated Test Pattern Generation for Hardware Trojan Detection.
ATS
Sudipta Paria, Pravin Gaikwad, Aritra Dasgupta, Swarup Bhunia
2024 — conf
LISA: A Multi-Layered Iterative Framework for Hardening Obfuscation with Modular Unit Transformations.
ACM Great Lakes Symposium on VLSI
Rasheed Almawzan, Atri Chatterjee, Aritra Dasgupta, Swarup Bhunia
2024 J jnl
Learning Your Lock: Exploiting Structural Vulnerabilities in Logic Locking.
IEEE Des. Test
Prabuddha Chakraborty, Jonathan Cruz, Rasheed Almawzan, Tanzim Mahfuz, Swarup Bhunia
2024 — conf
Navigating SoC Security Landscape on LLM-Guided Paths.
ACM Great Lakes Symposium on VLSI
Sudipta Paria, Aritra Dasgupta, Swarup Bhunia
2024 J jnl
Nuclear Quadrupole Resonance for Substance Detection.
IEEE Access
Kelsey L. Horace-Herron, Naren Vikram Raj Masna, Swarup Bhunia, Soumyajit Mandal, Sandip Ray
2024 J jnl
PRISTINE: An Emulation Platform for PCB-Level Hardware Trojans.
IEEE Access
Junjun Huan, Shubhra Deb Paul, Soumyajit Mandal, Swarup Bhunia
2024 J jnl
Pasteables: A Flexible and Smart "Stick-and-Peel" Wearable Platform for Fitness and Athletics.
IEEE Consumer Electron. Mag.
Reiner N. Dizon-Paradis, Rohan Reddy Kalavakonda, Prabuddha Chakraborty, Swarup Bhunia
2024 — conf
Pasteables: A Flexible, Stick-and-Peel Smart Sensing Platform for Edge Applications.
ISVLSI
Reiner N. Dizon-Paradis, Aritra Dasgupta, Rohan Reddy Kalavakonda, Swarup Bhunia
2024 J jnl
Practical Implementation of Robust State-Space Obfuscation for Hardware IP Protection.
IEEE Trans. Very Large Scale Integr. Syst.
Md. Moshiur Rahman, Swarup Bhunia
2024 J jnl
Quantum-Safe Internet of Things.
IEEE Des. Test
Anupam Chattopadhyay, Shivam Bhasin, Tim Güneysu, Swarup Bhunia
2024 — conf
SAMURAI: A Framework for Safeguarding Against Malicious Usage and Resilience of AI.
ATS
Habibur Rahaman, Atri Chatterjee, Swarup Bhunia
2024 J jnl
SPELL: An End-to-End Tool Flow for LLM-Guided Secure SoC Design for Embedded Systems.
IEEE Embed. Syst. Lett.
Sudipta Paria, Aritra Dasgupta, Swarup Bhunia
2024 J jnl
Scalable and Programmable Look-Up Table based Neural Acceleration (LUT-NA) for Extreme Energy Efficiency.
CoRR
Ovishake Sen, Chukwufumnanya Ogbogu, Peyman Dehghanzadeh, Janardhan Rao Doppa, Swarup Bhunia, Partha Pratim Pande, Baibhab Chatterjee
2024 — conf
Secure AI Systems: Emerging Threats and Defense Mechanisms.
ATS
Habibur Rahaman, Atri Chatterjee, Swarup Bhunia
2024 J jnl
Security Evaluation of State Space Obfuscation of Hardware IP through a Red Team-Blue Team Practice.
ACM Trans. Design Autom. Electr. Syst.
Md. Moshiur Rahman, Jim Geist, Daniel Xing, Yuntao Liu, Ankur Srivastava, Travis Meade, Yier Jin, Swarup Bhunia
2024 J jnl
Special Issue on Postquantum Cryptography for Internet of Things.
IEEE Des. Test
Shivam Bhasin, Anupam Chattopadhyay, Tim Güneysu, Swarup Bhunia
2024 — conf
Splitting the Secrets: A Cooperative Trust Model for System-on-Chip Designs with Untrusted IPs.
ISVLSI
Aritra Dasgupta, Sudipta Paria, Prabuddha Chakraborty, Swarup Bhunia
2024 — conf
Trimming The Fat: A Minimum-Security Architecture for Protecting SoC Designs Against Supply Chain Threats.
ISQED
Kshitij Raj, Aritra Bhattacharyay, Swarup Bhunia, Sandip Ray
2024 J jnl
VALIANT: An EDA Flow for Side-Channel Leakage Evaluation and Tailored Protection.
IEEE Trans. Computers
Rajat Sadhukhan, Sayandeep Saha, Sudipta Paria, Swarup Bhunia, Debdeep Mukhopadhyay
2024 J jnl
X-DFS: Explainable Artificial Intelligence Guided Design-for-Security Solution Space Exploration.
CoRR
Tanzim Mahfuz, Swarup Bhunia, Prabuddha Chakraborty
2023 J jnl
A Framework for Automated Exploration of Trojan Attack Space in FPGA Netlists.
IEEE Trans. Computers
Jonathan Cruz, Christopher Posada, Naren Vikram Raj Masna, Prabuddha Chakraborty, Pravin Gaikwad, Swarup Bhunia
2023 J jnl
An Automated Framework for Board-Level Trojan Benchmarking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Aritra Bhattacharyay, Shuo Yang, Jonathan Cruz, Prabuddha Chakraborty, Swarup Bhunia, Tamzidul Hoque
2023 Misc conf
An Exploration of ATPG Methods for Redacted IP and Reconfigurable Hardware.
VTS
Jackson Fugate, Greg Stitt, Naren Vikram Raj Masna, Aritra Dasgupta, Swarup Bhunia, Nij Dorairaj, David Kehlet
2023 J jnl
Contact-Less Integrity Verification of Microelectronics Using Near-Field EM Analysis.
IEEE Access
Junjun Huan, Peyman Dehghanzadeh, Soumyajit Mandal, Swarup Bhunia
2023 J jnl
CurIAs: Current-Based IC Authentication by Exploiting Supply Current Variations.
IEEE Trans. Computers
Shubhra Deb Paul, Swarup Bhunia
2023 J jnl
DIVAS: An LLM-based End-to-End Framework for SoC Security Analysis and Policy-based Protection.
CoRR
Sudipta Paria, Aritra Dasgupta, Swarup Bhunia
2023 J jnl
DiSPEL: Distributed Security Policy Enforcement for Bus-based SoC.
CoRR
Sudipta Paria, Swarup Bhunia
2023 B conf
Energy Efficient Memory-based Inference of LSTM by Exploiting FPGA Overlay.
IJCNN
Krishnendu Guha, Amit Ranjan Trivedi, Swarup Bhunia
2023 J jnl
Hardware IP Assurance against Trojan Attacks with Machine Learning and Post-processing.
ACM J. Emerg. Technol. Comput. Syst.
Pravin Gaikwad, Jonathan Cruz, Prabuddha Chakraborty, Swarup Bhunia, Tamzidul Hoque
2023 — conf
Hardware Specification Aware Timing Side Channel Security Analysis.
SOCC
Prabuddha Chakraborty, Tasneem Suha, Swarup Bhunia
2023 Misc ed.
International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2023, Hamburg, Germany, September 17-22, 2023
CASES
Jana Doppa, Swarup Bhunia
2023 J jnl
LUNA-CIM: Lookup Table based Programmable Neural Processing in Memory.
CoRR
Peyman Dehghanzadeh, Baibhab Chatterjee, Swarup Bhunia
2023 J jnl
On-Chip Batteries as Distributed Energy Sources in Heterogeneous 2.5D/3D Integrated Circuits.
IEEE Access
Peyman Dehghanzadeh, Junjun Huan, Rohan Reddy Kalavakonda, Soumyajit Mandal, Swarup Bhunia
2023 J jnl
SAVIOR: A Sustainable Network of Vehicles with Near-Perpetual Mobility.
IEEE Internet Things Mag.
Prabuddha Chakraborty, Reiner N. Dizon-Paradis, Swarup Bhunia
2023 J jnl
SIGNED: A Challenge-Response Scheme for Electronic Hardware Watermarking.
IEEE Trans. Computers
Patanjali SLPSK, Abhishek Anil Nair, Chester Rebeiro, Swarup Bhunia
2023 J jnl
TREEHOUSE: A Secure Asset Management Infrastructure for Protecting 3DIC Designs.
IEEE Trans. Computers
Patanjali SLPSK, Sandip Ray, Swarup Bhunia
2023 J jnl
TVF: A Metric for Quantifying Vulnerability Against Hardware Trojan Attacks.
IEEE Trans. Very Large Scale Integr. Syst.
Jonathan Cruz, Patanjali SLPSK, Pravin Gaikwad, Swarup Bhunia
2023 J jnl
Towards Model-Size Agnostic, Compute-Free, Memorization-based Inference of Deep Learning.
CoRR
Davide Giacomini, Maeesha Binte Hashem, Jeremiah Suarez, Swarup Bhunia, Amit Ranjan Trivedi
2023 Misc conf
Unifying Intrinsically-Operated Physically Unclonable Function and Random Number Generation in Analog Circuits: A Case Study on Successive Approximation ADC.
VLSID
Ahish Shylendra, Swarup Bhunia, Amit Ranjan Trivedi
2022 — conf
A Machine Learning Based Automatic Hardware Trojan Attack Space Exploration and Benchmarking Framework.
AsianHOST
Jonathan Cruz, Pravin Gaikwad, Abhishek Anil Nair, Prabuddha Chakraborty, Swarup Bhunia
2022 A conf
AI-Driven Assurance of Hardware IP against Reverse Engineering Attacks.
ITC
Prabuddha Chakraborty, Swarup Bhunia
2022 J jnl
ARTS: A Framework for AI-Rooted IoT System Design Automation.
IEEE Embed. Syst. Lett.
Prabuddha Chakraborty, Reiner N. Dizon-Paradis, Swarup Bhunia
2022 — conf
Analog-Domain Time-Series Moment Extraction for Low Power Predictive Maintenance Analytics.
AICAS
Ahish Shylendra, Priyesh Shukla, Swarup Bhunia, Amit Ranjan Trivedi
2022 — conf
Analysis of Hardware Trojan Resilience Enabled through Logic Locking.
AsianHOST
Jonathan Cruz, Pravin Gaikwad, Swarup Bhunia
2022 J jnl
Automatic Hardware Trojan Insertion using Machine Learning.
CoRR
Jonathan Cruz, Pravin Gaikwad, Abhishek Nair, Prabuddha Chakraborty, Swarup Bhunia
2022 J jnl
BINGO: brain-inspired learning memory.
Neural Comput. Appl.
Prabuddha Chakraborty, Swarup Bhunia
2022 — conf
FORTIFY: Analytical Pre-Silicon Side-Channel Characterization of Digital Designs.
ASP-DAC
A. V. Lakshmy, Chester Rebeiro, Swarup Bhunia
2022 J jnl
Golden-Free Hardware Trojan Detection Using Self-Referencing.
IEEE Trans. Very Large Scale Integr. Syst.
Shuo Yang, Tamzidul Hoque, Prabuddha Chakraborty, Swarup Bhunia
2022 J jnl
HASTE: Software Security Analysis for Timing Attacks on Clear Hardware Assumption.
IEEE Embed. Syst. Lett.
Prabuddha Chakraborty, Jonathan Cruz, Christopher Posada, Sandip Ray, Swarup Bhunia
2022 — ch.
Hardware IP Protection Using Register Transfer Level Locking and Obfuscation of Control and Data Flow.
Behavioral Synthesis for Hardware Security
Pranesh Santikellur, Rajat Subhra Chakraborty, Swarup Bhunia
2022 A conf
Hardware IP Protection against Confidentiality Attacks and Evolving Role of CAD Tool.
ICCAD
Swarup Bhunia, Amitabh Das, Saverio Fazzari, Vivian Kammler, David Kehlet, Jeyavijayan Rajendran, Ankur Srivastava
2022 J jnl
Intrinsically Secure Non-Volatile Memory Using ReRAM Devices.
IEEE Access
Junjun Huan, Nicholas Olexa, Brett Hochman, Swarup Bhunia, Rashmi Jha, Soumyajit Mandal
2022 J jnl
LeGO: A Learning-Guided Obfuscation Framework for Hardware IP Protection.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Abdulrahman Alaql, Saranyu Chattopadhyay, Prabuddha Chakraborty, Tamzidul Hoque, Swarup Bhunia
2022 — conf
Light Pollution Monitoring Using A Modular IoT Sensor Platform.
SmartIoT
Reiner N. Dizon-Paradis, Oliver Ferrigno, Ishamor Reid, Swarup Bhunia
2022 J jnl
RIHANN: Remote IoT Hardware Authentication With Intrinsic Identifiers.
IEEE Internet Things J.
Shubhra Deb Paul, Fengchao Zhang, Patanjali SLPSK, Amit Ranjan Trivedi, Swarup Bhunia
2022 Misc conf
SEVA: Structural Analysis based Security Evaluation of Sequential Locking.
VLSID
Abdulrahman Alaql, Aritra Dasgupta, Md. Moshiur Rahman, Swarup Bhunia
2022 J jnl
SoCCom: Automated Synthesis of System-on-Chip Architectures.
IEEE Trans. Very Large Scale Integr. Syst.
Atul Prasad Deb Nath, Kshitij Raj, Swarup Bhunia, Sandip Ray
2022 J jnl
Trojan Resilient Computing in COTS Processors Under Zero Trust.
IEEE Trans. Very Large Scale Integr. Syst.
Mahmudul Hasan, Jonathan Cruz, Prabuddha Chakraborty, Swarup Bhunia, Tamzidul Hoque
2022 A* conf
VIPR-PCB: a machine learning based golden-free PCB assurance framework.
DAC
Aritra Bhattacharyay, Prabuddha Chakraborty, Jonathan Cruz, Swarup Bhunia
2021 J jnl
A Smart Mask for Active Defense Against Coronaviruses and Other Airborne Pathogens.
IEEE Consumer Electron. Mag.
Rohan Reddy Kalavakonda, Naren Vikram Raj Masna, Anamika Bhuniaroy, Soumyajit Mandal, Swarup Bhunia
2021 J jnl
An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wei Hu, Chip-Hong Chang, Anirban Sengupta, Swarup Bhunia, Ryan Kastner, Hai Li
2021 A conf
CASTLE: Architecting Assured System-on-Chip Firmware Integrity.
DATE
Sandip Ray, Atul Prasad Deb Nath, Kshitij Raj, Swarup Bhunia
2021 J jnl
FaultDroid: An Algorithmic Approach for Fault-Induced Information Leakage Analysis.
ACM Trans. Design Autom. Electr. Syst.
Indrani Roy, Chester Rebeiro, Aritra Hazra, Swarup Bhunia
2021 J jnl
MAGIC: Machine-Learning-Guided Image Compression for Vision Applications in Internet of Things.
IEEE Internet Things J.
Prabuddha Chakraborty, Jonathan Cruz, Swarup Bhunia
2021 J jnl
Neural Storage: A New Paradigm of Elastic Memory.
CoRR
Prabuddha Chakraborty, Swarup Bhunia
2021 J jnl
On Database-Free Authentication of Microelectronic Components.
IEEE Trans. Very Large Scale Integr. Syst.
Fengchao Zhang, Shubhra Deb Paul, Patanjali SLPSK, Amit Ranjan Trivedi, Swarup Bhunia
2021 J jnl
SAIL: Analyzing Structural Artifacts of Logic Locking Using Machine Learning.
IEEE Trans. Inf. Forensics Secur.
Prabuddha Chakraborty, Jonathan Cruz, Abdulrahman Alaql, Swarup Bhunia
2021 J jnl
SARO: Scalable Attack-Resistant Logic Locking.
IEEE Trans. Inf. Forensics Secur.
Abdulrahman Alaql, Swarup Bhunia
2021 J jnl
SCOPE: Synthesis-Based Constant Propagation Attack on Logic Locking.
IEEE Trans. Very Large Scale Integr. Syst.
Abdulrahman Alaql, Md. Moshiur Rahman, Swarup Bhunia
2021 J jnl
SILVerIn: Systematic Integrity Verification of Printed Circuit Board Using JTAG Infrastructure.
ACM J. Emerg. Technol. Comput. Syst.
Shubhra Deb Paul, Swarup Bhunia
2021 — conf
SOMA: Security Evaluation of Obfuscation Methods via Attack Sequencing.
ISQED
Abdulrahman Alaql, Xinmu Wang, Md. Moshiur Rahman, Swarup Bhunia
2021 — conf
SSEL: An Extensible Specification Language for SoC Security.
AsianHOST
Kshitij Raj, Arrush Hegde, Atul Prasad Deb Nath, Swarup Bhunia, Sandip Ray
2021 — conf
Smart and Connected Mask for Protection beyond the Pandemic : (Invited Paper).
MWSCAS
Naren Vikram Raj Masna, Rohan Reddy Kalavakonda, Reiner Dizon, Swarup Bhunia
2021 J jnl
Software Variants for Hardware Trojan Detection and Resilience in COTS Processors.
CoRR
Mahmudul Hasan, Jonathan Cruz, Prabuddha Chakraborty, Swarup Bhunia, Tamzidul Hoque
2021 — conf
The Curious Case of Trusted IC Provisioning in Untrusted Testing Facilities.
ACM Great Lakes Symposium on VLSI
Sandip Ray, Atul Prasad Deb Nath, Kshitij Raj, Swarup Bhunia
2021 J jnl
Third-Party Hardware IP Assurance against Trojans through Supervised Learning and Post-processing.
CoRR
Pravin Gaikwad, Jonathan Cruz, Prabuddha Chakraborty, Swarup Bhunia, Tamzidul Hoque
2021 — conf
Trusted Electronic Systems with Untrusted COTS.
ISQED
Shuo Yang, Prabuddha Chakraborty, Patanjali SLPSK, Swarup Bhunia
2020 J jnl
An Automated Framework for Board-level Trojan Benchmarking.
CoRR
Tamzidul Hoque, Shuo Yang, Aritra Bhattacharyay, Jonathan Cruz, Swarup Bhunia
2020 J jnl
Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking.
CoRR
Benjamin Tan, Ramesh Karri, Nimisha Limaye, Abhrajit Sengupta, Ozgur Sinanoglu, Md. Moshiur Rahman, Swarup Bhunia, Danielle Duvalsaint, Ronald D. Blanton, Amin Rezaei, Yuanqi Shen, Hai Zhou, Leon Li, Alex Orailoglu, Zhaokun Han, Austin Benedetti, Luciano Brignone, Muhammad Yasin, Jeyavijayan Rajendran, Michael Zuzak, Ankur Srivastava, Ujjwal Guin, Chandan Karfa, Kanad Basu, Vivek V. Menon, Matthew French, Peilin Song, Franco Stellari, Gi-Joon Nam, Peter Gadfort, Alric Althoff, Joseph Tostenrude, Saverio Fazzari, Eric Breckenfeld, Kenneth Plaks
2020 J jnl
FEDS: Comprehensive Fault Attack Exploitability Detection for Software Implementations of Block Ciphers.
IACR Trans. Cryptogr. Hardw. Embed. Syst.
Keerthi K., Indrani Roy, Chester Rebeiro, Aritra Hazra, Swarup Bhunia
2020 — conf
Fault Attack Detection in AES by Monitoring Power Side-Channel Statistics.
ISQED
Ahish Shylendra, Priyesh Shukla, Swarup Bhunia, Amit Ranjan Trivedi
2020 J jnl
Guest Editorial: ACM JETC Special Issue on New Trends in Nanolectronic Device, Circuit, and Architecture Design: Part 2.
ACM J. Emerg. Technol. Comput. Syst.
Wei Zhang, Hai Helen Li, Wujie Wen, Swarup Bhunia
2020 J jnl
Hardware Obfuscation and Logic Locking: A Tutorial Introduction.
IEEE Des. Test
Tamzidul Hoque, Rajat Subhra Chakraborty, Swarup Bhunia
2020 J jnl
Hardware Trojan Attack in Embedded Memory.
ACM J. Emerg. Technol. Comput. Syst.
Xinmu Wang, Tamzidul Hoque, Abhishek Basak, Robert Karam, Wei Hu, Maoyuan Qin, Dejun Mu, Swarup Bhunia
2020 J jnl
Hidden in Plaintext: An Obfuscation-based Countermeasure against FPGA Bitstream Tampering Attacks.
ACM Trans. Design Autom. Electr. Syst.
Tamzidul Hoque, Kai Yang, Robert Karam, Shahin Tajik, Domenic Forte, Mark Tehranipoor, Swarup Bhunia
2020 J jnl
Introduction to the Special Issue on New Trends in Nanoelectronic Device, Circuit, and Architecture Design, Part 1.
ACM J. Emerg. Technol. Comput. Syst.
Hai Helen Li, Wei Zhang, Swarup Bhunia, Wujie Wen
2020 J jnl
Leveraging Domain Knowledge using Machine Learning for Image Compression in Internet-of-Things.
CoRR
Prabuddha Chakraborty, Jonathan Cruz, Swarup Bhunia
2020 J jnl
Low Power Unsupervised Anomaly Detection by Non-Parametric Modeling of Sensor Statistics.
CoRR
Ahish Shylendra, Priyesh Shukla, Saibal Mukhopadhyay, Swarup Bhunia, Amit Ranjan Trivedi
2020 J jnl
Low Power Unsupervised Anomaly Detection by Nonparametric Modeling of Sensor Statistics.
IEEE Trans. Very Large Scale Integr. Syst.
Ahish Shylendra, Priyesh Shukla, Saibal Mukhopadhyay, Swarup Bhunia, Amit Ranjan Trivedi
2020 J jnl
MeLPUF: Memory in Logic PUF.
CoRR
Christopher Vega, Patanjali SLPSK, Shubhra Deb Paul, Swarup Bhunia
2020 — conf
P2C2: Peer-to-Peer Car Charging.
VTC Spring
Prabuddha Chakraborty, Robert Parker, Tamzidul Hoque, Jonathan Cruz, Swarup Bhunia
2020 J jnl
Resilient System-on-Chip Designs With NoC Fabrics.
IEEE Trans. Inf. Forensics Secur.
Atul Prasad Deb Nath, Srivalli Boddupalli, Swarup Bhunia, Sandip Ray
2020 J jnl
SAFARI: Automatic Synthesis of Fault-Attack Resistant Block Cipher Implementations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Indrani Roy, Chester Rebeiro, Aritra Hazra, Swarup Bhunia
2020 J jnl
SIGNED: A Challenge-Response Based Interrogation Scheme for Simultaneous Watermarking and Trojan Detection.
CoRR
Abhishek Nair, Patanjali SLPSK, Chester Rebeiro, Swarup Bhunia
2020 A conf
SOLOMON: An Automated Framework for Detecting Fault Attack Vulnerabilities in Hardware.
DATE
Milind Srivastava, Patanjali SLPSK, Indrani Roy, Chester Rebeiro, Aritra Hazra, Swarup Bhunia
2020 J jnl
Scalable Attack-Resistant Obfuscation of Logic Circuits.
CoRR
Abdulrahman Alaql, Swarup Bhunia
2020 — conf
Trust Issues in COTS: The Challenges and Emerging Solution.
ACM Great Lakes Symposium on VLSI
Tamzidul Hoque, Patanjali SLPSK, Swarup Bhunia
2020 J jnl
Trust Issues in Microelectronics: The Concerns and the Countermeasures.
IEEE Consumer Electron. Mag.
Tamzidul Hoque, Patanjali SLPSK, Swarup Bhunia
2019 — ch.
An Adaptable System-on-Chip Security Architecture for Internet of Things Applications.
Security and Fault Tolerance in Internet of Things
Atul Prasad Deb Nath, Tamzidul Hoque, Sandip Ray, Swarup Bhunia
2019 J jnl
An Intrinsic and Database-Free Authentication by Exploiting Process Variation in Back-End Capacitors.
IEEE Trans. Very Large Scale Integr. Syst.
Ahish Shylendra, Swarup Bhunia, Amit Ranjan Trivedi
2019 J jnl
Early Detection of Cardiovascular Diseases Using Wearable Ultrasound Device.
IEEE Consumer Electron. Mag.
Sumaiya Shomaji, Parisa Dehghanzadeh, Alex Roman, Domenic Forte, Swarup Bhunia, Soumyajit Mandal
2019 J jnl
Eat, but Verify: Low-Cost Portable Devices for Food Safety Analysis.
IEEE Consumer Electron. Mag.
Naren Vikram Raj Masna, Shubhra Deb Paul, Cheng Chen, Soumyajit Mandal, Swarup Bhunia
2019 J jnl
Guest Editorial: Special Section on Autonomous Intelligence for Security and Privacy Analytics.
IEEE Trans. Very Large Scale Integr. Syst.
Prabhat Mishra, Debdeep Mukhopadhyay, Swarup Bhunia
2019 A conf
IEEE International Symposium on Hardware Oriented Security and Trust (HOST): Past, Present, and Future.
ITC
Domenic Forte, Swarup Bhunia, Ramesh Karri, Jim Plusquellic, Mark Tehranipoor
2019 — conf
Innovations in IoT for a Safe, Secure, and Sustainable Future.
ACM Great Lakes Symposium on VLSI
Swarup Bhunia
2019 — conf
New Frontiers in Hardware Security in the IoT Regime.
CICC
Swarup Bhunia
2019 Misc conf
Quality Obfuscation for Error-Tolerant and Adaptive Hardware IP Protection.
VTS
Abdulrahman Alaql, Tamzidul Hoque, Domenic Forte, Swarup Bhunia
2019 J jnl
Robust Authentication of Consumables With Extrinsic Tags and Chemical Fingerprinting.
IEEE Access
Naren Vikram Raj Masna, Cheng Chen, Soumyajit Mandal, Swarup Bhunia
2019 C conf
Runtime Integrity Verification in Cyber-physical Systems using Side-Channel Fingerprint.
ICCE
Shuo Yang, Abdulrahman Alaql, Tamzidul Hoque, Swarup Bhunia
2019 A conf
SCR-QRNG: Side-Channel Resistant Design using Quantum Random Number Generator.
ICCAD
Jungmin Park, Seongjoon Cho, Taejin Lim, Swarup Bhunia, Mark Tehranipoor
2019 — conf
SURF: Joint Structural Functional Attack on Logic Locking.
HOST
Prabuddha Chakraborty, Jonathan Cruz, Swarup Bhunia
2019 Misc conf
Special Session: Countering IP Security threats in Supply chain.
VTS
Hassan Salmani, Tamzidul Hoque, Swarup Bhunia, Muhammad Yasin, Jeyavijayan (JV) Rajendran, Naghmeh Karimi
2019 — conf
Sweep to the Secret: A Constant Propagation Attack on Logic Locking.
AsianHOST
Abdulrahman Alaql, Domenic Forte, Swarup Bhunia
2019 A* conf
The Metric Matters: The Art of Measuring Trust in Electronics.
DAC
Jonathan Cruz, Prabhat Mishra, Swarup Bhunia
2018 — conf
An Open-Source Test-Bench for Autonomous Ultrasound Imaging.
MWSCAS
Alex Roman, Parisa Dehghanzadeh, Vida Pashaei, Abhishek Basak, Swarup Bhunia, Soumyajit Mandal
2018 A conf
An automated configurable Trojan insertion framework for dynamic trust benchmarks.
DATE
Jonathan Cruz, Yuanwen Huang, Prabhat Mishra, Swarup Bhunia
2018 — conf
ArtiFact: Architecture and CAD Flow for Efficient Formal Verification of SoC Security Policies.
ISVLSI
Atul Prasad Deb Nath, Swarup Bhunia, Sandip Ray
2018 J jnl
Development and Evaluation of Hardware Obfuscation Benchmarks.
J. Hardw. Syst. Secur.
Sarah Amir, Bicky Shakya, Xiaolin Xu, Yier Jin, Swarup Bhunia, Mark Tehranipoor, Domenic Forte
2018 A conf
Hardware IP Trust Validation: Learn (the Untrustworthy), and Verify.
ITC
Tamzidul Hoque, Jonathan Cruz, Prabuddha Chakraborty, Swarup Bhunia
2018 Misc conf
Hardware Trojan attacks in embedded memory.
VTS
Tamzidul Hoque, Xinmu Wang, Abhishek Basak, Robert Karam, Swarup Bhunia
2018 — conf
Hardware virtualization for protection against power analysis attack.
HOST
Kai Yang, Jungmin Park, Mark Tehranipoor, Swarup Bhunia
2018 J jnl
Hardware-Enabled Pharmaceutical Supply Chain Security.
ACM Trans. Design Autom. Electr. Syst.
Kun Yang, Hao-Ting Shen, Domenic Forte, Swarup Bhunia, Mark Tehranipoor
2018 C conf
Internet of Things security: Are we paranoid enough?
ICCE
Swarup Bhunia
2018 A conf
Intrinsic and Database-free Watermarking in ICs by Exploiting Process and Design Dependent Variability in Metal-Oxide-Metal Capacitances.
ISLPED
Ahish Shylendra, Swarup Bhunia, Amit Ranjan Trivedi
2018 C conf
Keynotes.
ICCE
Linus Torvalds, Niraj K. Jha, Gary Davis, Nasir D. Memon, Petronel Bigioi, Swarup Bhunia, Koji Nakao
2018 — conf
Multi-Mode Micromechanical Resonant Tags for Traceability and Authentication Applications.
NEMS
Angela R. Newsome, Mehrdad Ramezani, Mayur Ghatge, Fengchao Zhang, Swarup Bhunia, Roozbeh Tabrizian
2018 — conf
Robust Timing Attack Countermeasure on Virtual Hardware.
ISVLSI
Kai Yang, Jungmin Park, Mark Tehranipoor, Swarup Bhunia
2018 — conf
SAIL: Machine Learning Guided Structural Analysis Attack on Hardware Obfuscation.
AsianHOST
Prabuddha Chakraborty, Jonathan Cruz, Swarup Bhunia
2018 J jnl
SAIL: Machine Learning Guided Structural Analysis Attack on Hardware Obfuscation.
CoRR
Prabuddha Chakraborty, Jonathan Cruz, Swarup Bhunia
2018 J jnl
Scalable Test Generation for Trojan Detection Using Side Channel Analysis.
IEEE Trans. Inf. Forensics Secur.
Yuanwen Huang, Swarup Bhunia, Prabhat Mishra
2018 — conf
Securing the Systems of the Future - Techniques for a Shifting Attack Space.
ACM Great Lakes Symposium on VLSI
Ioannis Savidis, Swarup Bhunia, Gang Qu, Matthew J. Casto, Jeremy Muldavin
2018 J jnl
System-on-Chip Platform Security Assurance: Architecture and Validation.
Proc. IEEE
Sandip Ray, Eric Peeters, Mark Tehranipoor, Swarup Bhunia
2018 — conf
System-on-chip security architecture and CAD framework for hardware patch.
ASP-DAC
Atul Prasad Deb Nath, Sandip Ray, Abhishek Basak, Swarup Bhunia
2017 J jnl
A Security Perspective on Battery Systems of the Internet of Things.
J. Hardw. Syst. Secur.
Anthony Bahadir Lopez, Korosh Vatanparvar, Atul Prasad Deb Nath, Shuo Yang, Swarup Bhunia, Mohammad Abdullah Al Faruque
2017 J jnl
A Uniquified Virtualization Approach to Hardware Security.
IEEE Embed. Syst. Lett.
Greg Stitt, Robert Karam, Kai Yang, Swarup Bhunia
2017 — conf
A solitary protection measure against scan chain, fault injection, and power analysis attacks on AES.
MWSCAS
Tonmoy Dhar, Swarup Bhunia, Amit Ranjan Trivedi
2017 — conf
ATAVE: A framework for automatic timing attack vulnerability evaluation.
MWSCAS
Jungmin Park, Massimiliano Corba, Antonio E. de la Sema, Richard L. Vigeant, Mark Tehranipoor, Swarup Bhunia
2017 J jnl
Adaptive ECC for Tailored Protection of Nanoscale Memory.
IEEE Des. Test
Dongyeob Shin, Jongsun Park, Jangwon Park, Somnath Paul, Swarup Bhunia
2017 — conf
Authentication and traceability of food products through the supply chain using NQR spectroscopy.
BioCAS
Fengchao Zhang, Naren Vikram Raj Masna, Swarup Bhunia, Cheng Chen, Soumyajit Mandal
2017 J jnl
Benchmarking of Hardware Trojans and Maliciously Affected Circuits.
J. Hardw. Syst. Secur.
Bicky Shakya, Miao Tony He, Hassan Salmani, Domenic Forte, Swarup Bhunia, Mark Tehranipoor
2017 — conf
Comparative Analysis of Hardware Obfuscation for IP Protection.
ACM Great Lakes Symposium on VLSI
Sarah Amir, Bicky Shakya, Domenic Forte, Mark Tehranipoor, Swarup Bhunia
2017 J jnl
ENFIRE: A Spatio-Temporal Fine-Grained Reconfigurable Hardware.
IEEE Trans. Very Large Scale Integr. Syst.
Wenchao Qian, Christopher Babecki, Robert Karam, Somnath Paul, Swarup Bhunia
2017 J jnl
Editorial for the Introductory Issue of the
J. Hardw. Syst. Secur.
Swarup Bhunia, Mark Tehranipoor
2017 J jnl
Energy-Efficient Adaptive Computing With Multifunctional Memory.
IEEE Trans. Circuits Syst. II Express Briefs
Wenchao Qian, Pai-Yu Chen, Robert Karam, Ligang Gao, Swarup Bhunia, Shimeng Yu
2017 J jnl
Energy-Efficient Reconfigurable Hardware Accelerators for Data-Intensive Applications.
J. Low Power Electron.
Kai Yang, Robert Karam, Swarup Bhunia
2017 J jnl
Golden-Free Hardware Trojan Detection with High Sensitivity Under Process Noise.
J. Electron. Test.
Tamzidul Hoque, Seetharam Narasimhan, Xinmu Wang, Sanchita Mal-Sarkar, Swarup Bhunia
2017 J jnl
Guest Editors Introduction: Security of Beyond CMOS Devices: Issues and Opportunities.
IEEE Trans. Emerg. Top. Comput.
Swarup Bhunia, An Chen, Ozgur Sinanoglu, Jason M. Fung
2017 — conf
Interleaved logic-in-memory architecture for energy-efficient fine-grained data processing.
MWSCAS
Kai Yang, Robert Karam, Swarup Bhunia
2017 — conf
MUTARCH: Architectural diversity for FPGA device and IP security.
ASP-DAC
Robert Karam, Tamzidul Hoque, Sandip Ray, Mark Tehranipoor, Swarup Bhunia
2017 J jnl
Memory-Centric Reconfigurable Accelerator for Classification and Machine Learning Applications.
ACM J. Emerg. Technol. Comput. Syst.
Robert Karam, Somnath Paul, Ruchir Puri, Swarup Bhunia
2017 — conf
Mixed-granular architectural diversity for device security in the Internet of Things.
AsianHOST
Robert Karam, Tamzidul Hoque, Kevin R. B. Butler, Swarup Bhunia
2017 J jnl
SMA: A System-Level Mutual Authentication for Protecting Electronic Hardware and Firmware.
IEEE Trans. Dependable Secur. Comput.
Ujjwal Guin, Swarup Bhunia, Domenic Forte, Mark Tehranipoor
2017 J jnl
Security Assurance for System-on-Chip Designs With Untrusted IPs.
IEEE Trans. Inf. Forensics Secur.
Abhishek Basak, Swarup Bhunia, Thomas E. Tkacik, Sandip Ray
2017 — conf
Security vulnerability analysis of design-for-test exploits for asset protection in SoCs.
ASP-DAC
Gustavo K. Contreras, Adib Nahiyan, Swarup Bhunia, Domenic Forte, Mark Tehranipoor
2017 J jnl
Tunable and Lightweight On-Chip Event Detection for Implantable Bladder Pressure Monitoring Devices.
IEEE Trans. Biomed. Circuits Syst.
Robert Karam, Steve J. A. Majerus, Dennis Bourbeau, Margot S. Damaser, Swarup Bhunia
2016 — ed.
2016 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2016, McLean, VA, USA, May 3-5, 2016
HOST
William H. Robinson, Swarup Bhunia, Ryan Kastner
2016 — conf
Active protection against PCB physical tampering.
ISQED
Steven Paley, Tamzidul Hoque, Swarup Bhunia
2016 J jnl
An Embedded Memory-Centric Reconfigurable Hardware Accelerator for Security Applications.
IEEE Trans. Computers
Christopher Babecki, Wenchao Qian, Somnath Paul, Robert Karam, Swarup Bhunia
2016 J jnl
Authentication of Medicines Using Nuclear Quadrupole Resonance Spectroscopy.
IEEE ACM Trans. Comput. Biol. Bioinform.
Cheng Chen, Fengchao Zhang, Jamie Barras, Kaspar Althoefer, Swarup Bhunia, Soumyajit Mandal
2016 A conf
Current based PUF exploiting random variations in SRAM cells.
DATE
Fengchao Zhang, Shuo Yang, Jim Plusquellic, Swarup Bhunia
2016 J jnl
DScanPUF: A Delay-Based Physical Unclonable Function Built Into Scan Chain.
IEEE Trans. Very Large Scale Integr. Syst.
Yu Zheng, Fengchao Zhang, Swarup Bhunia
2016 J jnl
Design and Validation for FPGA Trust under Hardware Trojan Attacks.
IEEE Trans. Multi Scale Comput. Syst.
Sanchita Mal-Sarkar, Robert Karam, Seetharam Narasimhan, Anandaroop Ghosh, Aswin Raghav Krishna, Swarup Bhunia
2016 A conf
ENFIRE: An Energy-efficient Fine-grained Spatio-temporal Reconfigurable Computing Fabric (Abstact Only).
FPGA
Wenchao Qian, Christopher Babecki, Robert Karam, Swarup Bhunia
2016 J jnl
Energy-Efficient Adaptive Hardware Accelerator for Text Mining Application Kernels.
IEEE Trans. Very Large Scale Integr. Syst.
Robert Karam, Ruchir Puri, Swarup Bhunia
2016 A* conf
Exploiting design-for-debug for flexible SoC security architecture.
DAC
Abhishek Basak, Swarup Bhunia, Sandip Ray
2016 J jnl
Foundations of Secure Scaling (Dagstuhl Seminar 16342).
Dagstuhl Reports
Lejla Batina, Swarup Bhunia, Patrick Schaumont, Jean-Pierre Seifert
2016 J jnl
Hardware Trojans: Lessons Learned after One Decade of Research.
ACM Trans. Design Autom. Electr. Syst.
Kan Xiao, Domenic Forte, Yier Jin, Ramesh Karri, Swarup Bhunia, Mark Tehranipoor
2016 — conf
JTAG-based robust PCB authentication for protection against counterfeiting attacks.
ASP-DAC
Andrew Hennessy, Yu Zheng, Swarup Bhunia
2016 A* conf
MERS: Statistical Test Generation for Side-Channel Analysis based Trojan Detection.
CCS
Yuanwen Huang, Swarup Bhunia, Prabhat Mishra
2016 A conf
On detecting delay anomalies introduced by hardware trojans.
ICCAD
Dylan Ismari, Jim Plusquellic, Charles Lamech, Swarup Bhunia, Fareena Saqib
2016 J jnl
P-Val: Antifuse-Based Package-Level Defense Against Counterfeit ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Abhishek Basak, Swarup Bhunia
2016 J jnl
Real-Time Classification of Bladder Events for Effective Diagnosis and Treatment of Urinary Incontinence.
IEEE Trans. Biomed. Eng.
Robert Karam, Dennis Bourbeau, Steve J. A. Majerus, Iryna Makovey, Howard B. Goldman, Margot S. Damaser, Swarup Bhunia
2016 — conf
Real-time, autonomous bladder event classification and closed-loop control from single-channel pressure data.
EMBC
Robert Karam, Swarup Bhunia, Steve J. A. Majerus, Steven W. Brose, Margot S. Damaser, Dennis Bourbeau
2016 — conf
Robust bitstream protection in FPGA-based systems through low-overhead obfuscation.
ReConFig
Robert Karam, Tamzidul Hoque, Sandip Ray, Mark Tehranipoor, Swarup Bhunia
2016 J jnl
SeMIA: Self-Similarity-Based IC Integrity Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yu Zheng, Shuo Yang, Swarup Bhunia
2016 — conf
Security Primitive Design with Nanoscale Devices: A Case Study with Resistive RAM.
ACM Great Lakes Symposium on VLSI
Robert Karam, Rui Liu, Pai-Yu Chen, Shimeng Yu, Swarup Bhunia
2016 Misc conf
Security validation in IoT space.
VTS
Sandip Ray, Swarup Bhunia, Yier Jin, Mark Tehranipoor
2016 J jnl
Supply-Chain Security for Cyberinfrastructure [Guest editors' introduction].
Computer
Domenic Forte, Ron Perez, Yongdae Kim, Swarup Bhunia
2016 — conf
Technical demonstration session: Software toolflow for FPGA bitstream obfuscation.
ReConFig
Robert Karam, Tamzidul Hoque, Sandip Ray, Mark Tehranipoor, Swarup Bhunia
2016 C conf
The power play: Security-energy trade-offs in the IoT regime.
ICCD
Sandip Ray, Tamzidul Hoque, Abhishek Basak, Swarup Bhunia
2016 — conf
Ultralow-power data compression for implantable bladder pressure monitor: Algorithm and hardware implementation.
BioCAS
Robert Karam, Steve J. A. Majerus, Dennis Bourbeau, Margot S. Damaser, Swarup Bhunia
2016 J jnl
Wearables, Implants, and Internet of Things: The Technology Needs in the Evolving Landscape.
IEEE Trans. Multi Scale Comput. Syst.
Sandip Ray, Jongsun Park, Swarup Bhunia
2015 A conf
A Flexible Architecture for Systematic Implementation of SoC Security Policies.
ICCAD
Abhishek Basak, Swarup Bhunia, Sandip Ray
2015 J jnl
A Memory-Based Logic Block With Optimized-for-Read SRAM for Energy-Efficient Reconfigurable Computing Fabric.
IEEE Trans. Circuits Syst. II Express Briefs
Wen Yueh, Subho Chatterjee, Muneeb Zia, Swarup Bhunia, Saibal Mukhopadhyay
2015 A* conf
Correctness and security at odds: post-silicon validation of modern SoC designs.
DAC
Sandip Ray, Jin Yang, Abhishek Basak, Swarup Bhunia
2015 J jnl
Emerging Trends in Design and Applications of Memory-Based Computing and Content-Addressable Memories.
Proc. IEEE
Robert Karam, Ruchir Puri, Swaroop Ghosh, Swarup Bhunia
2015 — conf
Energy-efficient reconfigurable computing using Spintronic memory.
MWSCAS
Robert Karam, Kai Yang, Swarup Bhunia
2015 J jnl
Exploring Spin Transfer Torque Devices for Unconventional Computing.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Kaushik Roy, Deliang Fan, Xuanyao Fong, Yusung Kim, Mrigank Sharad, Somnath Paul, Subho Chatterjee, Swarup Bhunia, Saibal Mukhopadhyay
2015 J jnl
Guest Editorial Computing in Emerging Technologies (Second Issue).
IEEE J. Emerg. Sel. Topics Circuits Syst.
Saibal Mukhopadhyay, Swarup Bhunia, Hillery C. Hunter, Kaushik Roy
2015 J jnl
Guest Editorial Special Section on Hardware Security and Trust.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ramesh Karri, Farinaz Koushanfar, Ozgur Sinanoglu, Yiorgos Makris, Ken Mai, Ahmad-Reza Sadeghi, Swarup Bhunia
2015 J jnl
Guest Editors' Introduction: Wearables, Implants, and Internet of Things.
IEEE Trans. Multi Scale Comput. Syst.
Sandip Ray, Jongsun Park, Swarup Bhunia
2015 J jnl
How Secure Are Printed Circuit Boards Against Trojan Attacks?
IEEE Des. Test
Swaroop Ghosh, Abhishek Basak, Swarup Bhunia
2015 J jnl
IIPS: Infrastructure IP for Secure SoC Design.
IEEE Trans. Computers
Xinmu Wang, Yu Zheng, Abhishek Basak, Swarup Bhunia
2015 J jnl
MAHA: An Energy-Efficient Malleable Hardware Accelerator for Data-Intensive Applications.
IEEE Trans. Very Large Scale Integr. Syst.
Somnath Paul, Aswin Raghav Krishna, Wenchao Qian, Robert Karam, Swarup Bhunia
2015 A conf
PiRA: IC authentication utilizing intrinsic variations in pin resistance.
ITC
Abhishek Basak, Fengchao Zhang, Swarup Bhunia
2015 Misc conf
Robust counterfeit PCB detection exploiting intrinsic trace impedance variations.
VTS
Fengchao Zhang, Andrew Hennessy, Swarup Bhunia
2015 J jnl
SACCI: Scan-Based Characterization Through Clock Phase Sweep for Counterfeit Chip Detection.
IEEE Trans. Very Large Scale Integr. Syst.
Yu Zheng, Xinmu Wang, Swarup Bhunia
2015 A* conf
Self-correcting STTRAM under magnetic field attacks.
DAC
Jae-Won Jang, Jongsun Park, Swaroop Ghosh, Swarup Bhunia
2015 Misc conf
Tutorial T2: Validation and Debug of Security and Trust Issues in Embedded Systems.
VLSID
Prabhat Mishra, Swarup Bhunia, Srivaths Ravi
2014 J jnl
A Variation-Aware Preferential Design Approach for Memory-Based Reconfigurable Computing.
IEEE Trans. Very Large Scale Integr. Syst.
Somnath Paul, Saibal Mukhopadhyay, Swarup Bhunia
2014 A conf
A non-volatile memory based physically unclonable function without helper data.
ICCAD
Wenjie Che, Jim Plusquellic, Swarup Bhunia
2014 Misc conf
Active defense against counterfeiting attacks through robust antifuse-based on-chip locks.
VTS
Abhishek Basak, Yu Zheng, Swarup Bhunia
2014 — conf
Analysis of practical scaling limits in nanoelectromechanical switches.
NEMS
Vaishnavi Nattar Ranganathan, Srihari Rajgopal, Mehran Mehregany, Swarup Bhunia
2014 A* conf
CACI: Dynamic Current Analysis Towards Robust Recycled Chip Identification.
DAC
Yu Zheng, Abhishek Basak, Swarup Bhunia
2014 A conf
Energy-efficient hardware acceleration through computing in the memory.
DATE
Somnath Paul, Robert Karam, Swarup Bhunia, Ruchir Puri
2014 J jnl
Guest Editorial Computing in Emerging Technologies (First Issue).
IEEE J. Emerg. Sel. Topics Circuits Syst.
Saibal Mukhopadhyay, Swarup Bhunia, Hillery C. Hunter, Kaushik Roy
2014 J jnl
Hardware Trojan Attacks: Threat Analysis and Countermeasures.
Proc. IEEE
Swarup Bhunia, Michael S. Hsiao, Mainak Banga, Seetharam Narasimhan
2014 — conf
Hardware trojan attacks in FPGA devices: threat analysis and effective counter measures.
ACM Great Lakes Symposium on VLSI
Sanchita Mal-Sarkar, Aswin Raghav Krishna, Anandaroop Ghosh, Swarup Bhunia
2014 J jnl
Implantable Ultrasonic Imaging Assembly for Automated Monitoring of Internal Organs.
IEEE Trans. Biomed. Circuits Syst.
Abhishek Basak, Vaishnavi Nattar Ranganathan, Swarup Bhunia
2014 J jnl
Improving Energy Efficiency in FPGA Through Judicious Mapping of Computation to Embedded Memory Blocks.
IEEE Trans. Very Large Scale Integr. Syst.
Anandaroop Ghosh, Somnath Paul, Jongsun Park, Swarup Bhunia
2014 — conf
Robust low-power reconfigurable computing with a variation-aware preferential design approach.
ICICDT
Somnath Paul, Saibal Mukhopadhyay, Swarup Bhunia
2014 A conf
Toward ultralow-power computing at exteme with silicon carbide (SiC) nanoelectromechanical logic.
DATE
Swarup Bhunia, Vaishnavi Nattar Ranganathan, Tina He, Srihari Rajgopal, Rui Yang, Mehran Mehregany, Philip X.-L. Feng
2014 — conf
Trade-off between energy and quality of service through dynamic operand truncation and fusion.
ACM Great Lakes Symposium on VLSI
Wenchao Qian, Robert Karam, Swarup Bhunia
2014 J jnl
VL-ECC: Variable Data-Length Error Correction Code for Embedded Memory in DSP Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Jangwon Park, Jongsun Park, Swarup Bhunia
2013 — conf
Content-aware encoding for improving energy efficiency in multi-level cell resistive random access memory.
NANOARCH
Hadi Hajimiri, Prabhat Mishra, Swarup Bhunia, Branden Long, Yibo Li, Rashmi Jha
2013 — conf
Dual-gate silicon carbide (SiC) lateral nanoelectromechanical switches.
NEMS
Tina He, Rui Yang, Srihari Rajgopal, Swarup Bhunia, Mehran Mehregany, Philip X.-L. Feng
2013 Misc conf
Dynamic Cache Tuning for Efficient Memory Based Computing in Multicore Architectures.
VLSI Design
Hadi Hajimiri, Prabhat Mishra, Swarup Bhunia
2013 J jnl
Hardware Trojan Detection by Multiple-Parameter Side-Channel Analysis.
IEEE Trans. Computers
Seetharam Narasimhan, Dongdong Du, Rajat Subhra Chakraborty, Somnath Paul, Francis G. Wolff, Christos A. Papachristou, Kaushik Roy, Swarup Bhunia
2013 — conf
Nanomechanical non-volatile memory for computing at extreme.
NANOARCH
Vaishnavi Nattar Ranganathan, Tina He, Srihari Rajgopal, Mehran Mehregany, Philip X.-L. Feng, Swarup Bhunia
2013 J jnl
Protection Against Hardware Trojan Attacks: Towards a Comprehensive Solution.
IEEE Des. Test
Swarup Bhunia, Miron Abramovici, Dakshi Agrawal, Paul Bradley, Michael S. Hsiao, Jim Plusquellic, Mohammad Tehranipoor
2013 A* conf
RESP: a robust physical unclonable function retrofitted into embedded SRAM array.
DAC
Yu Zheng, Maryamsadat Hashemian, Swarup Bhunia
2013 — conf
Reconfigurable ECC for adaptive protection of memory.
MWSCAS
Abhishek Basak, Somnath Paul, Jangwon Park, Jongsun Park, Swarup Bhunia
2013 A* conf
Role of power grid in side channel attack and power-grid-aware secure design.
DAC
Xinmu Wang, Wen Yueh, Debapriya Basu Roy, Seetharam Narasimhan, Yu Zheng, Saibal Mukhopadhyay, Debdeep Mukhopadhyay, Swarup Bhunia
2013 — conf
ScanPUF: Robust ultralow-overhead PUF using scan chain.
ASP-DAC
Yu Zheng, Aswin Raghav Krishna, Swarup Bhunia
2013 — conf
Secure and Trusted SoC: Challenges and Emerging Solutions.
MTV
Abhishek Basak, Sanchita Mal-Sarkar, Swarup Bhunia
2013 Misc conf
Ultralow-Power and Robust Embedded Memory for Bioimplantable Microsystems.
VLSI Design
Maryamsadat Hashemian, Swarup Bhunia
2012 Misc conf
Energy-Efficient Application Mapping in FPGA through Computation in Embedded Memory Blocks.
VLSI Design
Anandaroop Ghosh, Somnath Paul, Swarup Bhunia
2012 J jnl
Healing of DSP Circuits Under Power Bound Using Post-Silicon Operand Bitwidth Truncation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Seetharam Narasimhan, Keerthi Kunaparaju, Swarup Bhunia
2012 — conf
Implantable ultrasonic dual functional assembly for detection and treatment of anomalous growth.
EMBC
Abhishek Basak, Vaishnavi Nattar Ranganathan, Seetharam Narasimhan, Swarup Bhunia
2012 J jnl
Improving IC Security Against Trojan Attacks Through Integration of Security Monitors.
IEEE Des. Test Comput.
Seetharam Narasimhan, Wen Yueh, Xinmu Wang, Saibal Mukhopadhyay, Swarup Bhunia
2012 J jnl
Introduction to Special Issue on Implantable Electronics.
ACM J. Emerg. Technol. Comput. Syst.
Swarup Bhunia, Darrin J. Young
2012 — conf
Memory-based computing for performance and energy improvement in multicore architectures.
ACM Great Lakes Symposium on VLSI
Kamran Rahmani, Prabhat Mishra, Swarup Bhunia
2012 Misc conf
SCARE: Side-Channel Analysis Based Reverse Engineering for Post-Silicon Validation.
VLSI Design
Xinmu Wang, Seetharam Narasimhan, Aswin Raghav Krishna, Swarup Bhunia
2012 J jnl
Self-Healing Design in Deep Scaled CMOS Technologies.
J. Circuits Syst. Comput.
Jangjoon Lee, Srikar Bhagavatula, Swarup Bhunia, Kaushik Roy, Byunghoo Jung
2012 — conf
Software exploitable hardware Trojans in embedded processor.
DFT
Xinmu Wang, Tatini Mal-Sarkar, Aswin Raghav Krishna, Seetharam Narasimhan, Swarup Bhunia
2012 Misc conf
Tutorial T4: Intellectual Property Protection and Security in System-on-Chip Design.
VLSI Design
Susmita Sur-Kolay, Swarup Bhunia
2012 — ch.
Ultralow-Power Implantable Electronics.
Handbook of Energy-Aware and Green Computing
Seetharam Narasimhan, Swarup Bhunia
2012 Misc conf
Width-Aware Fine-Grained Dynamic Supply Gating: A Design Methodology for Low-Power Datapath and Memory.
VLSI Design
Lei Wang, Somnath Paul, Swarup Bhunia
2011 J jnl
Dynamic Transfer of Computation to Processor Cache for Yield and Reliability Improvement.
IEEE Trans. Very Large Scale Integr. Syst.
Somnath Paul, Swarup Bhunia
2011 — conf
Embedded Software Security through Key-Based Control Flow Obfuscation.
InfoSecHiComNet
Rajat Subhra Chakraborty, Seetharam Narasimhan, Swarup Bhunia
2011 J jnl
Energy-Efficient Reconfigurable Computing Using a Circuit-Architecture-Software Co-Design Approach.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Somnath Paul, Subho Chatterjee, Saibal Mukhopadhyay, Swarup Bhunia
2011 A conf
High-temperature (>500°C) reconfigurable computing using silicon carbide NEMS switches.
DATE
Xinmu Wang, Seetharam Narasimhan, Aswin Raghav Krishna, Francis G. Wolff, Srihari Rajgopal, Te-Hao Lee, Mehran Mehregany, Swarup Bhunia
2011 — book
Low-Power Variation-Tolerant Design in Nanometer Silicon
Swarup Bhunia, Saibal Mukhopadhyay
2011 — conf
Low-power implantable ultrasound imager for online monitoring of tumor growth.
EMBC
Abhishek Basak, Seetharam Narasimhan, Swarup Bhunia
2011 A conf
MECCA: A Robust Low-Overhead PUF Using Embedded Memory Array.
CHES
Aswin Raghav Krishna, Seetharam Narasimhan, Xinmu Wang, Swarup Bhunia
2011 A conf
Memory based computing: reshaping the fine-grained logic in a reconfigurable framework (abstract only).
FPGA
Somnath Paul, Swarup Bhunia
2011 A conf
Multi-level attacks: An emerging security concern for cryptographic hardware.
DATE
Subidh Ali, Rajat Subhra Chakraborty, Debdeep Mukhopadhyay, Swarup Bhunia
2011 — conf
NEMTronics: Symbiotic integration of nanoelectronic and nanomechanical devices for energy-efficient adaptive computing.
NANOARCH
Xinmu Wang, Seetharam Narasimhan, Somnath Paul, Swarup Bhunia
2011 J jnl
Reliability-Driven ECC Allocation for Multiple Bit Error Resilience in Processor Cache.
IEEE Trans. Computers
Somnath Paul, Fang Cai, Xinmiao Zhang, Swarup Bhunia
2011 J jnl
Security Against Hardware Trojan Attacks Using Key-Based Design Obfuscation.
J. Electron. Test.
Rajat Subhra Chakraborty, Swarup Bhunia
2011 C conf
Sequential hardware Trojan: Side-channel aware design and placement.
ICCD
Xinmu Wang, Seetharam Narasimhan, Aswin Raghav Krishna, Tatini Mal-Sarkar, Swarup Bhunia
2011 — conf
TeSR: A robust Temporal Self-Referencing approach for Hardware Trojan detection.
HOST
Seetharam Narasimhan, Xinmu Wang, Dongdong Du, Rajat Subhra Chakraborty, Swarup Bhunia
2011 J jnl
Ultra-Low-Power and Robust Digital-Signal-Processing Hardware for Implantable Neural Interface Microsystems.
IEEE Trans. Biomed. Circuits Syst.
Seetharam Narasimhan, Hillel J. Chiel, Swarup Bhunia
2011 Misc conf
VaROT: Methodology for Variation-Tolerant DSP Hardware Design Using Post-Silicon Truncation of Operand Width.
VLSI Design
Keerthi Kunaparaju, Seetharam Narasimhan, Swarup Bhunia
2010 — conf
A supply-demand model based scalable energy management system for improved energy utilization efficiency.
Green Computing Conference
Seetharam Narasimhan, David R. McIntyre, Francis G. Wolff, Yu Zhou, Daniel J. Weyer, Swarup Bhunia
2010 J jnl
Collaborative Trust: A Novel Paradigm of Trusted Mobile Computing
CoRR
Tatini Mal-Sarkar, Swarup Bhunia
2010 J jnl
Guest Editors' Introduction: Managing Uncertainty through Postfabrication Calibration and Repair.
IEEE Des. Test Comput.
Swarup Bhunia, Rahul Rao
2010 J jnl
Low-overhead
ACM Trans. Design Autom. Electr. Syst.
Somnath Paul, Hamid Mahmoodi, Swarup Bhunia
2010 — conf
Multiple-Parameter Side-Channel Analysis: A Non-invasive Hardware Trojan Detection Approach.
HOST
Seetharam Narasimhan, Rajat Subhra Chakraborty, Dongdong Du, Somnath Paul, Francis G. Wolff, Christos A. Papachristou, Kaushik Roy, Swarup Bhunia
2010 Misc conf
RTL Hardware IP Protection Using Key-Based Control and Data Flow Obfuscation.
VLSI Design
Rajat Subhra Chakraborty, Swarup Bhunia
2010 A conf
Self-referencing: A Scalable Side-Channel Approach for Hardware Trojan Detection.
CHES
Dongdong Du, Seetharam Narasimhan, Rajat Subhra Chakraborty, Swarup Bhunia
2010 Misc conf
Special session 11B: Hot topic hardware security: Design, test and verification issues.
VTS
Swarup Bhunia, Anand Raghunathan
2010 — conf
System level self-healing for parametric yield and reliability improvement under power bound.
AHS
Seetharam Narasimhan, Somnath Paul, Rajat Subhra Chakraborty, Francis G. Wolff, Christos A. Papachristou, Daniel J. Weyer, Swarup Bhunia
2010 J jnl
Trifecta: A Nonspeculative Scheme to Exploit Common, Data-Dependent Subcritical Paths.
IEEE Trans. Very Large Scale Integr. Syst.
Patrick Ndai, Nauman Rafique, Mithuna Thottethodi, Swaroop Ghosh, Swarup Bhunia, Kaushik Roy
2010 C conf
Trustworthy computing in a multi-core system using distributed scheduling.
IOLTS
David R. McIntyre, Francis G. Wolff, Christos A. Papachristou, Swarup Bhunia
2010 A conf
VAIL: variation-aware issue logic and performance binning for processor yield and profit improvement.
ISLPED
Somnath Paul, Swarup Bhunia
2009 A conf
A circuit-software co-design approach for improving EDP in reconfigurable frameworks.
ICCAD
Somnath Paul, Subho Chatterjee, Saibal Mukhopadhyay, Swarup Bhunia
2009 J jnl
A study of asynchronous design methodology for robust CMOS-nano hybrid system design.
ACM J. Emerg. Technol. Comput. Syst.
Rajat Subhra Chakraborty, Swarup Bhunia
2009 A conf
A variation-aware preferential design approach for memory based reconfigurable computing.
ICCAD
Somnath Paul, Saibal Mukhopadhyay, Swarup Bhunia
2009 — conf
Computing with nanoscale memory: Model and architecture.
NANOARCH
Somnath Paul, Swarup Bhunia
2009 — conf
Dynamic Evaluation of Hardware Trust.
HOST
David R. McIntyre, Francis G. Wolff, Christos A. Papachristou, Swarup Bhunia
2009 J jnl
HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rajat Subhra Chakraborty, Swarup Bhunia
2009 — conf
Hardware Trojan: Threats and emerging solutions.
HLDVT
Rajat Subhra Chakraborty, Seetharam Narasimhan, Swarup Bhunia
2009 J jnl
Low-power hybrid complementary metaloxide- semiconductor-nano-electro-mechanical systems field programmable gate array: circuit level analysis and defect-aware mapping.
IET Comput. Digit. Tech.
Rajat Subhra Chakraborty, Somnath Paul, Yu Zhou, Swarup Bhunia
2009 A conf
MERO: A Statistical Approach for Hardware Trojan Detection.
CHES
Rajat Subhra Chakraborty, Francis G. Wolff, Somnath Paul, Christos A. Papachristou, Swarup Bhunia
2009 — conf
Security Through Obscurity: An Approach for Protecting Register Transfer Level Hardware IP.
HOST
Rajat Subhra Chakraborty, Swarup Bhunia
2009 A conf
Security against hardware Trojan through a novel application of design obfuscation.
ICCAD
Rajat Subhra Chakraborty, Swarup Bhunia
2008 Misc conf
Analysis and Robust Design of Diode-Resistor Based Nanoscale Crossbar PLA Circuits.
VLSI Design
Rajat Subhra Chakraborty, Somnath Paul, Swarup Bhunia
2008 J jnl
Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique.
J. Electron. Test.
Swarup Bhunia, Hamid Mahmoodi, Arijit Raychowdhury, Kaushik Roy
2008 A* conf
Collective computing based on swarm intelligence.
DAC
Seetharam Narasimhan, Somnath Paul, Swarup Bhunia
2008 A conf
Fine-Grained Supply Gating Through Hypergraph Partitioning and Shannon Decomposition for Active Power Reduction.
DATE
Lawrence Leinweber, Swarup Bhunia
2008 A conf
Hardware protection and authentication through netlist level obfuscation.
ICCAD
Rajat Subhra Chakraborty, Swarup Bhunia
2008 A conf
Harvesting Wasted Heat in a Microprocessor Using Thermoelectric Generators: Modeling, Analysis and Measurement.
DATE
Yu Zhou, Somnath Paul, Swarup Bhunia
2008 A conf
Hybrid CMOS-STTRAM non-volatile FPGA: design challenges and optimization approaches.
ICCAD
Somnath Paul, Saibal Mukhopadhyay, Swarup Bhunia
2008 A conf
Low power design under parameter variations.
ISLPED
Swarup Bhunia, Kaushik Roy
2008 — conf
Low power design under parameter variations.
SoCC
Swarup Bhunia, Kaushik Roy
2008 — conf
MBARC: A scalable memory based reconfigurable computing framework for nanoscale devices.
ASP-DAC
Somnath Paul, Swarup Bhunia
2008 — conf
Micropipeline-Based Asynchronous Design Methodology for Robust System Design Using Nanoscale Crossbar.
ISQED
Rajat Subhra Chakraborty, Swarup Bhunia
2008 — conf
On-Demand Transparency for Improving Hardware Trojan Detectability.
HOST
Rajat Subhra Chakraborty, Somnath Paul, Swarup Bhunia
2008 — conf
On-die CMOS voltage droop detection and dynamiccompensation.
ACM Great Lakes Symposium on VLSI
Matthew Seetharam A. Holtz, Seetharam Narasimhan, Swarup Bhunia
2008 J jnl
Profit Aware Circuit Design Under Process Variations Considering Speed Binning.
IEEE Trans. Very Large Scale Integr. Syst.
Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy
2008 A* conf
Reconfigurable computing using content addressable memory for improved performance and resource usage.
DAC
Somnath Paul, Swarup Bhunia
2008 A conf
Towards Trojan-Free Trusted ICs: Problem Analysis and Detection Scheme.
DATE
Francis G. Wolff, Christos A. Papachristou, Swarup Bhunia, Rajat Subhra Chakraborty
2008 — conf
Towards Uniform Temperature Distribution in SOI Circuits Using Carbon Nanotube Based Thermal Interconnect.
ISQED
Yu Zhou, Somnath Paul, Swarup Bhunia
2008 J jnl
Within-Die Variation-Aware Scheduling in Superscalar Processors for Improved Throughput.
IEEE Trans. Computers
Patrick Ndai, Swarup Bhunia, Amit Agarwal, Kaushik Roy
2007 — conf
Adaptation to Temperature-Induced Delay Variations in Logic Circuits Using Low-Overhead Online Delay Calibration.
ISQED
Sivasubramaniam Krishnamurthy, Somnath Paul, Swarup Bhunia
2007 J jnl
CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Swaroop Ghosh, Swarup Bhunia, Kaushik Roy
2007 C conf
Defect-Aware Configurable Computing in Nanoscale Crossbar for Improved Yield.
IOLTS
Somnath Paul, Rajat Subhra Chakraborty, Swarup Bhunia
2007 J jnl
Device-Aware Yield-Centric Dual-V
IEEE Trans. Very Large Scale Integr. Syst.
Amit Agarwal, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy
2007 J jnl
Hybridization of CMOS With CNT-Based Nano-Electromechanical Switch for Low Leakage and Robust Circuit Design.
IEEE Trans. Circuits Syst. I Regul. Pap.
Rajat Subhra Chakraborty, Seetharam Narasimhan, Swarup Bhunia
2007 A conf
Low power FPGA design using hybrid CMOS-NEMS approach.
ISLPED
Yu Zhou, Shijo Thekkel, Swarup Bhunia
2007 J jnl
Low-Power and testable circuit synthesis using Shannon decomposition.
ACM Trans. Design Autom. Electr. Syst.
Swaroop Ghosh, Swarup Bhunia, Kaushik Roy
2007 A conf
Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling.
DATE
Swaroop Ghosh, Swarup Bhunia, Kaushik Roy
2007 A conf
Low-overhead design technique for calibration of maximum frequency at multiple operating points.
ICCAD
Somnath Paul, Sivasubramaniam Krishnamurthy, Hamid Mahmoodi, Swarup Bhunia
2007 C conf
Memory based computation using embedded cache for processor yield and reliability improvement.
ICCD
Somnath Paul, Swarup Bhunia
2007 J jnl
Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits
CoRR
Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy
2007 A conf
Power dissipation, variations and nanoscale CMOS design: Test challenges and self-calibration/self-repair solutions.
ITC
Swarup Bhunia, Kaushik Roy
2007 Misc conf
Process Variations and Process-Tolerant Design.
VLSI Design
Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy
2007 J jnl
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies
CoRR
Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Nilanjan Banerjee, Kaushik Roy
2007 C conf
Tolerance to Small Delay Defects by Adaptive Clock Stretching.
IOLTS
Swaroop Ghosh, Patrick Ndai, Swarup Bhunia, Kaushik Roy
2007 — conf
Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches.
ASP-DAC
Swarup Bhunia, Massood Tabib-Azar, Daniel G. Saab
2007 Misc conf
VIm-Scan: A Low Overhead Scan Design Approach for Protection of Secret Key in Scan-Based Secure Chips.
VTS
Somnath Paul, Rajat Subhra Chakraborty, Swarup Bhunia
2006 J jnl
A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy
2006 A conf
A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation.
ICCAD
Swaroop Ghosh, Swarup Bhunia, Kaushik Roy
2006 C conf
Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor.
IOLTS
Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy
2006 J jnl
Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy
2006 A conf
Low power synthesis of dynamic logic circuits using fine-grained clock gating.
DATE
Nilanjan Banerjee, Kaushik Roy, Hamid Mahmoodi-Meimand, Swarup Bhunia
2006 — conf
Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability.
ASP-DAC
Ashish Goel, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy
2006 J jnl
Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS logic circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy
2006 J jnl
Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis.
IEEE Trans. Very Large Scale Integr. Syst.
Nilanjan Banerjee, Arijit Raychowdhury, Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi
2006 — conf
Speed binning aware design methodology to improve profit under parameter variations.
ASP-DAC
Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy
2006 A conf
Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies.
DATE
Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy
2005 A conf
A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application.
DATE
Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy
2005 — conf
A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks.
ISQED
Animesh Datta, Swarup Bhunia, Nilanjan Banerjee, Kaushik Roy
2005 — conf
A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter Variations.
Asian Test Symposium
Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy
2005 B conf
A novel delay fault testing methodology using on-chip low-overhead delay measurement hardware at strategic probe points.
ETS
Arijit Raychowdhury, Swaroop Ghosh, Swarup Bhunia, Debjyoti Ghosh, Kaushik Roy
2005 A* conf
A novel synthesis approach for active leakage power reduction using dynamic supply gating.
DAC
Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hamid Mahmoodi-Meimand, Kaushik Roy
2005 J jnl
A novel wavelet transform-based transient current analysis for fault detection and localization.
IEEE Trans. Very Large Scale Integr. Syst.
Swarup Bhunia, Kaushik Roy
2005 J jnl
Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation.
IEEE Trans. Very Large Scale Integr. Syst.
Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy
2005 J jnl
Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Supply Current.
J. Electron. Test.
Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy
2005 A conf
Effectiveness of low power dual-V
ISLPED
Amit Agarwal, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy
2005 J jnl
Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations.
IEEE Trans. Very Large Scale Integr. Syst.
Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy
2005 J jnl
Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current.
J. Electron. Test.
Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy
2005 J jnl
GAARP: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks.
IEEE Trans. Computers
Swarup Bhunia, Animesh Datta, Nilanjan Banerjee, Kaushik Roy
2005 J jnl
Low-power scan design using first-level supply gating.
IEEE Trans. Very Large Scale Integr. Syst.
Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Saibal Mukhopadhyay, Kaushik Roy
2005 A conf
Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits.
DATE
Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy
2005 Misc conf
Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS.
VTS
Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy
2005 C conf
Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis.
ICCD
Nilanjan Banerjee, Arijit Raychowdhury, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy
2005 — conf
Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning.
ISQED
Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Kaushik Roy
2005 — conf
Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability.
Asian Test Symposium
Swaroop Ghosh, Swarup Bhunia, Kaushik Roy
2005 A conf
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies.
DATE
Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Nilanjan Banerjee, Kaushik Roy
2005 J jnl
Synthesis of application-specific highly efficient multi-mode cores for embedded systems.
ACM Trans. Embed. Comput. Syst.
Lih-Yih Chiou, Swarup Bhunia, Kaushik Roy
2005 C conf
Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub-100nm Technology.
IOLTS
Animesh Datta, Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy
2004 C conf
A Novel Low-Power Scan Design Technique Using Supply Gating.
ICCD
Swarup Bhunia, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Debjyoti Ghosh, Kaushik Roy
2004 C conf
A Technique to Reduce Power and Test Application Time in BIST.
IOLTS
Debjyoti Ghosh, Swarup Bhunia, Kaushik Roy
2004 J jnl
DCG: deterministic clock-gating for low-power microprocessor design.
IEEE Trans. Very Large Scale Integr. Syst.
Hai Li, Swarup Bhunia, Yiran Chen, Kaushik Roy, T. N. Vijaykumar
2004 — conf
First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique.
DFT
Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy
2004 — conf
Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current.
ISQED
Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy
2004 A conf
Trim Bit Setting of Analog Filters Using Wavelet-Based Supply Current Analysis.
DATE
Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy
2003 A* conf
Deterministic Clock Gating for Microprocessor Power Reduction.
HPCA
Hai Li, Swarup Bhunia, Yiran Chen, T. N. Vijaykumar, Kaushik Roy
2003 — conf
Multiple Scan Chain Design Technique for Power Reduction during Test Application in BIST.
DFT
Debjyoti Ghosh, Swarup Bhunia, Kaushik Roy
2003 A conf
Synthesis of Application-Specific Highly-Efficient Multi-Mode Systems for Low-Power Applications.
DATE
Lih-Yih Chiou, Swarup Bhunia, Kaushik Roy
2002 — conf
A High Performance IDDQ Testable Cache for Scaled CMOS Technologies.
Asian Test Symposium
Swarup Bhunia, Hai Li, Kaushik Roy
2002 A* conf
A novel wavelet transform based transient current analysis for fault detection and localization.
DAC
Swarup Bhunia, Kaushik Roy, Jaume Segura
2002 — conf
Content based image retrieval: related issues using Euler vector.
ICIP (2)
Arijit Bishnu, Swarup Bhunia, C. A. Murthy, Bhargab B. Bhattacharya, Malay Kumar Kundu, Tinku Acharya
2002 Misc conf
Dynamic Supply Current Testing of Analog Circuits Using Wavelet Transform.
VTS
Swarup Bhunia, Kaushik Roy
2002 A conf
Fault Detection and Diagnosis Using Wavelet Based Transient Current Analysis.
DATE
Swarup Bhunia, Kaushik Roy
2000 Misc conf
Topological Routing Amidst Polygonal Obstacles.
VLSI Design
Swarup Bhunia, Subhashis Majumder, Ayan Sircar, Susmita Sur-Kolay, Bhargab B. Bhattacharya
1999 Misc conf
Design, Simulation and Synthesis of an ASIC for Fractal Image Compression.
VLSI Design
Swarup Bhunia, Soumya K. Ghosh, Pramod Kumar, Partha Pratim Das, Jayanta Mukherjee