Swapna Banerjee

81 papers B 14C 2Misc 12Journal 36Unranked 17
YearRankTypeTitle / Venue / Authors
2021 J jnl
FPGA-accelerated adaptive projection-based image registration.
J. Real Time Image Process.
Pulak Mondal, Swapna Banerjee
2020 J jnl
A Low-Error, Memory-Based Fast Binary Logarithmic Converter.
IEEE Trans. Circuits Syst. II Express Briefs
Biswabandhu Jana, Avishek Sinha Roy, Goutam Saha, Swapna Banerjee
2020 J jnl
A high throughput pass parallel block decoder architecture for JPEG 2000 that prevents stalling in the decoding process.
Integr.
Pallab Kumar Nath, Swapna Banerjee
2020 J jnl
Compiler compatible 5.66 Mb/mm
Integr.
Arindrajit Ghosh, Uddalak Bhattacharya, Manish Kumar, Swapna Banerjee
2020 J jnl
Smartphone-Based Point-of-Care System Using Continuous-Wave Portable Doppler.
IEEE Trans. Instrum. Meas.
Biswabandhu Jana, Rakesh Biswas, Pallab Kumar Nath, Goutam Saha, Swapna Banerjee
2019 J jnl
A Reconfigurable Memory-Based Fast VLSI Architecture for Computation of the Histogram.
IEEE Trans. Consumer Electron.
Pulak Mondal, Swapna Banerjee
2019 J jnl
An IEEE Single Precision Floating Point Arithmetic-Based Apodization Architecture for Portable Ultrasound Imaging System.
IEEE Trans. Circuits Syst. I Regul. Pap.
Mayur Agarwal, Arijit De, Swapna Banerjee
2019 J jnl
Detection of peripheral arterial disease using Doppler spectrogram based expert system for Point-of-Care applications.
Biomed. Signal Process. Control.
Biswabandhu Jana, Kamal Oswal, Sankar Mitra, Goutam Saha, Swapna Banerjee
2018 J jnl
A Computationally Efficient Reconfigurable Constant Multiplication Architecture Based on CSD Decoded Vertical-Horizontal Common Sub-Expression Elimination Algorithm.
IEEE Trans. Circuits Syst. I Regul. Pap.
Indranil Hatai, Indrajit Chakrabarti, Swapna Banerjee
2018 J jnl
A High-Precision Low-Area Unified Architecture for Lossy and Lossless 3D Multi-Level Discrete Wavelet Transform.
IEEE Trans. Circuits Syst. Video Technol.
Rakesh Biswas, Siddarth Reddy Malreddy, Swapna Banerjee
2018 J jnl
Accuracy Enhancement for Noninvasive Glucose Estimation Using Dual-Wavelength Photoacoustic Measurements and Kernel-Based Calibration.
IEEE Trans. Instrum. Meas.
Praful P. Pai, Arijit De, Swapna Banerjee
2018 J jnl
Cloud Computing-Based Non-Invasive Glucose Monitoring for Diabetic Care.
IEEE Trans. Circuits Syst. I Regul. Pap.
Praful P. Pai, Pradyut Kumar Sanki, Sudeep K. Sahoo, Arijit De, Sourangshu Bhattacharya, Swapna Banerjee
2018 J jnl
Contention free delayed keeper for high density large signal sensing memory compiler.
Integr.
Arindrajit Ghosh, Uddalak Bhattacharya, Swapna Banerjee
2016 J jnl
A Low Complexity VLSI Architecture for Multi-Focus Image Fusion in DCT Domain.
CoRR
Ashutosh Mishra, Sudipta Mahapatra, Swapna Banerjee
2016 J jnl
A high speed, memory efficient line based VLSI architecture for the dual mode inverse discrete wavelet transform of JPEG2000 decoder.
Microprocess. Microsystems
Pallab Kumar Nath, Swapna Banerjee
2016 — conf
A new paradigm of oral cancer detection using digital infrared thermal imaging.
Computer-Aided Diagnosis
Mrityunjoy Chakraborty, Sudipta Mukhopadhyay, A. Dasgupta, Swapna Banerjee, Santanu Patsa, Jay G. Ray, K. Chaudhuri
2016 J jnl
Architecture of a real-time delay calculator for digital beamforming in ultrasound system.
IET Circuits Devices Syst.
Mayur Agarwal, Arijit De, Swapna Banerjee
2016 J jnl
FPGA based accelerated 3D affine transform for real-time image processing applications.
Comput. Electr. Eng.
Pulak Mondal, Pradyut Kumar Biswal, Swapna Banerjee
2016 B conf
Implementation of Smartphone Based Blood Flow Diagnoses from Doppler Spectrogram.
CBMS
Biswabandhu Jana, Swapna Banerjee
2015 — conf
A 10-Bit 500 MSPS Segmented DAC with Optimized Current Sources to Avoid Mismatch Effect.
ISVLSI
Santanu Sarkar, Swapna Banerjee
2015 — conf
A photoacoustics based continuous non-invasive blood glucose monitoring system.
MeMeA
Praful P. Pai, Pradyut Kumar Sanki, Swapna Banerjee
2015 J jnl
An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis.
IEEE Trans. Circuits Syst. I Regul. Pap.
Indranil Hatai, Indrajit Chakrabarti, Swapna Banerjee
2015 J jnl
An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation.
IEEE Trans. Very Large Scale Integr. Syst.
Indranil Hatai, Indrajit Chakrabarti, Swapna Banerjee
2015 J jnl
An FPGA-based architecture of DSC-SRI units specially for motion blind ultrasound systems.
J. Real Time Image Process.
Rakesh Biswas, Kishor Sarawadekar, Srinivas Varna, Swapna Banerjee
2015 J jnl
Efficient Hardware Implementation of Encoder and Decoder for Golay Code.
IEEE Trans. Very Large Scale Integr. Syst.
Satyabrata Sarangi, Swapna Banerjee
2015 — conf
NIR photoacoustic spectroscopy for non-invasive glucose measurement.
EMBC
Praful P. Pai, Pradyut Kumar Sanki, Arijit De, Swapna Banerjee
2015 J jnl
VLSI-Assisted Nonrigid Registration Using Modified Demons Algorithm.
IEEE Trans. Very Large Scale Integr. Syst.
Ashutosh Mishra, Pulak Mondal, Swapna Banerjee
2014 B conf
2D/3D Non-rigid Image Registration by an Efficient Demons Approach.
CBMS
Ashutosh Mishra, Pulak Mondal, Swapna Banerjee
2014 J jnl
An 8-bit low power DAC with re-used distributed binary cells architecture for reconfigurable transmitters.
Microelectron. J.
Santanu Sarkar, Swapna Banerjee
2014 B conf
Comparative Analysis of Golay Code Based Excitation and Coherent Averaging for Non-invasive Glucose Monitoring System.
CBMS
Satyabrata Sarangi, Praful P. Pai, Pradyut Kumar Sanki, Swapna Banerjee
2013 J jnl
Foreground calibration technique of a pipeline ADC using capacitor ratio of Multiplying Digital-to-Analog Converter (MDAC).
Microelectron. J.
Sounak Roy, Hiranmoy Basak, Swapna Banerjee
2013 J jnl
Parallel architecture for accelerating affine transform in high-speed imaging systems.
J. Real Time Image Process.
Pradyut Kumar Biswal, Pulak Mondal, Swapna Banerjee
2013 — conf
Reconfigurable Architecture of a RRC Fir Interpolator for Multi-standard Digital Up Converter.
IPDPS Workshops
Indranil Hatai, Indrajit Chakrabarti, Swapna Banerjee
2012 — conf
Modified Demons deformation algorithm for non-rigid image registration.
IHCI
Ashutosh Mishra, Pulak Mondal, Swapna Banerjee
2012 B conf
Motion estimation in medical video sequences using affine transform.
CBMS
Pulak Mondal, Swapna Banerjee
2012 C conf
Radix based digital calibration technique for pipelined ADC using Nyquist sampling of sinusoid.
ISCAS
Sounak Roy, Bibhudatta Sahoo, Swapna Banerjee
2012 J jnl
VLSI design of memory-efficient, high-speed baseline MQ coder for JPEG 2000.
Integr.
Kishor Sarawadekar, Swapna Banerjee
2012 J jnl
VLSI-DSP based real time solution of DSC-SRI for an ultrasound system.
Microprocess. Microsystems
Kishor Sarawadekar, Harihar Bharat Indana, Deep Bera, Swapna Banerjee
2011 J jnl
An Efficient Pass-Parallel Architecture for Embedded Block Coder in JPEG 2000.
IEEE Trans. Circuits Syst. Video Technol.
Kishor Sarawadekar, Swapna Banerjee
2010 — conf
A tunable transconductor with high linearity.
APCCAS
Vijaya Bhadauria, Krishna Kant, Swapna Banerjee
2010 J jnl
An Efficient Architecture for 3-D Discrete Wavelet Transform.
IEEE Trans. Circuits Syst. Video Technol.
Anirban Das, Anindya Hazra, Swapna Banerjee
2010 J jnl
Architectural design and FPGA implementation of radix-4 CORDIC processor.
Microprocess. Microsystems
Kaushik Bhattacharyya, Rakesh Biswas, Anindya Sundar Dhar, Swapna Banerjee
2009 — conf
A high speed bit plane coder for JPEG 2000 and it's FPGA implementation.
EUSIPCO
Kishor Sarawadekar, Swapna Banerjee
2009 — conf
An 8-bit 1.8 V 500 MSPS CMOS Segmented Current Steering DAC.
ISVLSI
Santanu Sarkar, Swapna Banerjee
2009 B conf
Efficient VLSI architecture for bit plane encoder of JPEG 2000.
ICIP
Kishor Sarawadekar, Swapna Banerjee
2009 B conf
Multirate scan conversion of ultrasound images using warped distance based adaptive bilinear interpolation.
CBMS
Deep Bera, Leeladhar Agarwal, Swapna Banerjee
2008 Misc conf
A 9 bit 400 MHz CMOS Double-Sampled Sample-and-Hold Amplifier.
VLSI Design
Sounak Roy, Swapna Banerjee
2008 C conf
An 8-bit 1.8 V 500 MS/s CMOS DAC with a novel four-stage current steering architecture.
ISCAS
Santanu Sarkar, Ravi Sankar Prasad, Sanjoy Kumar Dey, Vinay Belde, Swapna Banerjee
2006 — conf
A Fully Differential 11mW 10-bit 200MS/s Sample and Hold in 0.25µm BiCMOS Technology.
APCCAS
Santanu Sarkar, Arindrajit Ghosh, Swapna Banerjee
2006 B conf
A Real Time Speckle Noise Cleaning Filter for Ultrasound Images.
CBMS
Bodhisatwa Mazumdar, Aman Mediratta, Joydeep Bhattacharyya, Swapna Banerjee
2006 Misc conf
An 8-Bit, 3.8GHz Dynamic BiCMOS Comparator for High-Performance ADC.
VLSI Design
Sanjoy Kumar Dey, Swapna Banerjee
2006 Misc conf
Design of Low-Voltage Low-Power Continuous-Time Filter for Hearing Aid Application Using CMOS Current Conveyor Based Translinear Loop.
VLSI Design
Debashis Dutta, Ritesh Ujjwal, Swapna Banerjee
2006 B conf
Quantitative Analysis of Histopathological Features of Precancerous Lesion and Condition Using Image Processing Technique.
CBMS
Abhijeet Jadhav, Swapna Banerjee, P. K. Dutta, Ranjan Rashmi Paul, Mousumi Pal, P. Banerjee, K. Chaudhuri, Jyotirmoy Chatterjee
2006 Misc conf
Real Time Dynamic Receive Apodization for an Ultrasound Imaging System.
VLSI Design
J. Bhattacharyya, P. Mandal, R. Banerjee, Swapna Banerjee
2005 Misc conf
A 10-Bit 80-MSPS 2.5-V 27.65-mW 0.185-mm
VLSI Design
Samiran Halder, Swapna Banerjee, Arindrajit Ghosh, Ravi Sankar Prasad, Anirban Chatterjee, Sanjoy Kumar Dey
2005 Misc conf
A 160MSPS 8-Bit Pipeline Based ADC.
VLSI Design
Samiran Halder, Arindrajit Ghosh, Ravi Sankar Prasad, Anirban Chatterjee, Swapna Banerjee
2005 Misc conf
A New CMOS Current Conveyors Based Translinear Loop for Log-Domain Circuit Design.
VLSI Design
Debashis Dutta, Wouter A. Serdijn, Swapna Banerjee, Sriram Gupta
2005 — conf
Design of static and dynamic translinear circuits based on CMOS CCII translinear loops.
ICECS
Debashis Dutta, Ritesh Ujjwal, Swapna Banerjee, Wouter A. Serdijn
2005 J jnl
Modified virtually scaling-free adaptive CORDIC rotator algorithm and architecture.
IEEE Trans. Circuits Syst. Video Technol.
Koushik Maharatna, Swapna Banerjee, Eckhard Grass, Milos Krstic, Alfonso Troya
2004 B conf
A 16-bit CORDIC rotator for high-speed wireless LAN.
PIMRC
Koushik Maharatna, Alfonso Troya, Swapna Banerjee, Eckhard Grass, Milos Krstic
2004 B conf
A New Interpolation Free Method for X-ray CT Image Reconstruction.
CBMS
Abhishek Mitra, Swapna Banerjee
2004 — conf
A regular algorithm for real time Radon & inverse Radon transform [image processing applications].
ICASSP (5)
Abhishek Mitra, Swapna Banerjee
2004 B conf
Homogeneity Induced Inertial Snake with Application to Medical Image Segmentation.
CBMS
Bipul Das, Swapna Banerjee
2004 B conf
Real Time Noise Cleaning of Ultrasound Images.
CBMS
Anindya Hazra, J. Bhattacharyya, Swapna Banerjee
2003 Misc conf
A Memory Efficient 3-D DWT Architecture.
VLSI Design
Bipul Das, Swapna Banerjee
2003 Misc conf
A New Approach to Analyze a Sub-micron CMOS Inverter.
VLSI Design
Manisha Pattanaik, Swapna Banerjee
2003 B conf
A Novel Ram Architecture For Bit-Plane Based Coding.
DCC
Bipul Das, Swapna Banerjee
2003 — conf
A low complexity architecture for complex discrete wavelet transform.
ICASSP (2)
Bipul Das, Swapna Banerjee
2002 B conf
A Wavelet Based Low Complexity Embedded Block Coding Algorithm.
DCC
Bipul Das, Swapna Banerjee
2002 — conf
Design of continuous-time filter for hearing aid application using current conveyors.
ICECS
Debashis Dutta, Qadeer Ahmad Khan, Swapna Banerjee
2002 Misc conf
VLSI architecture for a new real-time 3D wavelet transform.
ICASSP
B. Das, Swapna Banerjee
2001 — conf
A CORDIC based array architecture for complex discrete wavelet transform.
ACM Great Lakes Symposium on VLSI
Bipul Das, Swapna Banerjee
2001 J jnl
A VLSI array architecture for Hough transform.
Pattern Recognit.
Koushik Maharatna, Swapna Banerjee
2001 J jnl
A VLSI array architecture for realization of DFT, DHT, DCT and DST.
Signal Process.
Koushik Maharatna, A. S. Dhar, Swapna Banerjee
2001 J jnl
FPGA realization of a CORDIC based FFT processor for biomedical signal processing.
Microprocess. Microsystems
Ayan Banerjee, Anindya Sundar Dhar, Swapna Banerjee
2000 — conf
Knowledge Base System for Diagnostic Assessment of Doppler Spectogram.
MICAI
Bipul Das, S. K. Mitra, Swapna Banerjee
1998 — conf
Knowledge-based Doppler blood-velocimeter system.
KES (3)
Bipul Das, Swapna Banerjee
1995 Misc conf
Analysis of temperature dependence of Si-Ge HBT.
VLSI Design
G. Hari Rama Krishna, Amit K. Aditya, Nirmal B. Chakrabarti, Swapna Banerjee
1995 J jnl
Finite element analysis of SiGe heterojunction devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
G. Hari Rama Krishna, Amit K. Aditya, Nirmal B. Chakrabarti, Swapna Banerjee
1994 Misc conf
Finite Element Analysis of SIGe npn HBT.
VLSI Design
G. Hari Rama Krishna, Nirmal B. Chakrabarti, Swapna Banerjee
1971 J jnl
On the Probability Distribution of Round-off Errors Propagated in Tabular Differences.
Aust. Comput. J.
S. K. Mitra, Swapna Banerjee