Sven-Ole Voigt

12 papers B 3C 1Misc 1Journal 4Unranked 2
YearRankTypeTitle / Venue / Authors
2014 J jnl
Scalability evaluation of an FPGA-based multi-core architecture with hardware-enforced domain partitioning.
Microprocess. Microsystems
Daniel Kliem, Sven-Ole Voigt
2013 B conf
An asynchronous bus bridge for partitioned multi-soc architectures on FPGAs.
FPL
Daniel Kliem, Sven-Ole Voigt
2013 J jnl
Analysis of Fast Radix-10 Digit Recurrence Algorithms for Fixed-Point and Floating-Point Dividers on FPGAs.
Int. J. Reconfigurable Comput.
Malte Baesler, Sven-Ole Voigt
2012 — conf
A multi-core FPGA-based SoC architecture with domain segregation.
ReConFig
Daniel Kliem, Sven-Ole Voigt
2011 — conf
FPGA Implementations of Radix-10 Digit Recurrence Fixed-Point and Floating-Point Dividers.
ReConFig
Malte Baesler, Sven-Ole Voigt, Thomas Teufel
2010 J jnl
A Decimal Floating-Point Accurate Scalar Product Unit with a Parallel Fixed-Point Multiplier on a Virtex-5 FPGA.
Int. J. Reconfigurable Comput.
Malte Baesler, Sven-Ole Voigt, Thomas Teufel
2010 C conf
A radix-10 digit recurrence division unit with a constant digit selection function.
ICCD
Malte Baesler, Sven-Ole Voigt, Thomas Teufel
2010 B conf
An IEEE 754-2008 Decimal Parallel and Pipelined FPGA Floating-Point Multiplier.
FPL
Malte Baesler, Sven-Ole Voigt, Thomas Teufel
2010 J jnl
Dynamically reconfigurable dataflow architecture for high-performance digital signal processing.
J. Syst. Archit.
Sven-Ole Voigt, Malte Baesler, Thomas Teufel
2008 Misc conf
Analysis of a Dynamically Reconfigurable Dataflow Architecture and its Scalable Parallel Extension for Multi-FPGA Platforms.
FCCM
Sven-Ole Voigt, Thomas Teufel
2008 — —
Dynamically reconfigurable dataflow architecture for high performance digital signal processing on multi FPGA platforms.
Sven-Ole Voigt
2007 B conf
Dynamically reconfigurable dataflow architecture for high-performance digital signal processing on multi-FPGA platforms.
FPL
Sven-Ole Voigt, Thomas Teufel