Susmita Sur-Kolay

136 papers A* 1A 3B 1C 7Misc 22Journal 64Unranked 37
YearRankTypeTitle / Venue / Authors
2025 J jnl
AFarePart: Accuracy-aware Fault-resilient Partitioner for DNN Edge Accelerators.
CoRR
Mukta Debnath, Krishnendu Guha, Debasri Saha, Amlan Chakrabarti, Susmita Sur-Kolay
2025 Misc conf
Constructing Rectilinear Steiner Minimum Tree with Conditional Generative Adversarial Network.
VLSID
Kritanta Saha, Pritha Banerjee, Susmita Sur-Kolay
2025 J jnl
Efficient Memristive Spiking Neural Networks Architecture with Supervised In-Situ STDP Method.
CoRR
Santlal Prajapati, Susmita Sur-Kolay, Soumyadeep Dutta
2025 J jnl
Efficient and Fault-Tolerant Memristive Neural Networks with In-Situ Training.
CoRR
Santlal Prajapat, Manobendra Nath Mondal, Susmita Sur-Kolay
2025 J jnl
GreyConE+: Efficient Rare-Target Test Generation for FPGA HLS Designs.
ACM Trans. Reconfigurable Technol. Syst.
Mukta Debnath, Animesh Basak Chowdhury, Debasri Saha, Susmita Sur-Kolay
2024 — conf
Aggregate Encryption Individual Decryption for FPGA Bitstream Protection on Cloud.
SEED
Mukta Debnath, Krishnendu Guha, Debasri Saha, Susmita Sur-Kolay
2024 J jnl
Efficient Syndrome Decoder for Heavy Hexagonal QECC via Machine Learning.
ACM Trans. Quantum Comput.
Debasmita Bhoumik, Ritajit Majumdar, Dhiraj Madan, Dhinakaran Vinayagamurthy, Shesha Raghunathan, Susmita Sur-Kolay
2024 J jnl
Fast 3D Volumetric Image Reconstruction from 2D MRI Slices by Parallel Processing.
SN Comput. Sci.
Somoballi Ghoshal, Shreemoyee Goswami, Amlan Chakrabarti, Susmita Sur-Kolay
2024 J jnl
FragQC: An efficient quantum error reduction technique using quantum circuit fragmentation.
J. Syst. Softw.
Saikat Basu, Arnav Das, Amit Saha, Amlan Chakrabarti, Susmita Sur-Kolay
2024 J jnl
Intermediate qutrit-assisted Toffoli gate decomposition with quantum error correction.
Quantum Inf. Process.
Ritajit Majumdar, Amit Saha, Amlan Chakrabarti, Susmita Sur-Kolay
2024 J jnl
Lumbar Spine Tumor Segmentation and Localization in T2 MRI Images Using AI.
CoRR
Rikathi Pal, Sudeshna Mondal, Aditi Gupta, Priya Saha, Somoballi Ghoshal, Amlan Chakrabarti, Susmita Sur-Kolay
2024 — conf
Machine Learning based Decoding of Heavy Hexagonal QECC for Asymmetric Quantum Noise.
ISVLSI
Debasmita Bhoumik, Ritajit Majumdar, Dhiraj Madan, Susmita Sur-Kolay
2024 Misc conf
Optimized QAOA ansatz circuit design for two-body Hamiltonian problems.
VLSID
Ritajit Majumdar, Dhiraj Madan, Debasmita Bhoumik, Dhinakaran Vinayagamurthy, Shesha Raghunathan, Susmita Sur-Kolay
2024 J jnl
Panoptic Segmentation and Labelling of Lumbar Spine Vertebrae using Modified Attention Unet.
CoRR
Rikathi Pal, Priya Saha, Somoballi Ghoshal, Amlan Chakrabarti, Susmita Sur-Kolay
2024 J jnl
Resource-aware scheduling of multiple quantum circuits on a hardware device.
CoRR
Debasmita Bhoumik, Ritajit Majumdar, Susmita Sur-Kolay
2024 J jnl
Scalable Test Generation to Trigger Rare Targets in High-Level Synthesizable IPs for Cloud FPGAs.
CoRR
Mukta Debnath, Animesh Basak Chowdhury, Debasri Saha, Susmita Sur-Kolay
2023 J jnl
AgEncID: Aggregate Encryption Individual Decryption of Key for FPGA Bitstream IP Cores in Cloud.
CoRR
Mukta Debnath, Krishnendu Guha, Debasri Saha, Susmita Sur-Kolay
2023 J jnl
Concurrent Steiner Tree Selection for Global routing with EUVL Flare Reduction.
Integr.
Sudipta Paul, Tridib Mukherjee, Pritha Banerjee, Susmita Sur-Kolay
2023 J jnl
Designing Ternary Quantum Error Correcting Codes from Binary Codes.
J. Multiple Valued Log. Soft Comput.
Ritajit Majumdar, Susmita Sur-Kolay
2023 J jnl
Fast 3D Volumetric Image Reconstruction from 2D MRI Slices by Parallel Processing.
CoRR
Somoballi Ghoshal, Shremoyee Goswami, Amlan Chakrabarti, Susmita Sur-Kolay
2023 J jnl
FragQC: An Efficient Quantum Error Reduction Technique using Quantum Circuit Fragmentation.
CoRR
Saikat Basu, Arnav Das, Amit Saha, Amlan Chakrabarti, Susmita Sur-Kolay
2023 — conf
Segmentation and Labeling of Vertebra Using SegFormer Architecture.
CVIP (2)
Archan Ghosh, Debgandhar Ghosh, Somoballi Ghoshal, Amlan Chakrabarti, Susmita Sur-Kolay
2023 J jnl
Test Optimization in Memristor Crossbars Based on Path Selection.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Manobendra Nath Mondal, Susmita Sur-Kolay, Bhargab B. Bhattacharya
2022 J jnl
Efficient Machine-Learning-based decoder for Heavy Hexagonal QECC.
CoRR
Debasmita Bhoumik, Ritajit Majumdar, Dhiraj Madan, Dhinakaran Vinayagamurthy, Shesha Raghunathan, Susmita Sur-Kolay
2022 J jnl
Faster search of clustered marked states with lackadaisical quantum walks.
Quantum Inf. Process.
Amit Saha, Ritajit Majumdar, Debasri Saha, Amlan Chakrabarti, Susmita Sur-Kolay
2022 A conf
GreyConE: Greybox Fuzzing + Concolic Execution Guided Test Generation for High Level Designs.
ITC
Mukta Debnath, Animesh Basak Chowdhury, Debasri Saha, Susmita Sur-Kolay
2022 — conf
Memristive Neural Network with Efficient In-Situ Supervised Training.
SOCC
Santlal Prajaprati, Manobendra Nath Mondal, Susmita Sur-Kolay
2022 C conf
Stitch-avoiding Detailed Routing for Multiple E-Beam Lithography.
VLSI-SoC
Kritanta Saha, Pritha Banerjee, Susmita Sur-Kolay
2022 Misc conf
Stitch-avoiding Global Routing for Multiple E-Beam Lithography.
VLSID
Kritanta Saha, Sudipta Paul, Pritha Banerjee, Susmita Sur-Kolay
2022 J jnl
Test Generation for SystemC designs by interlaced Greybox Fuzzing and Concolic Execution.
CoRR
Mukta Debnath, Animesh Basak Chowdhury, Debasri Saha, Susmita Sur-Kolay
2021 Misc conf
3D Reconstruction from Micro-CT Slices for Non-Destructive Viewing inside a Fossil.
IVCNZ
Somoballi Ghoshal, Partha Bhowmick, Amlan Chakrabarti, Susmita Sur-Kolay, Sanjukta Chakravorti, Dhurjati Sengupta
2021 J jnl
A study on flare minimisation in EUV lithography by post-layout re-allocation of wire segments.
IET Circuits Devices Syst.
Sudipta Paul, Pritha Banerjee, Susmita Sur-Kolay
2021 J jnl
Depth Optimized Ansatz Circuit in QAOA for Max-Cut.
CoRR
Ritajit Majumdar, Debasmita Bhoumik, Dhiraj Madan, Dhinakaran Vinayagamurthy, Shesha Raghunathan, Susmita Sur-Kolay
2021 J jnl
FuCE: Fuzzing+Concolic Execution guided Trojan Detection in Synthesizable Hardware Designs.
CoRR
Mukta Debnath, Animesh Basak Chowdhury, Debasri Saha, Susmita Sur-Kolay
2021 J jnl
Minimization of WCRT with Recovery Assurance from Hardware Trojans for Tasks on FPGA-based Cloud.
ACM Trans. Embed. Comput. Syst.
Debasri Saha, Susmita Sur-Kolay
2021 J jnl
Optimizing Ansatz Design in QAOA for Max-cut.
CoRR
Ritajit Majumdar, Dhiraj Madan, Debasmita Bhoumik, Dhinakaran Vinayagamurthy, Shesha Raghunathan, Susmita Sur-Kolay
2020 J jnl
3D reconstruction of spine image from 2D MRI slices along one axis.
IET Image Process.
Somoballi Ghoshal, Sourav Banu, Amlan Chakrabarti, Susmita Sur-Kolay, Alok Pandit
2020 — conf
Approximate Ternary Quantum Error Correcting Code with Low Circuit Cost.
ISMVL
Ritajit Majumdar, Susmita Sur-Kolay
2020 J jnl
Asymptotically Improved Grover's Algorithm in any Dimensional Quantum System with Novel Decomposed n-qudit Toffoli Gate.
CoRR
Amit Saha, Ritajit Majumdar, Debasri Saha, Amlan Chakrabarti, Susmita Sur-Kolay
2020 — conf
Current Comparator-Based Reconfigurable Adder and Multiplier on Hybrid Memristive Crossbar.
ISVLSI
Manobendra Nath Mondal, Susmita Sur-Kolay, Bhargab B. Bhattacharya
2020 J jnl
Exploiting degeneracy to construct good ternary quantum error correcting code.
CoRR
Ritajit Majumdar, Susmita Sur-Kolay
2020 C conf
Special Session: Quantum Error Correction in Near Term Systems.
ICCD
Ritajit Majumdar, Susmita Sur-Kolay
2019 — conf
Fault Coverage of a Test Set on Structure-Preserving Siblings of a Circuit-Under-Test.
ATS
Manobendra Nath Mondal, Animesh Basak Chowdhury, Manjari Pradhan, Susmita Sur-Kolay, Bhargab B. Bhattacharya
2019 J jnl
Guided GA-Based Multiobjective Optimization of Placement and Assignment of TSVs in 3-D ICs.
IEEE Trans. Very Large Scale Integr. Syst.
Debasri Saha, Susmita Sur-Kolay
2019 — conf
Minimization of Flare in EUVL by Simultaneous Wire Segment Perturbation and Dummification.
ISVLSI
Sudipta Paul, Pritha Banerjee, Susmita Sur-Kolay
2019 Misc conf
Selective Sensitization of Useless Sneak-Paths for Test Optimization in Memristor-Arrays.
VLSID
Manobennath Mondal, Susmita Sur-Kolay, Bhargab B. Bhattacharya
2018 J jnl
Early Routability Assessment in VLSI Floorplans: A Generalized Routing Model.
CoRR
Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal
2018 J jnl
Exploring the Scope of Unconstrained Via Minimization by Recursive Floorplan Bipartitioning.
CoRR
Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal
2018 J jnl
STAIRoute: Early Global Routing using Monotone Staircases for Congestion Reduction.
CoRR
Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal
2017 C conf
A Method to Reduce Resources for Quantum Error Correction.
RC
Ritajit Majumdar, Saikat Basu, Susmita Sur-Kolay
2017 J jnl
CABA: Continuous Authentication Based on BioAura.
IEEE Trans. Computers
Arsalan Mosenia, Susmita Sur-Kolay, Anand Raghunathan, Niraj K. Jha
2017 J jnl
DISASTER: Dedicated Intelligent Security Attacks on Sensor-Triggered Emergency Responses.
IEEE Trans. Multi Scale Comput. Syst.
Arsalan Mosenia, Susmita Sur-Kolay, Anand Raghunathan, Niraj K. Jha
2017 Misc conf
Multi-objective Optimization of Placement and Assignment of TSVs in 3D ICs.
VLSID
Debasri Saha, Susmita Sur-Kolay
2017 C conf
Post-Layout Perturbation towards Stitch Friendly Layout for Multiple E-Beam Lithography.
ICCD
Sudipta Paul, Pritha Banerjee, Susmita Sur-Kolay
2017 J jnl
Wearable Medical Sensor-Based System Design: A Survey.
IEEE Trans. Multi Scale Comput. Syst.
Arsalan Mosenia, Susmita Sur-Kolay, Anand Raghunathan, Niraj K. Jha
2016 Misc conf
A Novel EPE Aware Hybrid Global Route Planner after Floorplanning.
VLSID
Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal
2016 — conf
An early global routing framework for uniform wire distribution in SoCs.
SoCC
Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal
2016 C conf
An efficient synthesis method for ternary reversible logic.
ISCAS
Saikat Basu, Sudhindu Bikash Mandal, Amlan Chakrabarti, Susmita Sur-Kolay
2016 J jnl
Embedding of signatures in reconfigurable scan architecture for authentication of intellectual properties in system-on-chip.
IET Comput. Digit. Tech.
Debasri Saha, Susmita Sur-Kolay
2016 J jnl
Error tracing in linear and concatenated quantum circuits.
CoRR
Ritajit Majumdar, Saikat Basu, Priyanka Mukhopadhyay, Susmita Sur-Kolay
2016 J jnl
Physiological Information Leakage: A New Frontier in Health Information Security.
IEEE Trans. Emerg. Top. Comput.
Arsalan Mohsen Nia, Susmita Sur-Kolay, Anand Raghunathan, Niraj K. Jha
2015 — conf
A New Method for Defining Monotone Staircases in VLSI Floorplans.
ISVLSI
Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal
2015 J jnl
Approximation algorithms for maximum independent set of a unit disk graph.
Inf. Process. Lett.
Gautam K. Das, Minati De, Sudeshna Kolay, Subhas C. Nandy, Susmita Sur-Kolay
2015 J jnl
Energy-Efficient Long-term Continuous Personal Health Monitoring.
IEEE Trans. Multi Scale Comput. Syst.
Arsalan Mohsen Nia, Mehran Mozaffari Kermani, Susmita Sur-Kolay, Anand Raghunathan, Niraj K. Jha
2015 C conf
Flare reduction in EUV Lithography by perturbation of wire segments.
VLSI-SoC
Sudipta Paul, Pritha Banerjee, Susmita Sur-Kolay
2015 J jnl
PAQCS: Physical Design-Aware Fault-Tolerant Quantum Circuit Synthesis.
IEEE Trans. Very Large Scale Integr. Syst.
Chia-Chun Lin, Susmita Sur-Kolay, Niraj K. Jha
2015 J jnl
Quantum Ternary Circuit Synthesis Using Projection Operations.
J. Multiple Valued Log. Soft Comput.
Sudhindu Bikash Mandal, Amlan Chakrabarti, Susmita Sur-Kolay
2015 J jnl
Systematic Poisoning Attacks on and Defenses for Machine Learning in Healthcare.
IEEE J. Biomed. Health Informatics
Mehran Mozaffari Kermani, Susmita Sur-Kolay, Anand Raghunathan, Niraj K. Jha
2015 J jnl
Watermarking in Hard Intellectual Property for Pre-Fab and Post-Fab Verification.
IEEE Trans. Very Large Scale Integr. Syst.
Debasri Saha, Susmita Sur-Kolay
2014 J jnl
A Modular Design to Synthesize Symmetric Functions Using Quantum Quaternary Logic.
J. Low Power Electron.
Arighna Deb, Debesh Kumar Das, Susmita Sur-Kolay
2014 — conf
A novel architecture for QPSK modulation based on time-mode signal processing.
VDAT
Sumit Saha, Bapi Kar, Susmita Sur-Kolay
2014 Misc conf
Energy-Aware H.264 Decoding.
ICDCIT
Arani Bhattacharya, Ansuman Banerjee, Susmita Sur-Kolay
2014 Misc conf
Global Routing Using Monotone Staircases with Minimal Bends.
VLSID
Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal
2014 — conf
Synthesis of Ternary Grover's Algorithm.
ISMVL
Sudhindu Bikash Mandal, Amlan Chakrabarti, Susmita Sur-Kolay
2014 — conf
Trusted sharing of intellectual property in electronic hardware design.
WESS
Debasri Saha, Susmita Sur-Kolay
2013 — conf
A Cache-Aware Strategy for H.264 Decoding on Multi-processor Architectures.
VDAT
Arani Bhattacharya, Ansuman Banerjee, Susmita Sur-Kolay, Prasenjit Basu, Bhaskar J. Karmakar
2013 — conf
Modular Design for Symmetric Functions Using Quantum Quaternary Logic.
ISED
Arighna Deb, Debesh K. Das, Susmita Sur-Kolay
2013 — conf
STAIRoute: Global routing using monotone staircase channels.
ISVLSI
Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal
2012 — conf
A Faster Hierarchical Balanced Bipartitioner for VLSI Floorplans Using Monotone Staircase Cuts.
VDAT
Bapi Kar, Susmita Sur-Kolay, Sridhar H. Rangarajan, Chittaranjan A. Mandal
2012 J jnl
A Synthesis Method for Quaternary Quantum Logic Circuits
CoRR
Sudhindu Bikash Mandal, Amlan Chakrabarti, Susmita Sur-Kolay
2012 — conf
A Synthesis Method for Quaternary Quantum Logic Circuits.
VDAT
Sudhindu Bikash Mandal, Amlan Chakrabarti, Susmita Sur-Kolay
2012 — conf
Intellectual property protection and security of SoCs - An embedded tutorial.
SoCC
Susmita Sur-Kolay
2012 J jnl
Secure Public Verification of IP Marks in FPGA Design Through a Zero-Knowledge Protocol.
IEEE Trans. Very Large Scale Integr. Syst.
Debasri Saha, Susmita Sur-Kolay
2012 Misc conf
Tutorial T4: Intellectual Property Protection and Security in System-on-Chip Design.
VLSI Design
Susmita Sur-Kolay, Swarup Bhunia
2011 J jnl
Cone-based placement for field programmable gate arrays.
IET Comput. Digit. Tech.
Pritha Banerjee, Debasri Saha, Susmita Sur-Kolay
2011 J jnl
Floorplanning for Partially Reconfigurable FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Pritha Banerjee, Megha Sangtani, Susmita Sur-Kolay
2011 J jnl
Linear Nearest Neighbor Synthesis of Reversible Circuits by Graph Partitioning
CoRR
Amlan Chakrabarti, Susmita Sur-Kolay, Ayan Chaudhury
2011 J jnl
SoC: A Real Platform for IP Reuse, IP Infringement, and IP Protection.
VLSI Design
Debasri Saha, Susmita Sur-Kolay
2011 — conf
Synthesis Techniques for Ternary Quantum Logic.
ISMVL
Sudhindu Bikash Mandal, Amlan Chakrabarti, Susmita Sur-Kolay
2011 — conf
TSV-aware Scan Chain Reordering for 3D IC.
ISVLSI
Ayan Datta, Charudhattan Nagarajan, Susmita Sur-Kolay
2010 Misc conf
A Unified Approach for IP Protection across Design Phases in a Packaged Chip.
VLSI Design
Debasri Saha, Susmita Sur-Kolay
2010 J jnl
Robust intellectual property protection of VLSI physical design.
IET Comput. Digit. Tech.
Debasri Saha, Susmita Sur-Kolay
2010 J jnl
Test pattern generation for droop faults.
IET Comput. Digit. Tech.
Debasis Mitra, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Sandip Kundu, Ashish Nigam, Sandeep K. Dey
2009 J jnl
Droop sensitivity of stuck-at fault tests.
IET Comput. Digit. Tech.
Debasis Mitra, Susmita Sur-Kolay, Bhargab B. Bhattacharya
2009 Misc conf
Encoding of Floorplans through Deterministic Perturbation.
VLSI Design
Debasri Saha, Susmita Sur-Kolay
2009 J jnl
FPGA placement using space-filling curves: Theory meets practice.
ACM Trans. Embed. Comput. Syst.
Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu, Sandip Das, Subhas C. Nandy, Subhasis Bhattacharjee
2009 J jnl
Fast Unified Floorplan Topology Generation and Sizing on Heterogeneous FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu
2009 Misc conf
Floorplanning for Partial Reconfiguration in FPGAs.
VLSI Design
Pritha Banerjee, Megha Sangtani, Susmita Sur-Kolay
2009 J jnl
MAkE: Multiobjective algorithm for k-way equipartitioning of a point set.
Appl. Soft Comput.
Sriparna Saha, Susmita Sur-Kolay, Parthasarathi Dasgupta, Sanghamitra Bandyopadhyay
2009 — conf
Secure Leakage-Proof Public Verification of IP Marks in VLSI Physical Design.
ISVLSI
Debasri Saha, Susmita Sur-Kolay
2009 J jnl
The Double Digest Problem: finding all solutions.
Int. J. Bioinform. Res. Appl.
Susmita Sur-Kolay, Satyajit Banerjee, Srabani Mukhopadhyaya, C. A. Murthy
2008 — conf
An Analytical Approach to Direct IP Protection of VLSI Floorplans.
ICIIS
Debasri Saha, Susmita Sur-Kolay
2008 — ch.
Floorplanning.
Handbook of Algorithms for Physical Design Automation
Susmita Sur-Kolay
2007 — conf
A Novel Scheme for Encoding and Watermark Embedding in VLSI Physical Design for IP Protection.
ICCTA
Debasri Saha, Parthasarathi Dasgupta, Susmita Sur-Kolay, Samar Sen-Sarma
2007 — conf
Fast Robust Intellectual Property Protection for VLSI Physical Design.
ICIT
Debasri Saha, Susmita Sur-Kolay
2007 — conf
Faster Placer for Island-Style FPGAs.
ICCTA
Pritha Banerjee, Susmita Sur-Kolay
2007 Misc conf
Floorplanning in Modern FPGAs.
VLSI Design
Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu
2007 J jnl
Hierarchical partitioning of VLSI floorplans by staircases.
ACM Trans. Design Autom. Electr. Syst.
Subhashis Majumder, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Swarup Kumar Das
2007 J jnl
Nearest Neighbour based Synthesis of Quantum Boolean Circuits.
Eng. Lett.
Amlan Chakrabarti, Susmita Sur-Kolay
2006 — conf
Multiobjective Genetic Algorithm for k-way Equipartitioning of a Point Set with Application to CAD-VLSI.
ICIT
Sriparna Saha, Susmita Sur-Kolay, Sanghamitra Bandyopadhyay, Parthasarathi Dasgupta
2006 Misc conf
Test Pattern Generation for Power Supply Droop Faults.
VLSI Design
Debasis Mitra, Subhasis Bhattacharjee, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Sujit T. Zachariah, Sandip Kundu
2005 B conf
Fast FPGA Placement using Space-filling Curve.
FPL
Pritha Banerjee, Subhasis Bhattacharjee, Susmita Sur-Kolay, Sandip Das, Subhas C. Nandy
2005 — conf
Genetic Algorithm for Double Digest Problem.
PReMI
Susmita Sur-Kolay, Satyajit Banerjee, Srabani Mukhopadhyaya, C. A. Murthy
2005 Misc conf
Hot Spots and Zones in a Chip: A Geometrician's View.
VLSI Design
Subhashis Majumder, Susmita Sur-Kolay, Subhas C. Nandy, Bhargab B. Bhattacharya, B. Chakraborty
2004 A conf
A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuit.
DATE
Chandra Tirumurti, Sandip Kundu, Susmita Sur-Kolay, Yi-Shing Chang
2004 J jnl
Manhattan-diagonal routing in channels and switchboxes.
ACM Trans. Design Autom. Electr. Syst.
Sandip Das, Susmita Sur-Kolay, Bhargab B. Bhattacharya
2004 Misc conf
Physical Design Trends and Layout-Based Fault Modeling.
VLSI Design
Susmita Sur-Kolay, Parthasarathi Dasgupta, Bhargab B. Bhattacharya, Sujit T. Zachariah
2004 — conf
Virtual Molecular Computing - Emulating DNA Molecules.
IWDC
Sanjay Goswami, Susmita Sur-Kolay
2003 — conf
Flavours of Traveling Salesman Problem in VLSI Design.
IICAI
Susmita Sur-Kolay, Satyajit Banerjee, C. A. Murthy
2001 — conf
Area(number)-balanced hierarchy of staircase channels with minimum crossing nets.
ISCAS (5)
Subhashis Majumder, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Subhas C. Nandy
2001 — conf
Combined instruction and loop parallelism in array synthesis for FPGAs.
ISSS
Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay
2001 Misc conf
Combining Instruction and Loop Level Parallelism for FPGAs.
FCCM
Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay
2001 Misc conf
Partitioning Routing Area into Zones with Distinct Pins.
VLSI Design
Koushik Sinha, Susmita Sur-Kolay, Bhargab B. Bhattacharya, P. S. Dasgupta
2001 J jnl
Slicible rectangular graphs and their optimal floorplans.
ACM Trans. Design Autom. Electr. Syst.
Parthasarathi Dasgupta, Susmita Sur-Kolay
2000 — conf
Fsimac: a fault simulator for asynchronous sequential circuits.
Asian Test Symposium
Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, Parimal Pal Chaudhuri, Rob Roy
2000 — conf
Optimal Partitioning for FPGA Based Regular Array Implementations.
PARELEC
Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay
2000 Misc conf
Topological Routing Amidst Polygonal Obstacles.
VLSI Design
Swarup Bhunia, Subhashis Majumder, Ayan Sircar, Susmita Sur-Kolay, Bhargab B. Bhattacharya
1998 J jnl
A unified approach to topology generation and optimal sizing of floorplans.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Parthasarathi Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya
1998 Misc conf
Routing of L-Shaped Channels, Switchboxes and Staircases in Manhattan-Diagonal Model.
VLSI Design
Sandip Das, Susmita Sur-Kolay, Bhargab B. Bhattacharya
1997 — conf
Slicibility of rectangular graphs and floorplan optimization.
ISPD
Parthasarathi Dasgupta, Susmita Sur-Kolay
1995 A conf
A unified approach to topology generation and area optimization of general floorplans.
ICCAD
Parthasarathi Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya
1995 — conf
Efficient Algorithms for Vertex Arboricity of Planar Graphs.
FSTTCS
Abhik Roychoudhury, Susmita Sur-Kolay
1995 Misc conf
VLSI floorplan generation and area optimization using AND-OR graph search.
VLSI Design
P. S. Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya
1992 A* conf
Canonical Embedding of Rectangular Duals with Applications to VLSI Floorplanning.
DAC
Susmita Sur-Kolay, Bhargab B. Bhattacharya
1991 C conf
The Cycle Structure of Channel Graphs in Nonslicible Floorplans and A Unified Algorithm for Feasible Routing Order.
ICCD
Susmita Sur-Kolay, Bhargab B. Bhattacharya
1988 — conf
Inherent Nonslicibility of Rectangular Duals in VLSI Floorplanning.
FSTTCS
Susmita Sur-Kolay, Bhargab B. Bhattacharya