Susana Patón - RankMe

50 papers C 12Journal 10Unranked 28

Year	Rank	Type	Title / Venue / Authors
2025	C	`conf`	All-Digital Open-Loop 2 ISCAS Nordin Zbida, Susana Patón, Eric Gutierrez
2025	J	`jnl`	MWSCAS Guest Editorial Special Issue Based on the 67th International Midwest Symposium on Circuits and Systems. IEEE Trans. Circuits Syst. I Regul. Pap. Marvin Onabajo, Susana Patón, Bibhu Datta Sahoo, Hanjun Jiang
2025	J	`jnl`	VCO-CARE: VCO-based Calibration-free Analog Readout for Electrodermal activity sensing. CoRR Leidy Mabel Alvero-Gonzalez, Matías R. Miguez, Eric Gutierrez, Juan Sapriza, Susana Patón, David Atienza, José Miranda
2024	C	`conf`	A 3 ISCAS Nordin Zbida, Susana Patón, Eric Gutierrez
2024	—	`conf`	A Comparison of Frequency-to-Digital Conversion Architectures in VCO-ADCs Built with Standard Cells. DCIS Alba Páez-Montoro, Celia López-Ongil, Mario García-Valderas, Susana Patón
2024	J	`jnl`	Analysis of VCO-Based Continuous-Time ΣΔ ADCs Using a Subset of Phases as the Feedback Signal. IEEE Trans. Circuits Syst. II Express Briefs Victor Medina, Leidy Mabel Alvero-Gonzalez, Eric Gutierrez, Luis Hernández, Susana Patón
2024	—	`conf`	Parasitic Capacitance Cancellation and SNR Improvement for Capacitance-to-Digital Converters based on a Switched-Capacitor Feedback. DCIS Michele Noviello, Andrés Quintero, Susana Patón
2024	—	`conf`	System Analysis of Capacitance-to-Digital Converters Based on a Switched-Capacitor Feedback. MWSCAS Michele Noviello, Rubén Garvi, Andrés Quintero, Susana Patón
2023	J	`jnl`	A Gray-Encoded Ring Oscillator for Efficient Frequency-to-Digital Conversion in VCO-Based ADCs. IEEE Trans. Circuits Syst. II Express Briefs Victor Medina, Rubén Garvi, Eric Gutierrez, Susana Patón, Luis Hernández
2023	—	`conf`	Ring Oscillator Circuits in Flexible aIGZO Technology for Biosignal Acquisition. DCIS Alba Páez-Montoro, Javier De Mena Pacheco, Marisa López-Vallejo, Celia López-Ongil, Susana Patón
2022	J	`jnl`	An Analysis of Noise in Multi-Bit ΣΔ Modulators with Low-Frequency Input Signals. Sensors Pablo Vera, Andreas Wiesbauer, Susana Patón
2022	C	`conf`	Optimal reconfiguration instant in ΣΔ Modulators. ISCAS Pablo Vera, Dietmar Straeussnigg, Victor Medina, Luis Hernández, Susana Patón
2020	C	`conf`	A Model of Continuous-Time Sigma Delta Modulation Based on Pulse Frequency Encoding. ISCAS Victor Medina, Susana Patón, Eric Gutierrez, Luis Hernández
2020	C	`conf`	Clock Jitter Analysis of Continuous-Time ΣΔ Modulators Based on a Relative Time-Base Projection. ISCAS Fernando Cardes, Victor Medina, Susana Patón, Luis Hernández
2020	—	`conf`	DAC mismatch shaping in Discrete Time Sigma Delta ADCs with non uniform quantizer. DCIS Pablo Vera, Susana Patón
2020	—	`conf`	Low Power Phase-Encoded MAC Accelerator for Smart Sensors with VCO-based ADCs. MWSCAS Eric Gutierrez, Carlos Perez, Susana Patón, Luis Hernández
2019	J	`jnl`	Clock Jitter Analysis of Continuous-Time ΣΔ Modulators Based on a Relative Time-Base Projection. IEEE Trans. Circuits Syst. I Regul. Pap. Fernando Cardes, Victor Medina, Susana Patón, Luis Hernández
2019	—	`conf`	Continuous Time Sigma-Delta Modulator with VCO-based integrators and optimized NTF zeros. ICECS Victor Medina, Leidy Mabel Alvero-Gonzalez, Eric Gutierrez, Susana Patón, Luis Hernández
2019	C	`conf`	Idle Tones Reduction in Digital Single-Bit ΣΔ Modulators. ISCAS Pablo Vera, Susana Patón, Dietmar Straeussnigg
2018	—	`conf`	Optimal NTF zero placement in MASH VCO-ADCs with higher order noise shaping. ICECS Eric Gutierrez, Luis Hernández, Susana Patón, Pieter Rombouts
2018	C	`conf`	VCO-ADC Resolution Enhancement Using Maximum Length Sequences. ISCAS Luis Hernández, Enrique Prefasi, Susana Patón, Eric Gutierrez
2017	—	`conf`	Noise-shaping time-interleaved ADC based on a single ring oscillator and a sampling array. MWSCAS Andrés Quintero, Carlos Perez, Eric Gutierrez, Luis Hernández, Susana Patón
2016	—	`conf`	Signal boosting to extend the bandwidth of oversampled converters. ICECS Laura Conesa-Peraleja, Susana Patón, Dietmar Straeussnigg, Andreas Wiesbauer
2015	—	`conf`	A noise coupled ΣΔ architecture using a Non Uniform Quantizer. NORCAS Juan A. Torreño, Susana Patón, Laura Conesa-Peraleja, Luis Hernández, Dietmar Straeussnigg
2014	—	`conf`	A 0.03mm ICECS Enrique Prefasi, Eric Gutierrez, Luis Hernández, Susana Patón, Sergio Walter, Ulrich Gaier
2014	—	`conf`	Time difference amplifiers to improve the dynamic range of MASH time encoded ADCs. MWSCAS Laura Conesa-Peraleja, Susana Patón
2013	C	`conf`	A distortion corrected passive RC noise shaping ADC for biomedical applications. ISCAS Luis Hernández, Enrique Prefasi, Susana Patón
2013	C	`conf`	A multi-stage and time-based continuous time ΣΔ Architecture using a Gated Ring Oscillator. ISCAS Juan A. Torreño, Susana Patón, Luis Hernández, Enrique Prefasi, M. Presicce, G. Paoli
2012	—	`conf`	Analysis of VCO based noise shaping ADCs linearized by PWM modulation. ICECS Luis Hernández, Enrique Prefasi, Susana Patón, Pieter Rombouts
2011	J	`jnl`	A 7 mW 20 MHz BW Time-Encoding Oversampling Converter Implemented in a 0.08 mm IEEE J. Solid State Circuits Enrique Prefasi, Susana Patón, Luis Hernández
2010	—	`conf`	A 0.08 mm2, 7mW Time-Encoding Oversampling Converter with 10 bits and 20MHz BW in 65nm CMOS. ESSCIRC Enrique Prefasi, Susana Patón, Luis Hernández, Richard Gaggl, Andreas Wiesbauer, Jörg Hauptmann
2010	C	`conf`	A time encoded decimation filter for noise shaped power DACs. ISCAS Luis Hernández, Jorge Fernández, Enrique Prefasi, Susana Patón
2010	C	`conf`	Continuous Time Cascade Sigma Delta Modulator without digital cancellation filters. ISCAS Susana Patón, Juan A. Torreño, Enrique Prefasi, Luis Hernández
2009	J	`jnl`	A 0.1 mm IEEE J. Solid State Circuits Enrique Prefasi, Luis Hernández, Susana Patón, Andreas Wiesbauer, Richard Gaggl, Ernesto Pun
2009	J	`jnl`	A 1.2-MHz 10-bit Continuous-Time Sigma-Delta ADC Using a Time Encoding Quantizer. IEEE Trans. Circuits Syst. II Express Briefs Luis Hernández, Enrique Prefasi, Ernesto Pun, Susana Patón
2009	—	`conf`	Second-order multi-bit ΣΔ ADC using a Pulse-Width Modulated DAC and an integrating quantizer. ICECS Enrique Prefasi, Ernesto Pun, Luis Hernández, Susana Patón
2008	—	`conf`	An A/D converter based on pulse width modulation and the walsh-hadamard transform. ICECS Luis Hernández, Susana Patón, Enrique Prefasi
2008	—	`conf`	Resolution enhancement of sigma-delta modulators using a tracking digital filter. ICECS Luis Hernández, Susana Patón
2006	—	`conf`	A 2-2 Discrete Time Cascaded ΣΔ Modulator With NTF Zero Using Interstage Feedback. ICECS Manuel Sanchez-Renedo, Susana Patón, Luis Hernández
2006	—	`conf`	Design of Cascaded Continuous-Time Sigma-Delta Modulators. ICECS Susana Patón, Manuel Sanchez-Renedo, Luis Hernández, Enrique Prefasi, Andreas Wiesbauer, Antonio Di Giandomenico, David San Segundo
2006	C	`conf`	Spectral shaping of clock jitter errors for continuous time sigma-delta modulators. ISCAS Luis Hernández, Susana Patón, Andreas Wiesbauer
2005	—	`conf`	Synthesis of sigma delta modulators employing continuous time delays. ISCAS (4) Luis Hernández, Enrique Prefasi, Susana Patón, Pieter Rombouts
2004	J	`jnl`	A 70-mW 300-MHz CMOS continuous-time ΣΔ ADC with 15-MHz bandwidth and 11 bits of resolution. IEEE J. Solid State Circuits Susana Patón, Antonio Di Giandomenico, Luis Hernández, Andreas Wiesbauer, Thomas Pötscher, Martin Clara
2004	—	`conf`	A jitter insensitive continuous-time ΣΔ modulator using transmission lines. ICECS Luis Hernández, Pieter Rombouts, Enrique Prefasi, Susana Patón, Mario Garcia, Celia López
2004	—	`conf`	Linearity enhancement techniques in low OSR, high clock rate multi-bit continuous-time sigma-delta modulators. CICC Susana Patón, Thomas Pötscher, Antonio Di Giandomenico, Klaus Kolhaupt, Luis Hernández, Andreas Wiesbauer, Martin Clara, Ramon Frutos
2004	—	`conf`	Modelling and optimization of low pass continuous-time sigma delta modulators for clock jitter noise reduction. ISCAS (1) Luis Hernández, Andreas Wiesbauer, Susana Patón, Antonio Di Giandomenico
2003	—	`conf`	A 15 MHz bandwidth sigma-delta ADC with 11 bits of resolution in 0.13μm CMOS. ESSCIRC Antonio Di Giandomenico, Susana Patón, Andreas Wiesbauer, Luis Hernández, Thomas Pötscher, Lukas Dörrer
2003	—	`conf`	Continuous time sigma-delta modulators with transmission line resonators and improved jitter and excess loop delay performance. ISCAS (1) Luis Hernández, Susana Patón
2002	—	`conf`	A superregenerative receiver for phase and frequency modulated carriers. ISCAS (3) Luis Hernández, Susana Patón
1999	—	`conf`	A continuous-time noise-shaping modulator for logarithmic A/D conversion. ISCAS (2) Luis Hernández, Susana Patón