Suriyaprakash Natarajan

52 papers A* 2A 16Misc 12Journal 9Unranked 13

Year	Rank	Type	Title / Venue / Authors
2025	A	`conf`	DRONE: Delay Defect and Marginality Targeted Scan Tests to Observe Insidious Errors. ITC Suriyaprakash Natarajan, Chaitali S. Oak, Nipun Chaplot, Vijay Kakollu, Venkata A. R. Gurram, Manish J. Mishra, Fayez Abu-gosh
2025	Misc	`conf`	Defect Severity Analysis for Analog Circuits Using Zoom Search and Hierarchical Fault Simulation. VTS Mehmet Onder, Lakshmanan Balasubramanian, Rubin A. Parekhji, Suriyaprakash Natarajan, Sule Ozev
2025	—	`conf`	Enhancing AMS Circuit Reliability: An Anomaly Dataset for Functional Safety Research in Automotive SoCs. ACM Great Lakes Symposium on VLSI Sanjay Das, Anand Menon, Omar Abiola Abioye, Afreen Fatimah Khazi-Syed, Jonathan Edward Lee, Ayush Arunachalam, Shamik Kundu, Pooja Madhusoodhanan, Prasanth Viswanathan Pillai, Rubin A. Parekhji, Arnab Raha, Suvadeep Banerjee, Suriyaprakash Natarajan, Kanad Basu
2025	Misc	`conf`	Innovation Practices Track: Frontiers in Diagnosis and Debug. VTS Suriyaprakash Natarajan, Saghir A. Shaikh, Wu-Tung Cheng, Sankaran Menon
2025	A*	`conf`	Machine Learning-Driven STL Generation for Enhancing Functional Safety of E/E Systems. DAC Sanjay Das, Swastik Bhattacharya, Anand Menon, Shamik Kundu, Pooja Madhusoodhanan, Prasanth Viswanathan Pillai, Rubin A. Parekhji, Arnab Raha, Suvadeep Banerjee, Suriyaprakash Natarajan, Kanad Basu
2024	J	`jnl`	DiagNNose: Toward Error Localization in Deep Learning Hardware-Based on VTA-TVM Stack. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shamik Kundu, Suvadeep Banerjee, Arnab Raha, Suriyaprakash Natarajan, Kanad Basu
2024	A	`conf`	Effectiveness of Timing-Aware Scan Tests in Targeting Marginal Failures and Silent Data Errors in a Data Center Processor. ITC Suriyaprakash Natarajan, Chaitali S. Oak, Vijay Kakollu, Nipun Chaplot, Soham Roy, Apurva Lonkar, Gerardo J. Perfecto Reyes
2024	J	`jnl`	Enhancing Functional Safety in Automotive AMS Circuits through Unsupervised Machine Learning. CoRR Ayush Arunachalam, Ian Kintz, Suvadeep Banerjee, Arnab Raha, Xiankun Jin, Fei Su, Viswanathan Pillai Prasanth, Rubin A. Parekhji, Suriyaprakash Natarajan, Kanad Basu
2024	—	`conf`	Generating Storage-Aware Test Sets Targeting Several Fault Models. ISVLSI Hari Addepalli, Irith Pomeranz, M. Enamul Amyeen, Suriyaprakash Natarajan, Arani Sinha, Srikanth Venkataraman
2024	Misc	`conf`	Structural Built In Self Test of Analog Circuits using ON/OFF Keying and Delay Monitors. VTS Suhas Krishna Kashyap, Chinmaye Raghavendra, Suriyaprakash Natarajan, Sule Ozev
2024	A	`conf`	TEACH: Outlier Oriented Testing of Analog/Mixed-Signal Circuits Using One-class Hyperdimensional Clustering. ITC Suhasini Komarraju, Mohamed Mejri, Abhijit Chatterjee, Suriyaprakash Natarajan, Prashant Goteti
2023	J	`jnl`	A Novel Low-Power Compression Scheme for Systolic Array-Based Deep Learning Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ayush Arunachalam, Shamik Kundu, Arnab Raha, Suvadeep Banerjee, Suriyaprakash Natarajan, Kanad Basu
2023	J	`jnl`	Analysis and Mitigation of DRAM Faults in Sparse-DNN Accelerators. IEEE Des. Test Shamik Kundu, Arnab Raha, Suvadeep Banerjee, Suriyaprakash Natarajan, Kanad Basu
2023	A	`conf`	Enhanced ML-Based Approach for Functional Safety Improvement in Automotive AMS Circuits. ITC Ayush Arunachalam, Sanjay Das, Monikka Rajan, Fei Su, Xiankun Jin, Suvadeep Banerjee, Arnab Raha, Suriyaprakash Natarajan, Kanad Basu
2023	J	`jnl`	Trouble-Shooting at GAN Point: Improving Functional Safety in Deep Learning Accelerators. IEEE Trans. Computers Shamik Kundu, Suvadeep Banerjee, Arnab Raha, Fei Su, Suriyaprakash Natarajan, Kanad Basu
2022	A*	`conf`	A defect tolerance framework for improving yield. DAC Shiva Shankar Thiagarajan, Suriyaprakash Natarajan, Yiorgos Makris
2022	A	`conf`	DEFCON: Defect Acceleration through Content Optimization. ITC Suriyaprakash Natarajan, Abhijit Sathaye, Chaitali Oak, Nipun Chaplot, Suvadeep Banerjee
2022	—	`conf`	Using Fault Detection Tests to Produce Diagnostic Tests Targeting Large Sets of Candidate Faults. ATS Hari Addepalli, Irith Pomeranz, M. Enamul Amyeen, Suriyaprakash Natarajan, Arani Sinha, Srikanth Venkataraman
2021	—	`conf`	HardCompress: A Novel Hardware-based Low-power Compression Scheme for DNN Accelerators. ISQED Ayush Arunachalam, Shamik Kundu, Arnab Raha, Suvadeep Banerjee, Suriyaprakash Natarajan, Kanad Basu
2021	J	`jnl`	Toward Functional Safety of Systolic Array-Based Deep Learning Hardware Accelerators. IEEE Trans. Very Large Scale Integr. Syst. Shamik Kundu, Suvadeep Banerjee, Arnab Raha, Suriyaprakash Natarajan, Kanad Basu
2021	Misc	`conf`	Two Pattern Timing Tests Capturing Defect-Induced Multi-Gate Delay Impact of Shorts. VTS Sujay Pandey, Zhiwei Liao, Shreyas Nandi, Suriyaprakash Natarajan, Arani Sinha, Adit D. Singh, Abhijit Chatterjee
2020	Misc	`conf`	Automated Design For Yield Through Defect Tolerance. VTS Suriyaprakash Natarajan, Andres F. Malavasi, Pascal Andreas Meinerzhagen
2020	A	`conf`	Automating Design For Yield: Silicon Learning to Predictive Models and Design Optimization. ITC Srikanth Venkataraman, Pongpachara Limpisathian, Pascal Meinerzhagen, Suriyaprakash Natarajan, Eric Yang
2020	A	`conf`	SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts. ITC Sujay Pandey, Zhiwei Liao, Shreyas Nandi, Sanya Gupta, Suriyaprakash Natarajan, Arani Sinha, Adit D. Singh, Abhijit Chatterjee
2017	J	`jnl`	A novel test compression algorithm for analog circuits to decrease production costs. Integr. Seyed Nematollah Ahmadyan, Suriyaprakash Natarajan, Shobha Vasudevan
2016	J	`jnl`	Analysis of Defects and Variations in Embedded Spin Transfer Torque (STT) MRAM Arrays. IEEE J. Emerg. Sel. Topics Circuits Syst. Ashwin Chintaluri, Helia Naeimi, Suriyaprakash Natarajan, Arijit Raychowdhury
2016	—	`conf`	Every test makes a difference: Compressing analog tests to decrease production costs. ASP-DAC Seyed Nematollah Ahmadyan, Suriyaprakash Natarajan, Shobha Vasudevan
2016	A	`conf`	Fault simulation for analog test coverage. ITC Jyotsna Sequeira, Suriyaprakash Natarajan, Prashant Goteti, Nitin Chaudhary
2016	Misc	`conf`	Infant mortality tests for analog and mixed-signal circuits. VTS Suvadeep Banerjee, Suriyaprakash Natarajan
2016	Misc	`conf`	Session 4B - Panel data analytics in semiconductor manufacturing. VTS Suriyaprakash Natarajan, Li-C. Wang
2015	—	`conf`	A Model Study of Defects and Faults in Embedded Spin Transfer Torque (STT) MRAM Arrays. ATS Ashwin Chintaluri, Abhinav Parihar, Suriyaprakash Natarajan, Helia Naeimi, Arijit Raychowdhury
2015	A	`conf`	Fast eye diagram analysis for high-speed CMOS circuits. DATE Seyed Nematollah Ahmadyan, Chenjie Gu, Suriyaprakash Natarajan, Eli Chiprout, Shobha Vasudevan
2015	—	`conf`	Identifying DC bias conditions for maximum DC current in digitally-assisted analog design. ICECS Chong Li, Suriyaprakash Natarajan, Chuanjin Richard Shi
2014	A	`conf`	Spatio-temporal wafer-level correlation modeling with progressive sampling: A pathway to HVM yield estimation. ITC Ali Ahmadi, Ke Huang, Suriyaprakash Natarajan, John M. Carulli Jr., Yiorgos Makris
2013	—	`conf`	Framework for analog test coverage. ISQED Debesh Bhatta, Ishita Mukhopadhyay, Suriyaprakash Natarajan, Prashant Goteti, Bin Xue
2013	A	`conf`	Scalable and efficient analog parametric fault identification. ICCAD Mustafa Berke Yelten, Suriyaprakash Natarajan, Bin Xue, Prashant Goteti
2013	Misc	`conf`	Special session 12B: Panel post-silicon validation & test in huge variance era. VTS Takahiro J. Yamaguchi, Jacob A. Abraham, Gordon W. Roberts, Suriyaprakash Natarajan, Dennis J. Ciplickas
2011	Misc	`conf`	The bang for the buck with resiliency: Yield or field? VTS Arani Sinha, Suriyaprakash Natarajan
2011	Misc	`conf`	The buck stops with wafer test: Dream or reality? VTS Suriyaprakash Natarajan, Arani Sinha
2010	Misc	`conf`	Innovative practices session 9C: Implications of power delivery network for validation and testing. VTS Suriyaprakash Natarajan
2010	A	`conf`	Path coverage based functional test generation for processor marginality validation. ITC Suriyaprakash Natarajan, Arun Krishnamachary, Eli Chiprout, Rajesh Galivanche
2008	J	`jnl`	Case Study on Speed Failure Causes in a Microprocessor. IEEE Des. Test Comput. Kip Killpack, Suriyaprakash Natarajan, Arun Krishnamachary, Pouria Bastani
2008	A	`conf`	On Accelerating Path Delay Fault Simulation of Long Test Sequences. ITC I-De Huang, Yi-Shing Chang, Suriyaprakash Natarajan, Ramesh Sharma, Sandeep K. Gupta
2008	—	`conf`	On efficient generation of instruction sequences to test for delay defects in a processor. ACM Great Lakes Symposium on VLSI Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham, Suriyaprakash Natarajan
2007	—	`conf`	The Region-Exhaustive Fault Model. ATS Abhijit Jas, Suriyaprakash Natarajan, Srinivas Patil
2006	Misc	`conf`	Path Delay Fault Simulation on Large Industrial Designs. VTS Suriyaprakash Natarajan, Srinivas Patil, Sreejit Chakravarty
2006	—	`conf`	Selecting High-Quality Delay Tests for Manufacturing Test and Debug. DFT Hangkyu Lee, Suriyaprakash Natarajan, Srinivas Patil, Irith Pomeranz
2005	—	`conf`	Untestable Multi-Cycle Path Delay Faults in Industrial Designs. Asian Test Symposium Manan Syal, Michael S. Hsiao, Suriyaprakash Natarajan, Sreejit Chakravarty
2002	A	`conf`	XIDEN: Crosstalk Target Identification Framework. ITC Shahin Nazarian, Hang Huang, Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer
2001	A	`conf`	Switch-level delay test of domino logic circuits. ITC Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer
1999	A	`conf`	Switch-level delay test. ITC Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer
1998	—	`conf`	Process Variations and their Impact on Circuit Operation. DFT Suriyaprakash Natarajan, Melvin A. Breuer, Sandeep K. Gupta