Surin Kittitornkun

20 papers A 2B 2C 2Journal 10Unranked 4
YearRankTypeTitle / Venue / Authors
2021 J jnl
Optimizing MultiStack Parallel (MSP) Sorting Algorithm.
J. Mobile Multimedia
Apisit Rattanatranurak, Surin Kittitornkun
2020 J jnl
A MultiStack Parallel (MSP) Partition Algorithm Applied to Sorting.
J. Mobile Multimedia
Apisit Rattanatranurak, Surin Kittitornkun
2017 J jnl
A Spatio-Temporal malware and country clustering algorithm: 2012 IIJ MITF case study.
Int. J. Inf. Sec.
Khamphao Sisaat, Surin Kittitornkun, Hiroaki Kikuchi, Chaxiong Yukonhiatou, Masato Terada, Hiroshi Ishii
2016 J jnl
Parallel Partition and Merge QuickSort (PPMQSort) on Multicore CPUs.
J. Supercomput.
Ratthaslip Ranokphanuwat, Surin Kittitornkun
2013 J jnl
Time Zone Correlation Analysis of Malware/Bot Downloads.
IEICE Trans. Commun.
Khamphao Sisaat, Hiroaki Kikuchi, Shunji Matsuo, Masato Terada, Masashi Fujiwara, Surin Kittitornkun
2012 — conf
Geographical Visualization of Malware Download for Anomaly Detection.
AsiaJCIS
N. Hiroguchi, Hiroaki Kikuchi, Khamphao Sisaat, Surin Kittitornkun
2010 — conf
Massively Parallel Cuckoo Pattern Matching Applied for NIDS/NIPS.
DELTA
Thinh Ngoc Tran, Surin Kittitornkun
2009 J jnl
PAMELA: Pattern Matching Engine with Limited-Time Update for NIDS/NIPS.
IEICE Trans. Inf. Syst.
Thinh Ngoc Tran, Surin Kittitornkun, Shigenori Tomiyama
2007 — conf
Applying Cuckoo Hashing for FPGA-based Pattern Matching in NIDS/NIPS.
FPT
Tran Ngoc Thinh, Surin Kittitornkun, Shigenori Tomiyama
2007 C conf
FPGA-Based Cuckoo Hashing for Pattern Matching in NIDS/NIPS.
APNOMS
Thinh Ngoc Tran, Surin Kittitornkun
2006 A conf
MT-ClustalW: multithreading multiple sequence alignment.
IPDPS
Kridsadakorn Chaichoompu, Surin Kittitornkun, Sissades Tongsima
2006 A conf
Manifold similarity search of DNA sequences with reconfigurable hardware.
FPGA
Thinh Ngoc Tran, Surin Kittitornkun, Shigenori Tomiyama
2003 J jnl
Mapping deep nested do-loop DSP algorithms to large scale FPGA array structures.
IEEE Trans. Very Large Scale Integr. Syst.
Surin Kittitornkun, Yu Hen Hu
2003 J jnl
Processor Array Synthesis from Shift-Variant Deep Nested Do Loops.
J. Supercomput.
Surin Kittitornkun, Yu Hen Hu
2003 — conf
Supersystolic arrays on large-scale FPGA structures.
ISCAS (2)
Surin Kittitornkun, Yu Hen Hu
2001 J jnl
Efficient Implementation of Nested-Loop Multimedia Algorithms.
EURASIP J. Adv. Signal Process.
Surin Kittitornkun, Yu Hen Hu
2001 J jnl
Frame-level pipelined motion estimation array processor.
IEEE Trans. Circuits Syst. Video Technol.
Surin Kittitornkun, Yu Hen Hu
2001 C conf
Low bit rate video sequence coding artifact removal.
MMSP
Seungjoon Yang, Surin Kittitornkun, Yu Hen Hu, Truong Q. Nguyen, Damon L. Tull
2000 B conf
Blocking Artifact Free Inverse Discrete Cosine Transform.
ICIP
Seungjoon Yang, Surin Kittitornkun, Yu Hen Hu, Truong Q. Nguyen, Damon L. Tull
2000 B conf
Data Partitioning and Reversible Variable Length Codes for Robust Video Communications.
Data Compression Conference
Adam H. Li, Surin Kittitornkun, Yu Hen Hu, Dong-Seek Park, John D. Villasenor