Suresh Purini - RankMe

40 papers A 3B 7C 2Misc 8Journal 9Unranked 11

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A Critical Review and Evaluation of LLMs for RTL Generation. IEEE Access Arun Ravindran, Aditya Patra, Vahid Babaey, Suresh Purini
2025	—	`conf`	ArchXBench: A Complex Digital Systems Benchmark Suite for LLM Driven RTL Synthesis. MLCAD Suresh Purini, Siddhant Garg, Mudit Gaur, Sankalp Bhat, Sohan Mupparapu, Arun Ravindran
2025	J	`jnl`	ArchXBench: A Complex Digital Systems Benchmark Suite for LLM Driven RTL Synthesis. CoRR Suresh Purini, Siddhant Garg, Mudit Gaur, Sankalp Bhat, Sohan Mupparapu, Arun Ravindran
2024	J	`jnl`	Accelerating local laplacian filters on FPGAs. CoRR Shashwat Khandelwal, Ziaul Choudhury, Shashwat Shrivastava, Suresh Purini
2024	Misc	`conf`	Seer: A Framework for Optimizing Traffic Camera Placement and Deep Learning Inference at the Edge for Vehicle Path Reconstruction. SEC Siddhant Jain, Kunal Jain, Arun Ravindran, Suresh Purini
2023	B	`conf`	A Cloud-Fog Architecture for Video Analytics on Large Scale Camera Networks Using Semantic Scene Analysis. CCGrid Kunal Jain, Kishan Sairam Adapa, Kunwar Grover, Ravi Kiran Sarvadevabhatla, Suresh Purini
2023	B	`conf`	Building Low-Latency Order Books with Hybrid Binary-Linear Search Data Structures on FPGAs. FPL Vaibhav Kashera, Siddhant Jain, Abhishek Banerjee, Suresh Purini
2023	J	`jnl`	FlowPix: Accelerating Image Processing Pipelines on an FPGA Overlay using a Domain Specific Compiler. ACM Trans. Archit. Code Optim. Ziaul Choudhury, Anish Gulati, Suresh Purini
2023	—	`conf`	Hardware Accelerator for Transformer based End-to-End Automatic Speech Recognition System. IPDPS Workshops Shaarada D. Yamini, Mirishkar Sai Ganesh, Anil Kumar Vuppala, Suresh Purini
2022	—	`conf`	Accuracy Configurable FPGA Implementation of Harris Corner Detection. ISVLSI Shivani Maurya, Ziaul Choudhury, Suresh Purini
2022	J	`jnl`	An FPGA Overlay for CNN Inference with Fine-grained Flexible Parallelism. ACM Trans. Archit. Code Optim. Ziaul Choudhury, Shashwat Shrivastava, Lavanya Ramapantulu, Suresh Purini
2022	—	`conf`	Systolic Array based FPGA accelerator for Yolov3-tiny. HPEC Prithvi Velicheti, Sivani Pentapati, Suresh Purini
2021	J	`jnl`	Pricing strategies of an oligopolist in federated cloud markets. J. Cloud Comput. Yash Khandelwal, Arushi Dogra, Karthik Ganti, Suresh Purini, Puduru V. Reddy
2020	B	`conf`	Accelerating Local Laplacian Filters on FPGAs. FPL Shashwat Khandelwal, Ziaul Choudhury, Shashwat Shrivastava, Suresh Purini
2020	B	`conf`	Bitwidth customization in image processing pipelines using interval analysis and SMT solvers. CC Suresh Purini, Vinamra Benara, Ziaul Choudhury, Uday Bondhugula
2020	B	`conf`	FPGA Accelerator for Stereo Vision using Semi-Global Matching through Dependency Relaxation. FPL Shashwat Shrivastava, Ziaul Choudhury, Shashwat Khandelwal, Suresh Purini
2020	Misc	`conf`	Model Checking as a Service using Dynamic Resource Scaling. HiPC Surya Teja Palavalasa, Yuvraj Singh, Adhish Singla, Suresh Purini, Venkatesh Choppella
2018	Misc	`conf`	A Multi-Cloud Marketplace Model with Multiple Brokers for IaaS Layer and Generalized Stable Matching. UCC Shrenik Jain, Suresh Purini, Puduru V. Reddy
2018	—	`conf`	Cloud Federation Formation in Oligopolistic Markets. Euro-Par Yash Khandelwal, Karthik Ganti, Suresh Purini, Puduru V. Reddy
2018	—	`conf`	Flow Sensor IoT Node for Wi-Fi Equipped Apartments and Gated Communities. IEEE SENSORS Deepak Awasthi, Syed Azeemuddin, Suresh Purini, Annesha Mazumder
2018	Misc	`conf`	Share-a-GPU: Providing Simple and Effective Time-Sharing on GPUs. HiPC Shaleen Garg, Kishore Kothapalli, Suresh Purini
2018	J	`jnl`	Synthesizing Power and Area Efficient Image Processing Pipelines on FPGAs using Customized Bit-widths. CoRR Vinamra Benara, Sahithi Rampalli, Ziaul Choudhury, Suresh Purini, Uday Bondhugula
2017	—	`conf`	Plagiarism Detection in Programming Assignments Using Deep Features. ACPR Jitendra Yasaswi, Suresh Purini, C. V. Jawahar
2017	—	`conf`	Unsupervised Learning Based Approach for Plagiarism Detection in Programming Assignments. ISEC Jitendra Yasaswi, Sri Kailash, Anil Chilupuri, Suresh Purini, C. V. Jawahar
2016	B	`conf`	A DSL Compiler for Accelerating Image Processing Pipelines on FPGAs. PACT Nitin Chugh, Vinay Vasista, Suresh Purini, Uday Bondhugula
2016	C	`conf`	A Hybrid CPU+GPU Working-Set Dictionary. ISPDC Ziaul Choudhury, Suresh Purini, Shiva Rama Krishna
2016	—	`conf`	Accurus: A Fast Convergence Technique for Accuracy Configurable Approximate Adder Circuits. ISVLSI Vinamra Benara, Suresh Purini
2016	—	`conf`	Anuvaad Pranaali: A RESTful API for Machine Translation. ICSOC Workshops Nehal J. Wani, Sharada Prasanna Mohanty, Suresh Purini, Dipti Misra Sharma
2016	C	`conf`	Distributed Safety Verification Using Vertex Centric Programming Model. ISPDC Adhish Singla, Krishnaji Desai, Suresh Purini, Venkatesh Choppella
2016	Misc	`conf`	Fast algorithms for optimal coalition formation in federated clouds. UCC Yash Khandelwal, Suresh Purini, Puduru V. Reddy
2016	A	`conf`	Re-targeting Optimization Sequences from Scalar Processors to FPGAs in HLS compilers (Abstract Only). FPGA Ronak Kogta, Suresh Purini, Ajit Mathew
2015	B	`conf`	Dynamic Memory and Core Scaling in Virtual Machines. CLOUD Kapil Kumar, Nehal J. Wani, Suresh Purini
2014	—	`conf`	RLC - A Reliable Approach to Fast and Efficient Live Migration of Virtual Machines in the Clouds. IEEE CLOUD Sanidhya Kashyap, Jaspal Singh Dhillon, Suresh Purini
2013	J	`jnl`	Finding good optimization sequences covering program space. ACM Trans. Archit. Code Optim. Suresh Purini, Lakshya Jain
2013	Misc	`conf`	Virtual Machine Coscheduling: A Game Theoretic Approach. UCC Jaspal Singh Dhillon, Suresh Purini, Sanidhya Kashyap
2010	J	`jnl`	Design of Low Power Systems Using Inexact Logic Circuits. J. Low Power Electron. Bharghava Rajaram, Abinesh Ramachandran, Suresh Purini, R. Govindatajulu
2010	Misc	`conf`	Inexact Decision Circuits: An Application to Hamming Weight Threshold Voting. VLSI Design Bharghava Rajaram, Abinesh Ramachandran, Suresh Purini, Govindarajulu Regeti
2010	Misc	`conf`	Transition Inversion Based Low Power Data Coding Scheme for Buffered Data Transfer. VLSI Design Abinesh Ramachandran, Bharghava Rajaram, Suresh Purini, Govindarajulu Regeti
2008	A	`conf`	Amplifying ZPP^SAT[1] and the Two Queries Problem. CCC Richard Chang, Suresh Purini
2007	A	`conf`	Bounded Queries and the NP Machine Hypothesis. CCC Richard Chang, Suresh Purini