Surendra S. Rathod

13 papers Journal 9Unranked 4
YearRankTypeTitle / Venue / Authors
2024 J jnl
Modelling and design of asynchronous receptive circuit for cone pathways.
Integr.
Payal Shah, Satvik Sawant, Reena Sonkusare, Surendra S. Rathod
2020 — conf
Suppression of SSN in High-Speed Circuits using 1-D EBG structure.
ICCCNT
Sayli Shinde, Manisha Bansode, Pramod P. Bhavarthe, Surendra S. Rathod
2019 J jnl
SOI FinFET based instrumentation amplifier for biomedical applications.
Microelectron. J.
Reena Sonkusare, Omkar Joshi, Surendra S. Rathod
2017 — conf
Synapse Circuits Implementation and Analysis in 180 nm MOSFET and CNFET Technology.
VDAT
Sushma Srivastava, Surendra S. Rathod
2015 — conf
Analysis of CMOS inhibitory synapse with varying neurotransmitter concentration, reuptake time and spread delay.
VDAT
Pradyumna Galgali, Surendra S. Rathod
2015 — conf
Implementing a cloud based Xilinx ISE FPGA design platform for integrated remote labs.
ICACCI
Jinalkumar Doshi, Pratiksha Patil, Zalak Dave, Ganesh Gore, Jonathan Joshi, Reena Sonkusare, Surendra S. Rathod
2012 J jnl
Analysis of double-gate FinFET-based address decoder for radiation-induced single-event-transients.
IET Circuits Devices Syst.
Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta
2012 J jnl
Dg-FinFET-Based SRAM Configurations for Increased SEU Immunity.
J. Circuits Syst. Comput.
Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta
2011 J jnl
A low-noise, process-variation-tolerant double-gate FinFET based sense amplifier.
Microelectron. Reliab.
Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta
2011 J jnl
Alpha-particle-induced effects in partially depleted silicon on insulator device: With and without body contact.
IET Circuits Devices Syst.
Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta
2011 J jnl
Electrical performance study of 25 nm Omega-FinFET under the influence of gamma radiation: A 3D simulation.
Microelectron. J.
Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta
2010 J jnl
A proposed DG-FinFET based SRAM cell design with RadHard capabilities.
Microelectron. Reliab.
Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta
2010 J jnl
Robust Double Gate FinFET Based Sense Amplifier Design Using Independent Gate Control.
J. Low Power Electron.
Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta