Surajit Kumar Roy

39 papers A 1C 1Misc 2Journal 12Unranked 23
YearRankTypeTitle / Venue / Authors
2025 — conf
A Behavioral Trust-Based Framework for Multi-Attack Detection in Social Internet of Things.
ANTS
Priya Mukherjee, Surajit Kumar Roy, Chandan Giri
2025 J jnl
Localisation of malicious nets in integrated circuits using unsupervised methodologies.
Integr.
Tapobrata Dhar, Chandan Giri, Surajit Kumar Roy
2025 — conf
Optimization and Security of AI Models for Deployment at Edge: A Comprehensive Review.
ISVLSI
Hafizur Rahaman, Chandan Giri, Surajit Kumar Roy, Amlan Chakrabarti
2024 J jnl
Built-in Self-prevention (BISP) for runtime ageing effects of TSVs in 3D ICs.
Integr.
Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri
2023 — conf
Cost Effective Single Target Sample Preparation on Digital Microfluidic Biochip.
iSES
Sourav Ghosh, Surajit Kumar Roy, Chandan Giri
2023 J jnl
Fault Detection and Diagnosis of DMFB Using Concurrent Electrodes Actuation.
J. Electron. Test.
Sourav Ghosh, Surajit Kumar Roy, Chandan Giri
2023 J jnl
Threshold Analysis Using Probabilistic Xgboost Classifier for Hardware Trojan Detection.
J. Electron. Test.
Tapobrata Dhar, Ranit Das, Chandan Giri, Surajit Kumar Roy
2022 J jnl
A Cost-Effective Built-In Self-Test Mechanism for Post-Manufacturing TSV Defects in 3D ICs.
ACM J. Emerg. Technol. Comput. Syst.
Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri
2022 J jnl
Frequency-scaled thermal-aware test scheduling for 3D ICs using machine learning based temperature estimation.
Microelectron. J.
Subhajit Chatterjee, Surajit Kumar Roy, Chandan Giri, Hafizur Rahaman
2021 J jnl
Hardware Trojan Horse Detection through Improved Switching of Dormant Nets.
ACM J. Emerg. Technol. Comput. Syst.
Tapobrata Dhar, Surajit Kumar Roy, Chandan Giri
2021 J jnl
TSV-Cluster Defect Tolerance Using Tree-Based Redundancy for Yield Improvement of 3-D ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri
2021 J jnl
Testing and Diagnosis of Digital Microfluidic Biochips using Multiple Droplets.
J. Electron. Test.
Sourav Ghosh, Surajit Kumar Roy, Chandan Giri
2020 — conf
An Efficient Test Scheduling to Co-optimize Test Time and Peak Power for 3D ICs.
ISDCS
Subhajit Chatterjee, Surajit Kumar Roy, Chandan Giri, Hafizur Rahaman
2020 — conf
Hardware Trojan Detection Using Improved Testability Measures.
ISDCS
Priyanka Naskar, Tapobrata Dhar, Surajit Kumar Roy
2019 Misc conf
Hardware Trojan Detection by Stimulating Transitions in Rare Nets.
VLSID
Tapobrata Dhar, Surajit Kumar Roy, Chandan Giri
2019 J jnl
Identification of Random/Clustered TSV Defects in 3D IC During Pre-Bond Testing.
J. Electron. Test.
Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri
2019 — conf
Iterative Parallel Test to Detect and Diagnose Multiple Defects for Digital Microfluidic Biochip.
ATS
Sourav Ghosh, Dolan Maity, Arijit Chowdhury, Surajit Kumar Roy, Chandan Giri
2018 — conf
Detecting Hardware Trojans by Reducing Rarity of Transitions in ICs.
VDAT
Tapobrata Dhar, Surajit Kumar Roy, Chandan Giri
2018 — conf
Identification of Faulty TSV with a Built-In Self-Test Mechanism.
ATS
Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri, Hafizur Rahaman
2018 Misc conf
Identification of Faulty TSVs in 3D IC During Pre-Bond Testing.
VLSID
Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri
2017 A conf
Design-for-test and test time optimization for 3D SOCs.
ITC
Surajit Kumar Roy, Chandan Giri
2017 — conf
Faulty TSVs Identification in 3D IC Using Pre-bond Testing.
VDAT
Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri
2017 — conf
Modeling and Analysis of Transient Heat for 3D IC.
VDAT
Subhajit Chatterjee, Surajit Kumar Roy, Chandan Giri, Hafizur Rahaman
2017 — conf
TSV repairing for 3D ICs using redundant TSV.
ISED
Sudeep Ghosh, Surajit Kumar Roy, Hafizur Rahaman, Chandan Giri
2016 J jnl
Optimization of Test Wrapper for TSV Based 3D SOCs.
J. Electron. Test.
Surajit Kumar Roy, Chandan Giri, Hafizur Rahaman
2015 C conf
A thermal estimation model for 3D IC using liquid cooled microchannels and thermal TSVs.
VLSI-SoC
Surajit Kumar Roy, Supriyo Mandal, Chandan Giri, Hafizur Rahaman
2015 J jnl
Optimisation of test architecture in three-dimensional stacked integrated circuits for partial stack/complete stack using hard system-on-chips.
IET Comput. Digit. Tech.
Surajit Kumar Roy, Chandan Giri, Hafizur Rahaman
2015 — conf
Recovery of faulty TSVs in 3D ICs.
ISQED
Surajit Kumar Roy, Kaustav Roy, Chandan Giri, Hafizur Rahaman
2015 — conf
Test Time Optimization for 3D-SICs Having Multiple Towers.
iNIS
Sumit Dhuwalia, Nikhil Khemka, Prince Gupta, Surajit Kumar Roy, Chandan Giri
2014 — conf
Session Based Core Test Scheduling for 3D SOCs.
ISVLSI
Surajit Kumar Roy, Payel Ghosh, Hafizur Rahaman, Chandan Giri
2013 — conf
Faulty TSVs identification and recovery in 3D stacked ICs during pre-bond testing.
3DIC
Surajit Kumar Roy, Sobitri Chatterjee, Chandan Giri, Hafizur Rahaman
2013 — conf
Optimizing test architecture of 3D stacked ICs for partial stack/complete stack using hard SoCs.
IDT
Surajit Kumar Roy, Chandan Giri, Hafizur Rahaman
2013 — conf
Power constraints test scheduling of 3D stacked ICs.
IDT
Surajit Kumar Roy, Joy Sankar Sengupta, Chandan Giri, Hafizur Rahaman
2012 — conf
Identifying Faulty TSVs in 3D Stacked IC during Pre-bond Testing.
ISED
Surajit Kumar Roy, Sobitri Chatterjee, Chandan Giri
2012 — conf
Post-bond Stack Testing for 3D Stacked IC.
VDAT
Surajit Kumar Roy, Dona Roy, Chandan Giri, Hafizur Rahaman
2012 — conf
Testing 3D stacked ICs for post-bond partial/complete stack.
MWSCAS
Surajit Kumar Roy, Dona Roy, Chandan Giri, Hafizur Rahman
2011 — conf
Optimization of Test Wrapper for TSV Based 3D SOCs.
ISED
Surajit Kumar Roy, Chandan Giri, Sourav Ghosh, Hafizur Rahaman
2011 — conf
Optimizing Test Architecture for TSV Based 3D Stacked ICs Using Hard SOCs.
ISED
Surajit Kumar Roy, Chandan Giri, Arnab Chakraborty, Subhro Mukherjee, Debesh K. Das, Hafizur Rahaman
2011 — conf
Optimizing Test Wrapper for Embedded Cores Using TSV Based 3D SOCs.
ISVLSI
Surajit Kumar Roy, Chandan Giri, Sourav Ghosh, Hafizur Rahaman