Suraj Sindia

19 papers A 1C 1Misc 5Journal 5Unranked 7
YearRankTypeTitle / Venue / Authors
2015 J jnl
Defect Level Constrained Optimization of Analog and Radio Frequency Specification Tests.
J. Electron. Test.
Suraj Sindia, Vishwani D. Agrawal
2015 Misc conf
Innovative practices session 2C: New technologies, new challenges - 2.
VTS
Suraj Sindia
2014 J jnl
A Test Time Theorem and its Applications.
J. Electron. Test.
Praveen Venkataramani, Suraj Sindia, Vishwani D. Agrawal
2014 — conf
Specification test minimization for given defect level.
LATW
Suraj Sindia, Vishwani D. Agrawal
2013 — conf
A test time theorem and its applications.
LATW
Praveen Venkataramani, Suraj Sindia, Vishwani D. Agrawal
2013 Misc conf
Finding best voltage and frequency to shorten power-constrained test time.
VTS
Praveen Venkataramani, Suraj Sindia, Vishwani D. Agrawal
2013 A conf
High sensitivity test signatures for unconventional analog circuit test paradigms.
ITC
Suraj Sindia, Vishwani D. Agrawal
2013 J jnl
Neural Network Guided Spatial Fault Resilience in Array Processors.
J. Electron. Test.
Suraj Sindia, Vishwani D. Agrawal
2012 J jnl
Defect Level and Fault Coverage in Coefficient Based Analog Circuit Testing.
J. Electron. Test.
Suraj Sindia, Vishwani D. Agrawal, Virendra Singh
2012 C conf
Impact of process variations on computers used for image processing.
ISCAS
Suraj Sindia, Fa Foster Dai, Vishwani D. Agrawal, Virendra Singh
2012 J jnl
Parametric Fault Testing of Non-Linear Analog Circuits Based on Polynomial and V-Transform Coefficients.
J. Electron. Test.
Suraj Sindia, Vishwani D. Agrawal, Virendra Singh
2012 — conf
Tailoring Tests for Functional Binning of Integrated Circuits.
Asian Test Symposium
Suraj Sindia, Vishwani D. Agrawal
2012 Misc conf
Towards spatial fault resilience in array processors.
VTS
Suraj Sindia, Vishwani D. Agrawal
2011 Misc conf
Non-linear analog circuit test and diagnosis under process variation using V-Transform coefficients.
VTS
Suraj Sindia, Vishwani D. Agrawal, Virendra Singh
2011 — conf
Test and Diagnosis of Analog Circuits Using Moment Generating Functions.
Asian Test Symposium
Suraj Sindia, Vishwani D. Agrawal, Virendra Singh
2011 — conf
Testing linear and non-linear analog circuits using moment generating functions.
LATW
Suraj Sindia, Vishwani D. Agrawal, Virendra Singh
2010 Misc conf
Parametric Fault Diagnosis of Nonlinear Analog Circuits Using Polynomial Coefficients.
VLSI Design
Suraj Sindia, Virendra Singh, Vishwani D. Agrawal
2009 — conf
Multi-tone Testing of Linear and Nonlinear Analog Circuits Using Polynomial Coefficients.
Asian Test Symposium
Suraj Sindia, Virendra Singh, Vishwani D. Agrawal
2009 — conf
Polynomial coefficient based DC testing of non-linear analog circuits.
ACM Great Lakes Symposium on VLSI
Suraj Sindia, Virendra Singh, Vishwani D. Agrawal