Sunwoo Lee - RankMe

15 papers A* 3Journal 6Unranked 6

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A Real-Time Speech Enhancement Processor for Hearing Aids in 28-nm CMOS. IEEE J. Solid State Circuits Sungjin Park, Sunwoo Lee, Jeongwoo Park, Hyeong-Seok Choi, Kyogu Lee, Dongsuk Jeon
2025	—	`conf`	An 83.16-TOPS/W Voltage-Scalable Time-Domain CNN Accelerator with Full-Swing Delay Cell and Gray-Code TDC in 28-nm CMOS. CICC Sangsu Jeong, Huiwon Yun, DongKwon Lee, Sunwoo Lee, Minyoung Kang, Dongsuk Jeon
2025	J	`jnl`	An Energy-Efficient 3D Semantic Segmentation Processor With Offset-Wise Weight Quantization. IEEE Trans. Circuits Syst. II Express Briefs Beomseok Kim, Sunwoo Lee, Byeungseok Yoo, Dongsuk Jeon
2025	J	`jnl`	CLAT: A Clustering-Based Attention Transformer Accelerator for Low-Latency Text Generation in LLMs. IEEE Trans. Circuits Syst. I Regul. Pap. Sunwoo Lee, Beomseok Kim, Jeongwoo Park, Dongsuk Jeon
2025	A*	`conf`	PaCA: Partial Connection Adaptation for Efficient Fine-Tuning. ICLR Sunghyeon Woo, Sol Namkung, Sunwoo Lee, Inho Jeong, Beomseok Kim, Dongsuk Jeon
2025	J	`jnl`	PaCA: Partial Connection Adaptation for Efficient Fine-Tuning. CoRR Sunghyeon Woo, Sol Namkung, Sunwoo Lee, Inho Jeong, Beomseok Kim, Dongsuk Jeon
2024	—	`conf`	A 5.6µW 10-Keyword End-to-End Keyword Spotting System Using Passive-Averaging SAR ADC and Sign-Exponent-Only Layer Fusion with 92.7% Accuracy. VLSI Technology and Circuits Sungjin Park, Kwanghyun Shin, DongKwon Lee, Minyoung Kang, Sunwoo Lee, Youngmin Park, Mingoo Seok, Dongsuk Jeon
2024	A*	`conf`	ALAM: Averaged Low-Precision Activation for Memory-Efficient Training of Transformer Models. ICLR Sunghyeon Woo, Sunwoo Lee, Dongsuk Jeon
2023	—	`conf`	A 4.27TFLOPS/W FP4/FP8 Hybrid-Precision Neural Network Training Processor Using Shift-Add MAC and Reconfigurable PE Array. ESSCIRC Sunwoo Lee, Jeongwoo Park, Dongsuk Jeon
2023	—	`conf`	A0.81 mm ISSCC Sungjin Park, Sunwoo Lee, Jeongwoo Park, Hyeong-Seok Choi, Dongsuk Jeon
2022	J	`jnl`	A Neural Network Training Processor With 8-Bit Shared Exponent Bias Floating Point and Multiple-Way Fused Multiply-Add Trees. IEEE J. Solid State Circuits Jeongwoo Park, Sunwoo Lee, Dongsuk Jeon
2022	—	`conf`	A low power neural network training processor with 8-bit floating point with a shared exponent bias and fused multiply add trees. AICAS Jeongwoo Park, Sunwoo Lee, Dongsuk Jeon
2022	A*	`conf`	Toward Efficient Low-Precision Training: Data Format Optimization and Hysteresis Quantization. ICLR Sunwoo Lee, Jeongwoo Park, Dongsuk Jeon
2021	—	`conf`	A 40nm 4.81TFLOPS/W 8b Floating-Point Training Processor for Non-Sparse Neural Networks Using Shared Exponent Bias and 24-Way Fused Multiply-Add Tree. ISSCC Jeongwoo Park, Sunwoo Lee, Dongsuk Jeon
2021	J	`jnl`	Dynamic Block-Wise Local Learning Algorithm for Efficient Neural Network Training. IEEE Trans. Very Large Scale Integr. Syst. Gwangho Lee, Sunwoo Lee, Dongsuk Jeon