Sunil R. Das - RankMe

77 papers A* 1B 1C 1Misc 9Journal 48Unranked 17

Year	Rank	Type	Title / Venue / Authors
2022	—	`conf`	Epileptic Seizure Detection Using Convolution Neural Networks. MeMeA William Sukaria, James Malasa, Shiu Kumar, Rahul Kumar, Mansour H. Assaf, Voicu Groza, Emil M. Petriu, Sunil R. Das
2021	—	`conf`	An Optimized Tongue Drive System for Disabled Persons. I2MTC Komal Chand, Kavilash Chand, Rahul Kumar, Bibhya Sharma, Mansour H. Assaf, Sunil R. Das, Voicu Groza, Emil M. Petriu, Satyendra N. Biswas
2019	J	`jnl`	Face Identification Based on Discrete Wavelet Transform and Neural Networks. Int. J. Image Graph. Samrat Pundalik Khadilkar, Sunil R. Das, Mansour H. Assaf, Satyendra N. Biswas
2018	J	`jnl`	Memristor-Based High-Speed Memory Cell With Stable Successive Read Operation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mohammad Nazmus Sakib, Rakibul Hassan, Satyendra N. Biswas, Sunil R. Das
2016	—	`conf`	A compact multispectral image capture unit for deployment on drones. I2MTC Ezekiel Bokolonga, Martin Hauhana, Nicholas Rollings, David Aitchison, Mansour H. Assaf, Sunil R. Das, Satyendra N. Biswas, Voicu Groza, Emil M. Petriu
2016	—	`conf`	An algorithm for generating prime implicants. I2MTC Sunil R. Das, Abdullah-Al Amin, Satyendra N. Biswas, Mansour H. Assaf, Emil M. Petriu, Voicu Groza
2016	—	`conf`	Short duration voice data speaker recognition system using novel fuzzy vector quantization algorithm. I2MTC Satyanand Singh, Mansour H. Assaf, Sunil R. Das, Satyendra N. Biswas, Emil M. Petriu, Voicu Groza
2015	—	`conf`	Designing elementary-tree space compressors using AND/NAND and XOR/XNOR combinations. I2MTC Nicholas A. Malan, Sunil R. Das, Satyendra N. Biswas, Mansour H. Assaf, Scott Morton, Emil M. Petriu, Voicu Groza
2015	—	`conf`	Image processing based system for classification of vehicles for parking purposes. I2MTC Amit Krishan Kumar, Mansour H. Assaf, Sunil R. Das, Satyendra N. Biswas, Emil M. Petriu, Voicu Groza
2014	—	`conf`	Design and implementation of high-performance master/slave memory controller with microcontroller bus architecture. I2MTC Shashisekhar Ramagundam, Sunil R. Das, Scott Morton, Satyendra N. Biswas, Voicu Groza, Mansour H. Assaf, Emil M. Petriu
2014	J	`jnl`	On System-on-Chip Testing Using Hybrid Test Vector Compression. IEEE Trans. Instrum. Meas. Satyendra N. Biswas, Sunil R. Das, Emil M. Petriu
2013	—	`conf`	Compressed video watermarking technique. I2MTC Satyendra N. Biswas, Touhidul Hasan, Shuvashis DasGupta, Sunil R. Das, Voicu Groza, Emil M. Petriu, Mansour H. Assaf
2013	—	`conf`	Data compression using mixed cascade of nonlinear logic. I2MTC Sunil R. Das, Danny L. Shaw, Satyendra N. Biswas, Mansour H. Assaf, Scott Morton, Irem Ozkarahan, Emil M. Petriu, Voicu Groza
2011	—	`conf`	Aliasing-Free Space Compaction in VLSI with Cascade of Two-Input OR/NOR Logic. DELTA Altaf Hossain, Voicu Groza, Sunil R. Das
2008	—	`conf`	A Novel Technique for Input Vector Compression in System-on-Chip Testing. ICIT Satyendra N. Biswas, Sunil R. Das, Mansour H. Assaf
2008	J	`jnl`	Aliasing-free compaction revisited. IET Circuits Devices Syst. Sunil R. Das, Altaf Hossain, Satyendra Biswas, Emil M. Petriu
2008	J	`jnl`	On a New Graph Theory Approach to Designing Zero-Aliasing Space Compressors for Built-In Self-Testing. IEEE Trans. Instrum. Meas. Sunil R. Das, Altaf Hossain, Satyendra Biswas, Emil M. Petriu, Mansour H. Assaf, Wen-Ben Jone, Mehmet Sahinoglu
2007	J	`jnl`	Testing Analog and Mixed-Signal Circuits With Built-In Hardware - A New Approach. IEEE Trans. Instrum. Meas. Sunil R. Das, Jila Zakizadeh, Satyendra Biswas, Mansour H. Assaf, Amiya Nayak, Emil M. Petriu, Wen-Ben Jone, Mehmet Sahinoglu
2006	J	`jnl`	Crosstalk test pattern generation for dynamic programmable logic arrays. IEEE Trans. Instrum. Meas. Jianxun Liu, Wen-Ben Jone, Sunil R. Das
2006	J	`jnl`	Guest Editorial Second Special Section of the IEEE Transactions on Instrumentation and Measurement in the Area of VLSI Testing - Future of Semiconductor Test. IEEE Trans. Instrum. Meas. Sunil R. Das, Rochit Rajsuman
2006	J	`jnl`	Space compactor design in VLSI circuits based on graph theoretic concepts. IEEE Trans. Instrum. Meas. Satyendra Biswas, Sunil R. Das, Emil M. Petriu
2005	J	`jnl`	A built-in self-testing method for embedded multiport memory arrays. IEEE Trans. Instrum. Meas. Vinod Narayanan, Swaroop Ghosh, Wen-Ben Jone, Sunil R. Das
2005	J	`jnl`	An adaptive compressed MPEG-2 video watermarking scheme. IEEE Trans. Instrum. Meas. Satyendra Biswas, Sunil R. Das, Emil M. Petriu
2005	J	`jnl`	Fault simulation and response compaction in full scan circuits using HOPE. IEEE Trans. Instrum. Meas. Sunil R. Das, Chittoor V. Ramamoorthy, Mansour H. Assaf, Emil M. Petriu, Wen-Ben Jone, Mehmet Sahinoglu
2005	J	`jnl`	Getting errors to catch themselves - self-testing of VLSI circuits with built-in hardware. IEEE Trans. Instrum. Meas. Sunil R. Das
2005	J	`jnl`	Guest Editorial First Special Section of the IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT in the Area of VLSI Testing - Future of Semiconductor Test. IEEE Trans. Instrum. Meas. Sunil R. Das, Rochit Rajsuman
2005	J	`jnl`	Measuring availability indexes with small samples for component and network reliability using the Sahinoglu-Libby probability model. IEEE Trans. Instrum. Meas. Mehmet Sahinoglu, David L. Libby, Sunil R. Das
2005	J	`jnl`	Revisiting response compaction in space for full-scan circuits with nonexhaustive test sets using concept of sequence characterization. IEEE Trans. Instrum. Meas. Sunil R. Das, Chittoor V. Ramamoorthy, Mansour H. Assaf, Emil M. Petriu, Wen-Ben Jone, Mehmet Sahinoglu
2004	J	`jnl`	A parallel built-in self-diagnostic method for nontraditional faults of embedded memory arrays. IEEE Trans. Instrum. Meas. Vikram Arora, Wen-Ben Jone, Der-Cheng Huang, Sunil R. Das
2004	J	`jnl`	Aliasing-Free Compaction in Testing Cores-Based System-on-Chip (SoC) using Compatibility of Response Data outputs. Trans. SDPS Sunil R. Das, Mansour H. Assaf, Emil M. Petriu, Mehmet Sahinoglu
2004	—	`conf`	Altera Max Plus II Development Environment in Fault Simulation and Test Implementation of Embedded Cores-Based Sequential Circuits. IWDC Sunil R. Das, Chuan Jin, Liwu Jin, Mansour H. Assaf, Emil M. Petriu, Mehmet Sahinoglu
2004	—	`conf`	Enhancing Testability in Architectural Design for the New Generation of Core-Based Embedded Systems. HASE Mansour H. Assaf, Sunil R. Das, Emil M. Petriu, Mehmet Sahinoglu
2004	C	`conf`	Implementation of Embedded Cores-Based Digital Devices in JBits Java Simulation Environment. CIT Mansour H. Assaf, Rami S. Abielmona, Payam Abolghasem, Sunil R. Das, Emil M. Petriu, Voicu Groza, Mehmet Sahinoglu
2004	J	`jnl`	Robotic tactile recognition of pseudorandom encoded objects. IEEE Trans. Instrum. Meas. Emil M. Petriu, Stephen K. S. Yeung, Sunil R. Das, Ana-Maria Cretu, Hans J. W. Spoelder
2003	J	`jnl`	An efficient BIST method for non-traditional faults of embedded memory arrays. IEEE Trans. Instrum. Meas. Wen-Ben Jone, Der-Cheng Huang, Sunil R. Das
2003	J	`jnl`	Guest editorial [Special section on innovations in VLSI automatic test equipment (ATEs)]. IEEE Trans. Instrum. Meas. Sunil R. Das, Rochit Rajsuman
2003	J	`jnl`	Instrumentation applications of multibit random-data representation. IEEE Trans. Instrum. Meas. Emil M. Petriu, Lichen Zhao, Sunil R. Das, Voicu Z. Groza, Aurel Cornell
2003	—	`conf`	JBits Implementation and Design Verification in Space Compressor Design of Digital Circuits. Modelling, Identification and Control Mansour H. Assaf, Rami S. Abielmona, Payam Abolghasem, Sunil R. Das, Emil M. Petriu, Voicu Groza
2003	J	`jnl`	Parity bit signature in response data compaction and built-in self-testing of VLSI circuits with nonexhaustive test sets. IEEE Trans. Instrum. Meas. Sunil R. Das, Made Sudarma, Mansour H. Assaf, Emil M. Petriu, Wen-Ben Jone, Krishnendu Chakrabarty, Mehmet Sahinoglu
2002	J	`jnl`	Data compression in space under generalized mergeability based on concepts of cover table and frequency ordering. IEEE Trans. Instrum. Meas. Sunil R. Das, Jing Yi Liang, Emil M. Petriu, Mansour H. Assaf, Wen-Ben Jone, Krishnendu Chakrabarty
2002	—	`conf`	Design of Aliasing Free Space Compressor in BIST with Maximal Compaction Ratio Using Concepts of Strong and Weak Compatibilities of Response Data Outputs and Generalized Sequence Mergeability. IWDC Sunil R. Das, Mansour H. Assaf, Emil M. Petriu, Sujoy Mukherjee
2001	Misc	`conf`	A Parallel Built-In Self-Diagnostic Method For Embedded Memory Buffers. VLSI Design Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das
2001	Misc	`conf`	An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers. VLSI Design Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das
2001	J	`jnl`	An adaptive path selection method for delay testing. IEEE Trans. Instrum. Meas. Wen-Ben Jone, Wu-Sung Yeh, Chingwei Yeh, Sunil R. Das
2001	J	`jnl`	Defect Level Estimation for Pseudorandom Testing Using Stochastic Analysis. VLSI Design Wen-Ben Jone, Der-Cheng Huang, Shih-Chieh Chang, Sunil R. Das
2001	J	`jnl`	Fault tolerance in systems design in VLSI using data compression under constraints of failure probabilities. IEEE Trans. Instrum. Meas. Sunil R. Das, Chittoor V. Ramamoorthy, Mansour H. Assaf, Emil M. Petriu, Wen-Ben Jone
2001	J	`jnl`	Guest Editorial. VLSI Design Sunil R. Das
2001	J	`jnl`	Random Pattern Testability Enhancement by Circuit Rewiring. VLSI Design Shih-Chieh Chang, Kwen-Yo Chen, Ching-Hsiang Cheng, Wen-Ben Jone, Sunil R. Das
2000	J	`jnl`	Space compression revisited. IEEE Trans. Instrum. Meas. Sunil R. Das, Tony F. Barakat, Emil M. Petriu, Mansour H. Assaf, Krishnendu Chakrabarty
2000	J	`jnl`	Test-set embedding based on width compression for mixed-mode BIST. IEEE Trans. Instrum. Meas. Krishnendu Chakrabarty, Sunil R. Das
1998	Misc	`conf`	A Stochastic Method for Defect Level Analysis of Pseudorandom Testing. VLSI Design Wen-Ben Jone, Sunil R. Das
1998	Misc	`conf`	Pseudorandom encoding for structured light applications. CATA Emil M. Petriu, Sunil R. Das, Niculaie Trif, Stephen S. K. Yeung
1998	J	`jnl`	Space compaction under generalized mergeability. IEEE Trans. Instrum. Meas. Sunil R. Das, Emil M. Petriu, Tony F. Barakat, Mansour H. Assaf, Amiya R. Nayak
1998	J	`jnl`	Syndrome Signature in Output Compaction for VLSI Built-in Self-Test. VLSI Design Sunil R. Das, Nita Goel, Wen-Ben Jone, Amiya R. Nayak
1997	Misc	`conf`	Delay Fault Coverage Enhancement Using Multiple Test Observation Times. VLSI Design Wen-Ben Jone, Yun-Pan Ho, Sunil R. Das
1997	J	`jnl`	Delay Fault Coverage Enhancement Using Variable Observation Times. J. Electron. Test. Wen-Ben Jone, Yun-Pan Ho, Sunil R. Das
1996	J	`jnl`	Guest Editorial. VLSI Design Sunil R. Das
1996	J	`jnl`	PGEN: A Novel Approach to Sequential Circuit Test Generation. VLSI Design Wen-Ben Jone, Nigam Shah, Anita Gleason, Sunil R. Das
1996	Misc	`conf`	Syndrome signature in output compaction for VLSI BIST. VLSI Design Sunil R. Das, Nishith Goel, Wen-Ben Jone, Amiya R. Nayak
1995	Misc	`conf`	An improved output compaction technique for built-in self-test in VLSI circuits. VLSI Design Sunil R. Das, H. T. Ho, Wen-Ben Jone, Amiya R. Nayak
1995	J	`jnl`	CACOP-a random pattern testability analyzer. IEEE Trans. Syst. Man Cybern. Wen-Ben Jone, Sunil R. Das
1995	J	`jnl`	On testing of sequential machines using circuit decomposition and stochastic modeling. IEEE Trans. Syst. Man Cybern. Sunil R. Das, Wen-Ben Jone, Amiya R. Nayak, Ian Choi
1994	B	`conf`	Designing General-Purpose Fault-Tolerant Distributed Systems - A Layered Approach. ICPADS Amiya R. Nayak, Wen-Ben Jone, Sunil R. Das
1994	Misc	`conf`	On Probabilistic Testing of Large-Scale Sequential Circuits Using Circuit Decomposition. VLSI Design Sunil R. Das, Wen-Ben Jone, Amiya Nayak, Ian Choi
1993	Misc	`conf`	CACOP - A Random Pattern Testability Analyzer. VLSI Design Wen-Ben Jone, Sunil R. Das
1993	J	`jnl`	Guest Editorial. VLSI Design Sunil R. Das
1992	J	`jnl`	On random testing for combinational circuits with a high measure of confidence. IEEE Trans. Syst. Man Cybern. Sunil R. Das, Wen-Ben Jone
1990	A*	`conf`	A survey on bit dimension optimization strategies of microprograms. MICRO Sunil R. Das, Amiya Nayak
1990	J	`jnl`	Multiple-output parity bit signature for exhaustive testing. J. Electron. Test. Wen-Ben Jone, Sunil R. Das
1990	J	`jnl`	Probabilistic modeling and fault analysis in sequential logic using computer simulation. IEEE Trans. Syst. Man Cybern. Sunil R. Das, Wen-Ben Jone, K. L. Wong
1987	J	`jnl`	Transition submatrices in regular homing experiments and identification of sequential machines of known class using direct-sum transition matrices. Comput. Oper. Res. Sunil R. Das, Ping Chao, Zen Chen, Yow Lung Dai, Mrinal K. Das
1986	J	`jnl`	An appraisal of the performance of the MMSC subgraph generation algorithm on a Cyber System 170/720. Computing Sunil R. Das, S. Y. Lee
1986	—	`conf`	On random testing of sequential digital logic with a high confidence measure (abstract). ACM Conference on Computer Science Sunil R. Das
1979	J	`jnl`	Transition matrices in the measurement and control of synchronous sequential machines. Inf. Sci. Sunil R. Das, C. L. Sheng, Zen Chen, W. J. Hsu
1978	J	`jnl`	Strong connectivity in symmetric graphs and generation of maximal minimally strongly connected subgraphs. Inf. Sci. Sunil R. Das, C. L. Sheng
1973	J	`jnl`	Multiform Partial Symmetry and Linearity. IEEE Trans. Computers N. S. Khabra, Sunil R. Das
1972	J	`jnl`	Clause-Column Table Approach for Generating All the Prime Implicants of Switching Functions. IEEE Trans. Computers Sunil R. Das, Narinder Singh Khabra