Sunil P. Khatri

210 papers A* 14A 28B 6C 48Misc 13Journal 48Unranked 53

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A Flash-Based Reconfigurable QCNN Inference Accelerator for Edge Applications. IEEE Trans. Computers Kyler R. Scott, Sunil P. Khatri
2026	Misc	`conf`	Flash-Based Dynamic Dot Product Acceleration. VLSID Kyler R. Scott, Sunil P. Khatri
2025	—	`conf`	A Novel Mixed-Signal Flash-based Finite Impulse Response (FFIR) Filter for IoT Applications. ASP-DAC Cheng-Yen Lee, Sunil P. Khatri, Ali Ghrayeb
2025	J	`jnl`	Attention-Enhanced AGRU Framework for Induction Motor Incipient Fault Diagnosis in Electric Vehicles. IEEE Trans. Instrum. Meas. Mohammad AlShaikh Saleh, Ali Ghrayeb, Shady S. Refaat, Haitham Abu-Rub, Sunil P. Khatri, Jörg Kammermann
2025	J	`jnl`	CapsPDNet: Optimized Capsule Network for Predicting Insulator Discharges Using UHF Signals. IEEE Trans. Instrum. Meas. Mohammad AlShaikh Saleh, Ahmad Darwish, Ali Ghrayeb, Shady S. Refaat, Haitham Abu-Rub, Sunil P. Khatri, Ayman H. El-Hag, Celal Fadil Kumru
2025	—	`conf`	Classification of Corrosion in Underground Power Cables Using CNNs and Microscopic Imaging. EUROCON Alamera Nouran Alquennah, Mohammad AlShaikh Saleh, Shady S. Refaat, Ali Ghrayeb, Haitham Abu-Rub, Marek Olesz, Mohammed Abdullah Al-Hajri, Sunil P. Khatri
2024	J	`jnl`	A Mixed-Signal Quantized Neural Network Accelerator Using Flash Transistors. IEEE Trans. Circuits Syst. I Regul. Pap. Kyler R. Scott, Cheng-Yen Lee, Sunil P. Khatri, Sarma B. K. Vrudhula
2024	J	`jnl`	An ASIC Accelerator for QNN With Variable Precision and Tunable Energy Efficiency. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ankit Wagle, Gian Singh, Sunil P. Khatri, Sarma B. K. Vrudhula
2024	C	`conf`	Self-Adaptive Physics Informed Neural Network for Paper Insulation Degree of Polymerization Prediction. IECON Alamera Nouran Alquennah, Mohammad AlShaikh Saleh, Ali Ghrayeb, Haitham Abu-Rub, Shady S. Refaat, Mohammed Abdullah Al-Hajri, Sunil P. Khatri
2023	J	`jnl`	A Digital Low Dropout (LDO) Voltage Regulator Using Pseudoflash Transistors. IEEE Trans. Very Large Scale Integr. Syst. Cheng-Yen Lee, Sunil P. Khatri
2023	—	`conf`	A Hardware Validation Framework for a Networked Dynamic Multi-factor Security Protocol. CommNet Cheng-Yen Lee, Kyler R. Scott, Sunil P. Khatri, Ali Ghrayeb
2023	—	`conf`	A Novel Pseudo-Flash Based Digital Low Dropout (LDO) Voltage Regulator. ISQED Cheng-Yen Lee, Sunil P. Khatri, Sarma B. K. Vrudhula
2023	C	`conf`	An Extremely Low-voltage Floating Gate Artificial Neuron. ISCAS Kyler R. Scott, Sunil P. Khatri
2023	A	`conf`	Scaled Population Division for Approximate Computing. ISLPED Kunal Bharathi, Sunil P. Khatri, Jiang Hu
2022	A	`conf`	A Flash-based Current-mode IC to Realize Quantized Neural Networks. DATE Kyler R. Scott, Cheng-Yen Lee, Sunil P. Khatri, Sarma B. K. Vrudhula
2022	C	`conf`	A Flash-based Digital to Analog Converter for Low Power Applications. ICCD Kyler R. Scott, Sunil P. Khatri
2022	J	`jnl`	A Novel ASIC Design Flow Using Weight-Tunable Binary Neurons as Standard Cells. IEEE Trans. Circuits Syst. I Regul. Pap. Ankit Wagle, Gian Singh, Sunil P. Khatri, Sarma B. K. Vrudhula
2022	J	`jnl`	A Novel ASIC Design Flow using Weight-Tunable Binary Neurons as Standard Cells. CoRR Ankit Wagle, Gian Singh, Sunil P. Khatri, Sarma B. K. Vrudhula
2022	B	`conf`	TD3lite: FPGA Acceleration of Reinforcement Learning with Structural and Representation Optimizations. FPL Chan-Wei Hu, Jiang Hu, Sunil P. Khatri
2021	J	`jnl`	A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard Cells. CoRR Ankit Wagle, Sunil P. Khatri, Sarma B. K. Vrudhula
2021	C	`conf`	CIDAN: Computing in DRAM with Artificial Neurons. ICCD Gian Singh, Ankit Wagle, Sarma B. K. Vrudhula, Sunil P. Khatri
2021	J	`jnl`	CIDAN: Computing in DRAM with Artificial Neurons. CoRR Gian Singh, Ankit Wagle, Sarma B. K. Vrudhula, Sunil P. Khatri
2021	J	`jnl`	Hardware Acceleration of Hash Operations in Modern Microprocessors. IEEE Trans. Computers Abbas A. Fairouz, Monther Abusultan, Viacheslav V. Fedorov, Sunil P. Khatri
2021	C	`conf`	NIST-Lite: Randomness Testing of RNGs on an Energy-Constrained Platform. ICCD Cheng-Yen Lee, Kunal Bharathi, Joellen Lansford, Sunil P. Khatri
2020	C	`conf`	A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard Cells. ICCD Ankit Wagle, Sunil P. Khatri, Sarma B. K. Vrudhula
2020	—	`conf`	A Mathematical Framework for Exploring Protein Folding Dynamics using Probabilistic Model Checking. ICICT Prasenjit Biswas, Sarit Pal, Sunil P. Khatri
2020	—	`conf`	A Statistical Methodology for Post-Fabrication Weight Tuning in a Binary Perceptron. ISQED Elham Azari, Ankit Wagle, Sunil P. Khatri, Sarma B. K. Vrudhula
2020	—	`conf`	Scaled Population Arithmetic for Efficient Stochastic Computing. ASP-DAC He Zhou, Sunil P. Khatri, Jiang Hu, Frank Liu
2020	C	`conf`	Scaled Population Subtraction for Approximate Computing. ICCD Kunal Bharathi, Jiang Hu, Sunil P. Khatri
2019	A*	`conf`	A Memory-Efficient Markov Decision Process Computation Framework Using BDD-based Sampling Representation. DAC He Zhou, Sunil P. Khatri, Jiang Hu, Frank Liu
2019	J	`jnl`	Fast, Ring-Based Design of 3-D Stacked DRAM. IEEE Trans. Very Large Scale Integr. Syst. Andrew J. Douglass, Sunil P. Khatri
2019	C	`conf`	Threshold Logic in a Flash. ICCD Ankit Wagle, Gian Singh, Jinghua Yang, Sunil P. Khatri, Sarma B. K. Vrudhula
2019	J	`jnl`	Threshold Logic in a Flash. CoRR Ankit Wagle, Gian Singh, Jinghua Yang, Sunil P. Khatri, Sarma B. K. Vrudhula
2018	J	`jnl`	A GPU-CPU heterogeneous algorithm for NGS read alignment. Int. J. Comput. Biol. Drug Des. Ahmad Al Kawam, Sunil P. Khatri, Aniruddha Datta
2018	—	`conf`	A Homomorphic Encryption Scheme Based on Affine Transforms. ACM Great Lakes Symposium on VLSI Kyle Loyka, He Zhou, Sunil P. Khatri
2018	C	`conf`	A Plain-Text Incremental Compression (PIC) Technique with Fast Lookup Ability. ICCD Kunal Bharathi, Harsh Kumar, Abbas A. Fairouz, Ahmad Al Kawam, Sunil P. Khatri
2018	J	`jnl`	Comparing Leakage Reduction Techniques for an Asynchronous Network-on-Chip Router. J. Low Power Electron. Abbas A. Fairouz, Monther Abusultan, Amr Elshennawy, Sunil P. Khatri
2018	C	`conf`	Synchronization of Ring-Based Resonant Standing Wave Oscillators for 3D Clocking Applications. ICCD Andrew J. Douglass, Sunil P. Khatri
2017	—	`conf`	A Robust C-element Design with Enhanced Metastability Performance. ACM Great Lakes Symposium on VLSI Kinshuk Sharma, Sunil P. Khatri
2017	J	`jnl`	A Survey of Software and Hardware Approaches to Performing Read Alignment in Next Generation Sequencing. IEEE ACM Trans. Comput. Biol. Bioinform. Ahmad Al Kawam, Sunil P. Khatri, Aniruddha Datta
2017	C	`conf`	An FPGA-Based Coprocessor for Hash Unit Acceleration. ICCD Abbas A. Fairouz, Sunil P. Khatri
2017	—	`conf`	Circuit Level Design of a Hardware Hash Unit for use in Modern Microprocessors. ACM Great Lakes Symposium on VLSI Abbas A. Fairouz, Monther Abusultan, Sunil P. Khatri
2017	—	`conf`	Design of a Flash-based Circuit for Multi-valued Logic. ACM Great Lakes Symposium on VLSI Monther Abusultan, Sunil P. Khatri
2017	—	`conf`	Fast and Highly Scalable Bayesian MDP on a GPU Platform. BCB He Zhou, Sunil P. Khatri, Jiang Hu, Frank Liu, Cliff C. N. Sze
2017	C	`conf`	Fast, Ring-Based Design of 3D Stacked DRAM. ICCD Andrew J. Douglass, Sunil P. Khatri
2016	C	`conf`	A GPU-based implementation of a sensor tasking methodology. FUSION Monther Abusultan, Suman Chakravorty, Sunil P. Khatri
2016	—	`conf`	A Ternary-Valued, Floating Gate Transistor-Based Circuit Design Approach. ISVLSI Monther Abusultan, Sunil P. Khatri
2016	A	`conf`	A flash-based digital circuit design flow. ICCAD Monther Abusultan, Sunil P. Khatri
2016	C	`conf`	A novel hardware hash unit design for modern microprocessors. ICCD Abbas A. Fairouz, Monther Abusultan, Sunil P. Khatri
2016	Misc	`conf`	A practical methodology to validate the statistical behavior of bloom filters. CODES+ISSS Venkateshwar Kottapalli, Sunil P. Khatri
2016	C	`conf`	Exploring static and dynamic flash-based FPGA design topologies. ICCD Monther Abusultan, Sunil P. Khatri
2016	J	`jnl`	FTCAM: An Area-Efficient Flash-Based Ternary CAM Design. IEEE Trans. Computers Viacheslav V. Fedorov, Monther Abusultan, Sunil P. Khatri
2016	—	`conf`	GPU acceleration for Bayesian control of Markovian genetic regulatory networks. BHI He Zhou, Jiang Hu, Sunil P. Khatri, Frank Liu, Cliff C. N. Sze, Mohammadmahdi R. Yousefi
2016	C	`conf`	Implementing low power digital circuits using flash devices. ICCD Monther Abusultan, Sunil P. Khatri
2016	J	`jnl`	Response to "Comment on 'Zero and negative energy dissipation at information-theoretic erasure'". CoRR Laszlo B. Kish, Claes-Goran Granqvist, Sunil P. Khatri, Ferdinand Peper
2015	—	`conf`	An Efficient Approach to Sample On-Chip Power Supplies. ACM Great Lakes Symposium on VLSI Luke Murray, Sunil P. Khatri
2015	—	`conf`	Delay, Power and Energy Tradeoffs in Deep Voltage-scaled FPGAs. ACM Great Lakes Symposium on VLSI Monther Abusultan, Sunil P. Khatri
2015	C	`conf`	Exploring the viability of stochastic computing. ICCD Joao Marcos de Aguiar, Sunil P. Khatri
2015	J	`jnl`	Zero and negative energy dissipation at information-theoretic erasure. CoRR Laszlo B. Kish, Claes-Göran Granqvist, Sunil P. Khatri, Ferdinand Peper
2014	—	`conf`	A comparison of FinFET based FPGA LUT designs. ACM Great Lakes Symposium on VLSI Monther Abusultan, Sunil P. Khatri
2014	C	`conf`	An area-efficient Ternary CAM design using floating gate transistors. ICCD Viacheslav V. Fedorov, Monther Abusultan, Sunil P. Khatri
2014	C	`conf`	An asynchronous Network-on-Chip router with low standby power. ICCD Amr Elshennawy, Sunil P. Khatri
2014	A	`conf`	FPGA LUT design for wide-band dynamic voltage and frequency scaled operation (abstract only). FPGA Monther Abusultan, Sunil P. Khatri
2014	Misc	`conf`	Look-up Table Design for Deep Sub-threshold through Full-Supply Operation. FCCM Monther Abusultan, Sunil P. Khatri
2014	Misc	`conf`	Techniques to Improve the Efficiency of SAT Based Path Delay Test Generation. VLSID Kun Bian, D. M. H. Walker, Sunil P. Khatri
2013	C	`conf`	A low-jitter phase-locked resonant clock generation and distribution scheme. ICCD Ayan Mandal, Kalyana C. Bollapalli, Nikhil Jayakumar, Sunil P. Khatri, Rabi N. Mahapatra
2013	—	`conf`	A source-synchronous Htree-based network-on-chip. ACM Great Lakes Symposium on VLSI Ayan Mandal, Sunil P. Khatri, Rabi N. Mahapatra
2013	—	`conf`	Architecture and 3D device simulation of a PIN diode-based Gamma radiation detector. ACM Great Lakes Symposium on VLSI Amr Elshennawy, Craig M. Marianno, Sunil P. Khatri
2013	A	`conf`	Crosstalk avoidance codes for 3D VLSI. DATE Rajeev Kumar, Sunil P. Khatri
2013	A	`conf`	Exploring topologies for source-synchronous ring-based network-on-chip. DATE Ayan Mandal, Sunil P. Khatri, Rabi N. Mahapatra
2013	—	`conf`	GPU implementation of a scalable non-linear congruential generator for cryptography applications. ACM Great Lakes Symposium on VLSI Aditya Belsare, Steve Liu, Sunil P. Khatri
2013	—	`conf`	Mixed structural-functional path delay test generation and compaction. DFTS Kun Bian, D. M. H. Walker, Sunil P. Khatri, Shayak Lahiri
2013	C	`conf`	Noise-based algorithms for functional equivalence and tautology checking. ICCD Pey-Chang Kent Lin, Sunil P. Khatri
2013	J	`jnl`	Using GPUs to Accelerate CAD Algorithms. IEEE Des. Test John F. Croix, Sunil P. Khatri, Kanupriya Gulati
2012	A	`conf`	A fast, source-synchronous ring-based network-on-chip design. DATE Ayan Mandal, Sunil P. Khatri, Rabi N. Mahapatra
2012	—	`conf`	Alleviating NBTI-induced failure in off-chip output drivers. ACM Great Lakes Symposium on VLSI Bhavitavya Bhadviya, Ayan Mandal, Sunil P. Khatri
2012	C	`conf`	An efficient arithmetic Sum-of-Product (SOP) based multiplication approach for FIR filters and DFT. ICCD Rajeev Kumar, Ayan Mandal, Sunil P. Khatri
2012	A*	`conf`	Application of logic synthesis to the understanding and cure of genetic diseases. DAC Pey-Chang Kent Lin, Sunil P. Khatri
2012	C	`conf`	Architectural simulations of a fast, source-synchronous ring-based Network-on-Chip design. ICCD Ayan Mandal, Sunil P. Khatri, Rabi N. Mahapatra
2012	A*	`conf`	Boolean satisfiability using noise based logic. DAC Pey-Chang Kent Lin, Ayan Mandal, Sunil P. Khatri
2012	—	`conf`	Determining gene function in boolean networks using boolean satisfiability. GENSiPS Pey-Chang Kent Lin, Sunil P. Khatri
2012	J	`jnl`	On Optimal and Achievable Fix-Free Codes. IEEE Trans. Inf. Theory Serap A. Savari, S. M. Hossein Tabatabaei Yazdi, Navid Abedini, Sunil P. Khatri
2012	C	`conf`	Timing aware partitioning for multi-FPGA based logic simulation using top-down selective hierarchy flattening. ICCD Subramanian Poothamkurissi Swaminathan, Pey-Chang Kent Lin, Sunil P. Khatri
2011	J	`jnl`	A DCVSL Delay Cell for Fast Low Power Frequency Synthesis Applications. IEEE Trans. Circuits Syst. I Regul. Pap. Didem Zeliha Turker, Sunil P. Khatri, Edgar Sánchez-Sinencio
2011	C	`conf`	A novel cryptographic key exchange scheme using resistors. ICCD Pey-Chang Kent Lin, Alex Ivanov, Bradley Johnson, Sunil P. Khatri
2011	Misc	`conf`	An Automated Approach for Minimum Jitter Buffered H-Tree Construction. VLSI Design Ayan Mandal, Nikhil Jayakumar, Kalyana C. Bollapalli, Sunil P. Khatri, Rabi N. Mahapatra
2011	J	`jnl`	Boolean Satisfiability using Noise Based Logic CoRR Pey-Chang Kent Lin, Ayan Mandal, Sunil P. Khatri
2011	—	`conf`	Efficient cancer therapy using Boolean networks and Max-SAT-based ATPG. GENSiPS Pey-Chang Kent Lin, Sunil P. Khatri
2011	Misc	`conf`	Interconnected Tile Standing Wave Resonant Oscillator Based Clock Distribution Circuits. VLSI Design Ayan Mandal, Vinay Karkala, Sunil P. Khatri, Rabi N. Mahapatra
2011	J	`jnl`	Noise-based Deterministic Logic and Computing: a Brief Survey. Int. J. Unconv. Comput. Laszlo B. Kish, Sunil P. Khatri, Sergey M. Bezrukov, Ferdinand Peper, Zoltan Gingl, Tamás Horváth
2011	J	`jnl`	Noise-based information processing: Noise-based logic and computing: what do we have so far? CoRR Laszlo B. Kish, Sunil P. Khatri, Sergey M. Bezrukov, Ferdinand Peper, Zoltan Gingl, Tamás Horváth
2010	B	`conf`	A SAT-Based Scheme to Determine Optimal Fix-Free Codes. DCC Navid Abedini, Sunil P. Khatri, Serap A. Savari
2010	J	`jnl`	A Simultaneous Input Vector Control and Circuit Modification Technique to Reduce Leakage with Zero Delay Penalty. ACM Trans. Design Autom. Electr. Syst. Nikhil Jayakumar, Sunil P. Khatri
2010	C	`conf`	An efficient pulse flip-flop based launch-on-shift scan cell. ISCAS Rajesh Kumar, Sunil P. Khatri
2010	—	`conf`	Boolean satisfiability on a graphics processor. ACM Great Lakes Symposium on VLSI Kanupriya Gulati, Sunil P. Khatri
2010	J	`jnl`	Computation using Noise-based Logic: Efficient String Verification over a Slow Communication Channel CoRR Laszlo B. Kish, Sunil P. Khatri, Tamás Horváth
2010	A	`conf`	Efficient arithmetic sum-of-product (SOP) based Multiple Constant Multiplication (MCM) for FFT. ICCAD Vinay Karkala, Joseph Wanstrath, Travis Lacour, Sunil P. Khatri
2010	J	`jnl`	Fault Table Computation on GPUs. J. Electron. Test. Kanupriya Gulati, Sunil P. Khatri
2010	A	`conf`	Implementing digital logic with sinusoidal supplies. DATE Kalyana C. Bollapalli, Sunil P. Khatri, Laszlo B. Kish
2010	—	`conf`	Inference of gene predictor set using Boolean satisfiability. GENSiPS Pey-Chang Kent Lin, Sunil P. Khatri
2010	J	`jnl`	Instantaneous noise-based logic CoRR Laszlo B. Kish, Sunil P. Khatri, Ferdinand Peper
2010	J	`jnl`	Noise-based deterministic logic and computing: a brief survey CoRR Laszlo B. Kish, Sunil P. Khatri, Sergey M. Bezrukov, Ferdinand Peper, Zoltan Gingl, Tamás Horváth
2010	J	`jnl`	Towards brain-inspired computing CoRR Zoltan Gingl, Sunil P. Khatri, Laszlo B. Kish
2010	—	`conf`	VLSI implementation of a non-linear feedback shift register for high-speed cryptography applications. ACM Great Lakes Symposium on VLSI Pey-Chang Kent Lin, Sunil P. Khatri
2009	C	`conf`	3D simulation and analysis of the radiation tolerance of voltage scaled digital circuit. ICCD Rajesh Garg, Sunil P. Khatri
2009	J	`jnl`	A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations. IEEE Trans. Very Large Scale Integr. Syst. Suganth Paul, Nikhil Jayakumar, Sunil P. Khatri
2009	C	`conf`	A PLL design based on a standing wave resonant oscillator. ICCD Vinay Karkala, Kalyana C. Bollapalli, Rajesh Garg, Sunil P. Khatri
2009	C	`conf`	A radiation tolerant Phase Locked Loop design for digital electronics. ICCD Rajesh Kumar, Vinay Karkala, Rajesh Garg, Tanuj Jindal, Sunil P. Khatri
2009	C	`conf`	A robust pulsed flip-flop and its use in enhanced scan design. ICCD Rajesh Kumar, Kalyana C. Bollapalli, Rajesh Garg, Tarun Soni, Sunil P. Khatri
2009	—	`conf`	Accelerating statistical static timing analysis using graphics processing units. ASP-DAC Kanupriya Gulati, Sunil P. Khatri
2009	J	`jnl`	Circuit-Level Design Approaches for Radiation-Hard Digital Electronics. IEEE Trans. Very Large Scale Integr. Syst. Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri, Gwan S. Choi
2009	A	`conf`	Closed-loop modeling of power and temperature profiles of FPGAs. FPGA Kanupriya Gulati, Sunil P. Khatri, Peng Li
2009	—	`conf`	Design and implementation of a sub-threshold BFSK transmitter. ISQED Suganth Paul, Rajesh Garg, Sunil P. Khatri, Sheila Vaidya
2009	J	`jnl`	Efficient On-Chip Crosstalk Avoidance CODEC Design. IEEE Trans. Very Large Scale Integr. Syst. Chunjie Duan, Victor H. Cordero Calle, Sunil P. Khatri
2009	—	`conf`	Efficient analytical determination of the SEU-induced pulse shape. ASP-DAC Rajesh Garg, Sunil P. Khatri
2009	J	`jnl`	Encoding Serial Graphical Data for Energy-Delay Product/Energy Minimization. J. Low Power Electron. Sasidharan Ekambavanan, Rajesh Garg, Sunil P. Khatri, Krishna R. Narayanan
2009	J	`jnl`	FPGA-based hardware acceleration for Boolean satisfiability. ACM Trans. Design Autom. Electr. Syst. Kanupriya Gulati, Suganth Paul, Sunil P. Khatri, Srinivas Patil, Abhijit Jas
2009	—	`conf`	Fast circuit simulation on graphics processing units. ASP-DAC Kanupriya Gulati, John F. Croix, Sunil P. Khatri, Rahm Shastry
2009	—	`conf`	Fault table generation using Graphics Processing Units. HLDVT Kanupriya Gulati, Sunil P. Khatri
2009	—	`conf`	Highly parallel decoding of space-time codes on graphics processing units. Allerton Kalyana C. Bollapalli, Yiyue Wu, Kanupriya Gulati, Sunil P. Khatri, A. Robert Calderbank
2009	A	`conf`	Introduction to GPU programming for EDA. ICCAD John F. Croix, Sunil P. Khatri
2009	—	`conf`	Low power and high performance sram design using bank-based selective forward body bias. ACM Great Lakes Symposium on VLSI Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri
2009	—	`conf`	Noise-Based Logic and Computing: From Boolean Logic Gates to Brain Circuitry and Its Possible Hardware Realization. IWNC Laszlo B. Kish, Sergey M. Bezrukov, Sunil P. Khatri, Zoltan Gingl, S. Sethuraman
2009	C	`conf`	On-chip bidirectional wiring for heavily pipelined systems using network coding. ICCD Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri
2009	—	`conf`	Robust window-based multi-node technology-independent logic minimization. ACM Great Lakes Symposium on VLSI Jeff L. Cobb, Kanupriya Gulati, Sunil P. Khatri
2009	—	`conf`	SEU hardened clock regeneration circuits. ISQED Rajballav Dash, Rajesh Garg, Sunil P. Khatri, Gwan S. Choi
2009	J	`jnl`	Selective Forward Body Bias for High Speed and Low Power SRAMs. J. Low Power Electron. Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri
2009	C	`conf`	Sorting Binary Numbers in Hardware - A Novel Algorithm and its Implementation. ISCAS Srikanth Alaparthi, Kanupriya Gulati, Sunil P. Khatri
2008	A	`conf`	A Delay-efficient Radiation-hard Digital Design Approach Using CWSP Elements. DATE Charu Nagpal, Rajesh Garg, Sunil P. Khatri
2008	Misc	`conf`	A Merged Synthesis Technique for Fast Arithmetic Blocks Involving Sum-of-Products and Shifters. VLSI Design Sabyasachi Das, Sunil P. Khatri
2008	J	`jnl`	A Novel Hybrid Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic. IEEE Trans. Very Large Scale Integr. Syst. Sabyasachi Das, Sunil P. Khatri
2008	A	`conf`	A Single-supply True Voltage Level Shifter. DATE Rajesh Garg, Gagandeep Mallarapu, Sunil P. Khatri
2008	J	`jnl`	A Timing-Driven Approach to Synthesize Fast Barrel Shifters. IEEE Trans. Circuits Syst. II Express Briefs Sabyasachi Das, Sunil P. Khatri
2008	Misc	`conf`	A Timing-Driven Synthesis Technique for Arithmetic Product-of-Sum Expressions. VLSI Design Sabyasachi Das, Sunil P. Khatri
2008	A*	`conf`	A fast, analytical estimator for the SEU-induced pulse width in combinational designs. DAC Rajesh Garg, Charu Nagpal, Sunil P. Khatri
2008	—	`conf`	A lithography-friendly structured ASIC design approach. ACM Great Lakes Symposium on VLSI Salman Gopalani, Rajesh Garg, Sunil P. Khatri, Mosong Cheng
2008	C	`conf`	A novel, highly SEU tolerant digital circuit design approach. ICCD Rajesh Garg, Sunil P. Khatri
2008	J	`jnl`	A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations. Integr. Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri, D. M. H. Walker
2008	—	`conf`	A robust, fast pulsed flip-flop design. ACM Great Lakes Symposium on VLSI Arunprasad Venkatraman, Rajesh Garg, Sunil P. Khatri
2008	Misc	`conf`	An Inversion-Based Synthesis Approach for Area and Power Efficient Arithmetic Sum-of-Products. VLSI Design Sabyasachi Das, Sunil P. Khatri
2008	A	`conf`	Clock Distribution Scheme using Coplanar Transmission Lines. DATE Victor H. Cordero Calle, Sunil P. Khatri
2008	J	`jnl`	Dynamically De-Skewable Clock Distribution Methodology. IEEE Trans. Very Large Scale Integr. Syst. Arjun Kapoor, Nikhil Jayakumar, Sunil P. Khatri
2008	J	`jnl`	Efficient, scalable hardware engine for Boolean satisfiability and unsatisfiable core extraction. IET Comput. Digit. Tech. Kanupriya Gulati, Mandar Waghmode, Sunil P. Khatri, Weiping Shi
2008	A	`conf`	Energy Efficient and High Speed On-Chip Ternary Bus. DATE Chunjie Duan, Sunil P. Khatri
2008	A*	`conf`	Forbidden transition free crosstalk avoidance CODEC design. DAC Chunjie Duan, Chengyu Zhu, Sunil P. Khatri
2008	—	`conf`	Improving FPGA routability using network coding. ACM Great Lakes Symposium on VLSI Kanupriya Gulati, Sunil P. Khatri
2008	C	`conf`	Modeling dynamic stability of SRAMS in the presence of single event upsets (SEUs). ISCAS Rajesh Garg, Peng Li, Sunil P. Khatri
2008	—	`conf`	Pipelined network of PLA based circuit design. ACM Great Lakes Symposium on VLSI Suganth Paul, Rajesh Garg, Sunil P. Khatri
2008	J	`jnl`	Resource sharing among mutually exclusive sum-of-product blocks for area reduction. ACM Trans. Design Autom. Electr. Syst. Sabyasachi Das, Sunil P. Khatri
2008	J	`jnl`	SAT-based ATPG using multilevel compatible don't-cares. ACM Trans. Design Autom. Electr. Syst. Nikhil Saluja, Kanupriya Gulati, Sunil P. Khatri
2008	A*	`conf`	Towards acceleration of fault simulation using graphics processing units. DAC Kanupriya Gulati, Sunil P. Khatri
2007	J	`jnl`	A Predictably Low-Leakage ASIC Design Style. IEEE Trans. Very Large Scale Integr. Syst. Nikhil Jayakumar, Sunil P. Khatri
2007	C	`conf`	A Structured ASIC Design Approach Using Pass Transistor Logic. ISCAS Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri
2007	—	`conf`	A methodology for interconnect dimension determination. ISPD Jeff L. Cobb, Rajesh Garg, Sunil P. Khatri
2007	A	`conf`	An algorithm to minimize leakage through simultaneous input vector control and circuit modification. DATE Nikhil Jayakumar, Sunil P. Khatri
2007	J	`jnl`	High-throughput VLSI Implementations of Iterative Decoders and Related Code Construction Problems. J. VLSI Signal Process. Vijay Nagarajan, Stefan Laendner, Nikhil Jayakumar, Olgica Milenkovic, Sunil P. Khatri
2007	C	`conf`	Toggle Equivalence Preserving (TEP) Logic Optimization. DSD Eugene Goldberg, Kanupriya Gulati, Sunil P. Khatri
2006	—	`conf`	A High-Speed Fully-Programmable VLSI Decoder for Regular LDPC Codes. ICASSP (3) Euncheol Kim, Nikhil Jayakumar, Pankaj Bhagawat, Anand Selvarathinam, Gwan Choi, Sunil P. Khatri
2006	A*	`conf`	A PLA based asynchronous micropipelining approach for subthreshold circuit design. DAC Nikhil Jayakumar, Rajesh Garg, Bruce Gamache, Sunil P. Khatri
2006	A*	`conf`	A design approach for radiation-hard digital electronics. DAC Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri, Gwan Choi
2006	—	`conf`	A design flow to optimize circuit delay by using standard cells and PLAs. ACM Great Lakes Symposium on VLSI Rajesh Garg, Mario Sánchez, Kanupriya Gulati, Nikhil Jayakumar, Anshul Gupta, Sunil P. Khatri
2006	C	`conf`	A probabilistic method to determine the minimum leakage vector for combinational designs. ISCAS Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri
2006	C	`conf`	An Efficient, Scalable Hardware Engine for Boolean SATisfiability. ICCD Mandar Waghmode, Kanupriya Gulati, Sunil P. Khatri, Weiping Shi
2006	A	`conf`	Bus stuttering: an encoding technique to reduce inductive noise in off-chip data transmission. DATE Brock J. LaMeres, Sunil P. Khatri
2006	C	`conf`	CMOS Comparators for High-Speed and Low-Power Applications. ICCD Eric Menendez, Dumezie Maduike, Rajesh Garg, Sunil P. Khatri
2006	C	`conf`	Computing during supply voltage switching in DVS enabled real-time processors. ISCAS Chunjie Duan, Sunil P. Khatri
2006	—	`conf`	Controlling inductive cross-talk and power in off-chip buses using CODECs. ASP-DAC Brock J. LaMeres, Kanupriya Gulati, Sunil P. Khatri
2006	C	`conf`	Efficient don't care computation for hierarchical designs. ISCAS Kanupriya Gulati, M. Lovell, Sunil P. Khatri
2006	C	`conf`	Generalized buffering of PTL logic stages using Boolean division. ISCAS Rajesh Garg, Sunil P. Khatri
2006	—	`conf`	Implementation of MOSFET based capacitors for digital applications. ACM Great Lakes Symposium on VLSI Bo Shen, Sunil P. Khatri, Takis Zourntos
2006	C	`conf`	Memory-based crosstalk canceling CODECs for on-chip buses. ISCAS Chunjie Duan, Kanupriya Gulati, Sunil P. Khatri
2006	A	`conf`	Network coding for routability improvement in VLSI. ICCAD Nikhil Jayakumar, Sunil P. Khatri, Kanupriya Gulati, Alexander Sprintson
2006	C	`conf`	On the Improvement of Statistical Static Timing Analysis. ICCD Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri
2006	—	`conf`	Resource and delay efficient matrix multiplication using newer FPGA devices. ACM Great Lakes Symposium on VLSI Scott J. Campbell, Sunil P. Khatri
2005	—	`conf`	A Boolean satisfiability based solution to the routing and wavelength assignment problem in optical telecommunication networks. ICC John Valavi, Nikhil Saluja, Sunil P. Khatri
2005	—	`conf`	A dynamic voltage scaling algorithm for energy reduction in hard real-time systems. ASP-DAC Van R. Culver, Sunil P. Khatri
2005	A*	`conf`	A self-adjusting scheme to determine the optimum RBB by monitoring leakage currents. DAC Nikhil Jayakumar, Sandeep Dhar, Sunil P. Khatri
2005	A*	`conf`	A variation tolerant subthreshold design approach. DAC Nikhil Jayakumar, Sunil P. Khatri
2005	A	`conf`	An algebraic decision diagram (ADD) based technique to find leakage histograms of combinational designs. ISLPED Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri
2005	C	`conf`	Broadband Impedance Matching for Inductive Interconnect in VLSI Packages. ICCD Brock J. LaMeres, Sunil P. Khatri
2005	A	`conf`	Efficient SAT-based combinational ATPG using multi-level don't-cares. ITC Nikhil Saluja, Sunil P. Khatri
2005	A	`conf`	Encoding-Based Minimization of Inductive Cross-Talk for Off-Chip Data Transmission. DATE Brock J. LaMeres, Sunil P. Khatri
2005	C	`conf`	Minimum Energy Near-threshold Network of PLA based Design. ICCD Nikhil Jayakumar, Sunil P. Khatri
2005	Misc	`conf`	Non-Manhattan Routing Using a Manhattan Router. VLSI Design Edward Hursey, Nikhil Jayakumar, Sunil P. Khatri
2005	—	`conf`	Performance model for inter-chip communication considering inductive cross-talk and cost. ISCAS (4) Brock J. LaMeres, Sunil P. Khatri
2005	A	`conf`	Practical techniques to reduce skew and its variations in buffered clock networks. ICCAD Ganesh Venkataraman, Nikhil Jayakumar, Jiang Hu, Peng Li, Sunil P. Khatri, Anand Rajaram, Patrick McGuinness, Charles J. Alpert
2005	C	`conf`	X-Routing using Two Manhattan Route Instances. ICCD Seraj Ahmad, Nikhil Jayakumar, Vijay Balasubramanian, Edward Hursey, Sunil P. Khatri, Rabi N. Mahapatra
2004	A	`conf`	A metal and via maskset programmable VLSI design methodology using PLAs. ICCAD Nikhil Jayakumar, Sunil P. Khatri
2004	A	`conf`	A novel clock distribution and dynamic de-skewing methodology. ICCAD Arjun Kapoor, Nikhil Jayakumar, Sunil P. Khatri
2004	A*	`conf`	A robust algorithm for approximate compatible observability don't care (CODC) computation. DAC Nikhil Saluja, Sunil P. Khatri
2004	A	`conf`	Exploiting Crosstalk to Speed up On-Chip Buse. DATE Chunjie Duan, Sunil P. Khatri
2004	B	`conf`	High-throughput VLSI implementations of iterative decoders and related code construction problems. GLOBECOM Vijay Nagarajan, Nikhil Jayakumar, Sunil P. Khatri, Olgica Milenkovic
2004	J	`jnl`	SPFD-based wire removal in standard-cell and network-of-PLA circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sunil P. Khatri, Subarnarekha Sinha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
2003	B	`conf`	A fast ternary CAM design for IP networking applications. ICCCN Bruce Gamache, Zachary Pfeffer, Sunil P. Khatri
2003	A	`conf`	An ASIC design methodology with predictably low leakage, using leakage-immune standard cells. ISLPED Nikhil Jayakumar, Sunil P. Khatri
2003	—	`conf`	IP routing table compression using ESPRESSO-MV. ICON Jianjian Bian, Sunil P. Khatri
2002	J	`jnl`	An efficient and regular routing methodology for datapath designsusing net regularity extraction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sabyasachi Das, Sunil P. Khatri
2001	—	`conf`	A regularity-driven fast gridless detailed router for high frequency datapath designs. ISPD Sabyasachi Das, Sunil P. Khatri
2001	A	`conf`	Addressing the Timing Closure Problem by Integrating Logic Optimization and Placement. ICCAD Wilsin Gosti, Sunil P. Khatri, Alberto L. Sangiovanni-Vincentelli
2001	—	`conf`	Analysis and avoidance of cross-talk in on-chip buses. Hot Interconnects Chunjie Duan, Anup Tirumala, Sunil P. Khatri
2000	C	`conf`	Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks. ICCD Subarnarekha Sinha, Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
2000	A	`conf`	Cross-Talk Immune VLSI Design Using a Network of PLAs Embedded in a Regular Layout Fabric. ICCAD Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1999	A*	`conf`	A Novel VLSI Layout Fabric for Deep Sub-Micron Applications. DAC Sunil P. Khatri, Amit Mehrotra, Robert K. Brayton, Ralph H. J. M. Otten, Alberto L. Sangiovanni-Vincentelli
1999	Misc	`conf`	Multi-Valued Logic Synthesis. VLSI Design Robert K. Brayton, Sunil P. Khatri
1999	Misc	`conf`	Sequential Multi-Valued Network Simplification using Redundancy Removal. VLSI Design Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1996	Misc	`conf`	A study of composition schemes for mixed apply/compose based construction of ROBDDs. VLSI Design Amit Narayan, Sunil P. Khatri, Jawahar Jain, Masahiro Fujita, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1996	B	`conf`	Decomposition Techniques for Efficient ROBDD Construction. FMCAD Jawahar Jain, Amit Narayan, C. Coelho, Sunil P. Khatri, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton, Masahiro Fujita
1996	A*	`conf`	Engineering Change in a Non-Deterministic FSM Setting. DAC Sunil P. Khatri, Amit Narayan, Sriram C. Krishnan, Kenneth L. McMillan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1996	B	`conf`	VIS. FMCAD Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa
1996	A*	`conf`	VIS: A System for Verification and Synthesis. CAV Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa