Sunghye Park

11 papers A* 3A 3Journal 2Unranked 3
YearRankTypeTitle / Venue / Authors
2025 A conf
Neural Circuit Parameter Prediction for Efficient Quantum Data Loading.
DATE
Dohun Kim, Sunghye Park, Seokhyeong Kang
2024 A* conf
HiLight: A Comprehensive Framework for High-Performance and Lightweight Scalability in Surface Code Communication.
DAC
Sunghye Park, Dohun Kim, Seokhyeong Kang
2024 A* conf
Hybrid Circuit Mapping: Leveraging the Full Spectrum of Computational Capabilities of Neutral Atom Quantum Computers.
DAC
Ludwig Schmid, Sunghye Park, Robert Wille
2024 — conf
QNSA: Quantum Neural Simulated Annealing for Combinatorial Optimization.
ISQED
Seongbin Kwon, Dohun Kim, Sunghye Park, Seojeong Kim, Seokhyeong Kang
2023 A conf
ClusterNet: Routing Congestion Prediction and Optimization Using Netlist Clustering and Graph Neural Networks.
ICCAD
Kyungjun Min, Seongbin Kwon, Sung-Yun Lee, Dohun Kim, Sunghye Park, Seokhyeong Kang
2023 J jnl
Hybrid Circuit Mapping: Leveraging the Full Spectrum of Computational Capabilities of Neutral Atom Quantum Computers.
CoRR
Ludwig Schmid, Sunghye Park, Seokhyeong Kang, Robert Wille
2022 A* conf
A fast and scalable qubit-mapping method for noisy intermediate-scale quantum computers.
DAC
Sunghye Park, Daeyeon Kim, Minhyuk Kweon, Jae-Yoon Sim, Seokhyeong Kang
2022 A conf
MCQA: Multi-Constraint Qubit Allocation for Near-FTQC Device.
ICCAD
Sunghye Park, Dohun Kim, Jae-Yoon Sim, Seokhyeong Kang
2020 J jnl
A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sunmean Kim, Sung-Yun Lee, Sunghye Park, Kyung Rok Kim, Seokhyeong Kang
2019 — conf
Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic.
ISMVL
Sunmean Kim, Sung-Yun Lee, Sunghye Park, Seokhyeong Kang
2019 — conf
Multi-Threshold Voltages Graphene Barristor-Based Ternary ALU.
ISOCC
Sunghye Park, Sunmean Kim, Seokhyeong Kang