Sungho Kang

244 papers A* 1A 4C 6Misc 2Journal 150Unranked 81
YearRankTypeTitle / Venue / Authors
2026 J jnl
A Dual-Mode Online BISR Architecture for Interconnect and Memory Repair in Chiplet-Based Systems.
IEEE Trans. Reliab.
Donghyun Han, Sooryeong Lee, Jongho Park, Dayoung Kim, Seungtae Kim, Youngkwang Lee, Sungho Kang
2026 J jnl
A Low Area Built-In Self-Repair Using Hybrid Fault Address Memory for HBM.
IEEE Trans. Very Large Scale Integr. Syst.
Byungsoo Kim, Seung Ho Shin, Youngki Moon, Eugene Jeong, Sungho Kang
2026 J jnl
CLAPS: A Graph Clustering-Based Approach for Partial Scan Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jaeyoung Joung, Sangjun Lee, Jongho Park, Jaehyun Kim, Laesang Jung, Sungho Kang
2026 J jnl
FADE: Fault-Aware Adaptive On-Die ECC for Improving Robustness.
IEEE Trans. Very Large Scale Integr. Syst.
Youngki Moon, Juyong Lee, Nayeun Kim, Yeonho Choi, Byungsoo Kim, Sungho Kang
2026 J jnl
STAR-PIM: Self-Test and Repair Structure for Processing-in-Memory With Adder Tree-Based MAC.
IEEE Trans. Circuits Syst. I Regul. Pap.
Seung Ho Shin, Younwoo Yoo, Youngki Moon, Nuri Son, Dahoon Kim, Sungho Kang
2026 J jnl
TOPS: Topology-Based Partial Scan for Stuck-At and Delay Testing.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sangjun Lee, Jongho Park, Jaeyoung Joung, Jaehyun Kim, Laesang Jung, Sungho Kang
2026 J jnl
Test Cycle Reduction for TSV Test Using Streaming Scan Network on 3-D IC.
IEEE Trans. Very Large Scale Integr. Syst.
Sunghoon Kim, Donghyun Han, Dayoung Kim, Sungho Kang
2026 J jnl
VASE: Vector Memory Using Bit-Level Address Segmentation for High-Speed Memory Testing.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sooryeong Lee, Juyong Lee, Hayoung Lee, Sungho Kang
2025 J jnl
A Built-In Self-Repair With Maximum Fault Collection and Fast Analysis Method for HBM.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Joonsik Yoon, Hayoung Lee, Youngki Moon, Seung Ho Shin, Sungho Kang
2025 J jnl
A Cost-Effective Per-Pin ALPG for High-Speed Memory Testing.
IEEE Trans. Very Large Scale Integr. Syst.
Juyong Lee, Hayoung Lee, Sooryeong Lee, Sungho Kang
2025 J jnl
A New Logic BIST for Complete Fault Detection Using Previous Scan-In Bit Dependency.
IEEE Access
Jongho Park, Sangjun Lee, Jaehyun Kim, Hanseong Cho, Nayeun Kim, Sungho Kang
2025 J jnl
A New Pipelined Output Data Reducer of BOST for Improved Parallelism.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sooryeong Lee, Hayoung Lee, Juyong Lee, Sungho Kang
2025 J jnl
A New Test Point Insertion Using Weight Adjusted Grouping.
IEEE Access
Jaehyun Kim, Hyemin Kim, Jongho Park, Sangjun Lee, Sungho Kang
2025 J jnl
A Novel CNN-Based Redundancy Analysis Using Parallel Solution Decision.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Seung Ho Shin, Minho Cheong, Hayoung Lee, Byungsoo Kim, Sungho Kang
2025 J jnl
A Novel Prediction-Based Two-Tiered ECC for Mitigating SWD Errors in HBM.
IEEE Trans. Very Large Scale Integr. Syst.
Youngki Moon, Seung Ho Shin, Seokjun Jang, Duyeon Won, Sungho Kang
2025 J jnl
A Robust Test Architecture for Low-Power AI Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hayoung Lee, Juyong Lee, Sungho Kang
2025 J jnl
An Efficient Low-Power BIST for Automotive SoC With Periodic Pattern Type Selection.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jongho Park, Sangjun Lee, Hyemin Kim, Jaeyoung Joung, Jaehyun Kim, Sungho Kang
2025 J jnl
An Efficient Test Architecture Using Hybrid Built-In Self-Test for Processing-in-Memory.
IEEE Trans. Very Large Scale Integr. Syst.
Hayoung Lee, Juyong Lee, Sungho Kang
2025 J jnl
An Efficient Test Scheduling Method Based on Dynamic Pairing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Heetae Kim, Hyojoon Yun, Doohyun Yoon, Sungho Kang
2025 J jnl
Effective Parallel Redundancy Analysis Using GPU for Memory Repair.
IEEE Trans. Very Large Scale Integr. Syst.
Seung Ho Shin, Hayoung Lee, Sungho Kang
2025 J jnl
Low Cost TSV Repair Architecture Using Switch-Based Matrix for Highly Clustered Faults.
IEEE Access
Seokjun Jang, Donghyun Han, Sunghoon Kim, Dayoung Kim, Sungho Kang
2025 J jnl
Multistage Enhanced Diagnosis With Fault Candidate Reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hyojoon Yun, Hyeonchan Lim, Hayoung Lee, Sungho Kang
2025 J jnl
PASS: Pattern-Sequence-Authentication-Based Secure Scan Against Reverse Engineering Attacks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Seokjun Jang, Youngki Moon, Duyeon Won, Sungho Kang
2025 J jnl
PETRA: Powerful Early Termination-Based Redundancy Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Youngkwang Lee, Hyojun Yun, Younwoo Yoo, Sungho Kang
2025 J jnl
RAPID: Redundancy Analysis With Parallelized and Intelligent Distribution.
IEEE Access
Younwoo Yoo, Hayoung Lee, Seung Ho Shin, Sungho Kang
2025 J jnl
SPOT: Fast and Optimal Built-In Redundancy Analysis Using Smart Potential Case Collection.
IEEE Trans. Very Large Scale Integr. Syst.
Donghyun Han, Sunghoon Kim, Dayoung Kim, Sungho Kang
2025 J jnl
TSV Built-In Self-Repair Architecture for Lifespan Reliability Enhancement of HBM.
IEEE Trans. Reliab.
Donghyun Han, Duyeon Won, Sunghoon Kim, Sungho Kang
2024 J jnl
A New Fail Address Memory Architecture for Cost-Effective ATE.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hayoung Lee, Sooryeong Lee, Sungho Kang
2024 J jnl
A New ISA for High-Speed and Area-Efficient ALPG.
IEEE Trans. Circuits Syst. II Express Briefs
Juyong Lee, Hayoung Lee, Sooryeong Lee, Sungho Kang
2024 J jnl
A New Zero-Overhead Test Method for Low-Power AI Accelerators.
IEEE Trans. Circuits Syst. II Express Briefs
Sangjun Lee, Jongho Park, Sungwhan Park, Hyemin Kim, Sungho Kang
2024 — conf
APAPG: Address Pre-Processed ALPG for High-Speed Linear Test.
ISOCC
Sooryeong Lee, Hayoung Lee, Juyong Lee, Sungho Kang
2024 J jnl
An Area-Efficient Systolic Array Redundancy Architecture for Reliable AI Accelerator.
IEEE Trans. Very Large Scale Integr. Syst.
Hayoung Lee, Jongho Park, Sungho Kang
2024 J jnl
An Efficient Scan Diagnosis for Intermittent Faults Using CNN With Multi-Channel Data.
IEEE Access
Hyojoon Yun, Hyeonchan Lim, Hayoung Lee, Doohyun Yoon, Sungho Kang
2024 — conf
Effective Data-Width Aware ECC Scheme for HBM.
ISOCC
Seung Ho Shin, Youngki Moon, Byungsoo Kim, Sungho Kang
2024 J jnl
GRAP: Efficient GPU-Based Redundancy Analysis Using Parallel Evaluation for Cross Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Seung Ho Shin, Hayoung Lee, Sungho Kang
2024 J jnl
RA-Aware Fail Data Collection Architecture for Cost Reduction.
IEEE Trans. Very Large Scale Integr. Syst.
Hayoung Lee, Sooryeong Lee, Sungho Kang
2024 J jnl
Reconfigurable Multi-Bit Scan Flip-Flop for Cell-Aware Diagnosis.
IEEE Trans. Circuits Syst. II Express Briefs
Hyeonchan Lim, Tae-Hyun Kim, Sungho Kang
2024 — conf
Scan Architecture with Data Observation for Multiple Scan Cell Fault Diagnosis.
ISOCC
Juyong Lee, Sooryeong Lee, Hayoung Lee, Sungho Kang
2024 — conf
Signal Shifting-based Reusable Redundant TSV Structure for Infrastructure TSV.
ISOCC
Donghyun Han, Sunghoon Kim, Sungho Kang
2023 — conf
A New Flip-flop Shared Architecture of Test Point Insertion for Scan Design.
ISOCC
Hyemin Kim, Sangjun Lee, Jongho Park, Sungwhan Park, Sungho Kang
2023 — conf
GPU-Based Redundancy Analysis using Partitioning Method for Memory Repair.
ISOCC
Younwoo Yoo, Hayoung Lee, Seung Ho Shin, Sungho Kang
2023 — conf
LOTS: Low Overhead TSV Repair Method Using IEEE-1838 Standard Architecture.
ISOCC
Sunghoon Kim, Donghyun Han, Seokjun Jang, Sungho Kang
2023 — conf
Machine Learning based Scan Chain Diagnosis for Double Faults.
ISOCC
Hyojoon Yun, Tae-Hyun Kim, Sungho Kang
2023 J jnl
Novel Error-Tolerant Voltage-Divider-Based Through-Silicon-Via Test Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Youngkwang Lee, Donghyun Han, Sooryeong Lee, Sungho Kang
2023 — conf
Redundancy Analysis Simplification Scheme for High-Speed Memory Repair.
ISOCC
Hayoung Lee, Younwoo Yoo, Seung Ho Shin, Sungho Kang
2023 J jnl
STRAIT: Self-Test and Self-Recovery for AI Accelerator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hayoung Lee, Jihye Kim, Jongho Park, Sungho Kang
2023 J jnl
Scan Chain Architecture With Data Duplication for Multiple Scan Cell Fault Diagnosis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sunghoon Kim, Seokjun Jang, Sungho Kang
2023 J jnl
Shift Left Quality Management System (QMS) Using a 3-D Matrix Scanning Method on System on a Chip.
IEEE Trans. Circuits Syst. II Express Briefs
Yong Lee, Seokjun Jang, Sungho Kang
2023 J jnl
TRUST: Through-Silicon via Repair Using Switch Matrix Topology.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hayoung Lee, Seung Ho Shin, Younwoo Yoo, Sungho Kang
2023 J jnl
TSV Built-In Self-Repair Architecture for Improving the Yield and Reliability of HBM.
IEEE Trans. Very Large Scale Integr. Syst.
Youngkwang Lee, Donghyun Han, Sungho Kang
2022 J jnl
A Hybrid Test Scheme for Automotive IC in Multisite Testing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hyeonchan Lim, Hyojoon Yun, Sungho Kang
2022 — conf
An Improved Early Termination Methodology Using Convolutional Neural Network.
ISOCC
Seung Ho Shin, Hayoung Lee, Sooryeong Lee, Younwoo Yoo, Sungho Kang
2022 — conf
Cell-Aware Scan Diagnosis Using Partially Synchronous Set and Reset.
ISOCC
Hyeonchan Lim, Hyojoon Yun, Juyong Lee, Sungho Kang
2022 — conf
Correlation Aware Random Pattern Generation for Test Time and Shift Power Reduction of Logic BIST.
ISOCC
Jongho Park, Sangjun Lee, Inhwan Lee, Sungwhan Park, Sungho Kang
2022 J jnl
ECMO: ECC Architecture Reusing Content-Addressable Memories for Obtaining High Reliability in DRAM.
IEEE Trans. Very Large Scale Integr. Syst.
Hayoung Lee, Younwoo Yoo, Seung Ho Shin, Sungho Kang
2022 — conf
FAME: Fault Address Memory Structure for Repair Time Reduction.
ISOCC
Hayoung Lee, Sooryeong Lee, Younwoo Yoo, Seung Ho Shin, Sungho Kang
2022 J jnl
Herringbone-Based TSV Architecture for Clustered Fault Repair and Aging Recovery.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sangmin Park, Minho Cheong, Donghyun Han, Sungho Kang
2022 — conf
Logic Diagnosis Based on Deep Learning for Multiple Faults.
ISOCC
Tae Hyun Kim, Hyeonchan Lim, Minho Cheong, Hyojoon Yun, Sungho Kang
2022 J jnl
Multibank Optimized Redundancy Analysis Using Efficient Fault Collection.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hogyeong Kim, Hayoung Lee, Donghyun Han, Sungho Kang
2022 — conf
PROG: Per-Row Output Generator for BOST.
ISOCC
Sooryeong Lee, Hayoung Lee, Younwoo Yoo, Seung Ho Shin, Sungho Kang
2022 — conf
Pair-Grouping Scan Chain Architecture for Multiple Scan Cell Fault Diagnosis.
ISOCC
Sunghoon Kim, Seokjun Jang, Youngki Moon, Sungho Kang
2022 J jnl
Reduced-Pin-Count BOST for Test-Cost Reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Youngkwang Lee, Young-Woo Lee, Sungyoul Seo, Sungho Kang
2022 J jnl
SPAR: A New Test-Point Insertion Using Shared Points for Area Overhead Reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Gyungbin Kim, Minho Cheong, Sungho Kang
2022 J jnl
Scan Cell Modification for Intra Cell-Aware Scan Chain Diagnosis.
IEEE Trans. Circuits Syst. II Express Briefs
Hyeonchan Lim, Hyojoon Yun, Sungho Kang
2022 — conf
ZOS: Zero Overhead Scan for Systolic Array-based AI accelerator.
ISOCC
Jihye Kim, Hayoung Lee, Jongho Park, Sungho Kang
2021 — conf
A Circular-based TSV Repair Architecture.
ISOCC
Youngkwang Lee, Donghyun Han, Sooryeong Lee, Sungho Kang
2021 J jnl
A Low-Power BIST Scheme Using Weight-Aware Scan Grouping and Scheduling for Automotive ICs.
IEEE Access
Kwonhyoung Lee, Sangjun Lee, Jongho Park, Inhwan Lee, Sungho Kang
2021 J jnl
A Secure Scan Architecture Protecting Scan Test and Scan Dump Using Skew-Based Lock and Key.
IEEE Access
Hyungil Woo, Seokjun Jang, Sungho Kang
2021 — conf
An Effective Spare Allocation Methodology for 3D Memory Repair with BIRA.
ISOCC
Seung Ho Shin, Hayoung Lee, Younwoo Yoo, Sungho Kang
2021 J jnl
An In-DRAM BIST for 16 Gb DDR4 DRAM in the 2nd 10-nm-Class DRAM Process.
IEEE Access
Jaewon Park, Jae Hoon Lee, Sang-Kil Park, Ki Chul Chun, Kyomin Sohn, Sungho Kang
2021 — conf
Area Efficient Built-In Redundancy Analysis using Pre-Solutions with Various Spare Structure.
ISOCC
Youngki Moon, Hyunho Yoo, Donghyun Han, Sungho Kang
2021 J jnl
ECC-Aware Fast and Reliable Pattern Matching Redundancy Analysis for Highly Reliable Memory.
IEEE Access
Donghyun Han, Hayoung Lee, Seungtaek Lee, Sungho Kang
2021 J jnl
Effective Spare Line Allocation Built-in Redundancy Analysis With Base Common Spare for Yield Improvement of 3D Memory.
IEEE Access
Donghyun Han, Hayoung Lee, Sungho Kang
2021 J jnl
Enhanced Postbond Test Architecture for Bridge Defects Between the TSVs.
IEEE Trans. Very Large Scale Integr. Syst.
Jungil Mok, Hyeonchan Lim, Sungho Kang
2021 — conf
Hardware Efficient Built-in Self-test Architecture for Power and Ground TSVs in 3D IC.
ISOCC
Donghyun Han, Youngkwang Lee, Sooryeong Lee, Sungho Kang
2021 — conf
Hybrid Test Access Mechanism for Multiple Identical Cores.
ISOCC
Sangjun Lee, Jongho Park, Inhwan Lee, Kwonhyoung Lee, Sungho Kang
2021 J jnl
Low-Power Scan Correlation-Aware Scan Cluster Reordering for Wireless Sensor Networks.
Sensors
Sangjun Lee, Kyunghwan Cho, Jihye Kim, Jongho Park, Inhwan Lee, Sungho Kang
2021 J jnl
On-Chip Error Detection Reusing Built-In Self-Repair for Silicon Debug.
IEEE Access
Hayoung Lee, Hyunggoy Oh, Sungho Kang
2021 — conf
Post-bond Repair of Line Faults with Double-bit ECC for 3D Memory.
ISOCC
Younwoo Yoo, Hayoung Lee, Seung Ho Shin, Sungho Kang
2021 J jnl
Reconfigurable Scan Architecture for High Diagnostic Resolution.
IEEE Access
Seokjun Jang, Jihye Kim, Sungho Kang
2021 — conf
Secure Scan Design through Pseudo Fault Injection.
ISOCC
Seokjun Jang, Hyungil Woo, Sunghoon Kim, Sungho Kang
2020 J jnl
A 3-D Rotation-Based Through-Silicon via Redundancy Architecture for Clustering Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Minho Cheong, Ingeol Lee, Sungho Kang
2020 J jnl
A New Logic Topology-Based Scan Chain Stitching for Test-Power Reduction.
IEEE Trans. Circuits Syst.
Sangjun Lee, Kyunghwan Cho, Sungki Choi, Sungho Kang
2020 — conf
Diagnosis of Scan Chain Faults Based-on Machine-Learning.
ISOCC
Hyeonchan Lim, Tae Hyun Kim, Seunghwan Kim, Sungho Kang
2020 A conf
Fail Memory Configuration Set for RA Estimation.
ITC
Hayoung Lee, Keewon Cho, Sungho Kang, Wooheon Kang, Seungtaek Lee, Woosik Jeong
2020 J jnl
Fine-Grained Defect Diagnosis for CMOL FPGA Circuits.
IEEE Access
Jihye Kim, Hayoung Lee, Seokjun Jang, Sungho Kang
2020 J jnl
GPU-Based Redundancy Analysis Using Concurrent Evaluation.
IEEE Trans. Very Large Scale Integr. Syst.
Tae Hyun Kim, Hayoung Lee, Sungho Kang
2020 — conf
Memory-like Defect Diagnosis for CMOL FPGAs.
ISOCC
Jihye Kim, Hayoung Lee, Seokjun Jang, Hogyeong Kim, Sungho Kang
2020 — conf
Redundancy Analysis Optimization with Clustered Known Solutions for High Speed Repair.
ISOCC
Hayoung Lee, Donghyun Han, Hogyeong Kim, Sungho Kang
2020 J jnl
Robust Secure Shield Architecture for Detection and Protection Against Invasive Attacks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Young-Woo Lee, Hyeonchan Lim, Youngkwang Lee, Sungho Kang
2020 J jnl
Scan-Chain-Fault Diagnosis Using Regressions in Cryptographic Chips for Wireless Sensor Networks.
Sensors
Hyunyul Lim, Minho Cheong, Sungho Kang
2020 — conf
W-ERA: One-Time Memory Repair with Wafer-Level Early Repair Analysis for Cost Reduction.
ITC-Asia
Hayoung Lee, Donghyun Han, Hogyeong Kim, Sungho Kang
2019 — conf
A Hardware-efficient TSV Repair Scheme Based on Butterfly Topology.
ISOCC
Minho Cheng, Hyunyul Lim, Tae Hyun Kim, Sungho Kang
2019 — conf
A New Scan Chain Reordering Method for Low Power Consumption based on Care Bit Density.
ISOCC
Kyunghwan Cho, Jihye Kim, Hyunggoy Oh, Sangjun Lee, Sungho Kang
2019 J jnl
An Efficient BIRA Utilizing Characteristics of Spare Pivot Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Keewon Cho, Young-Woo Lee, Sungyoul Seo, Sungho Kang
2019 J jnl
Dynamic Built-In Redundancy Analysis for Memory Repair.
IEEE Trans. Very Large Scale Integr. Syst.
Hayoung Lee, Donghyun Han, Seungtaek Lee, Sungho Kang
2019 J jnl
Highly Reliable Redundant TSV Architecture for Clustered Faults.
IEEE Trans. Reliab.
Ingeol Lee, Minho Cheong, Sungho Kang
2019 — conf
Redundancy Analysis based on Fault Distribution for Memory with Complex Spares.
ISOCC
Hayoung Lee, Donghyun Han, Seungtaek Lee, Sungho Kang
2019 J jnl
TSV Repair Architecture for Clustered Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jaewon Jang, Minho Cheong, Sungho Kang
2019 J jnl
Test-Friendly Data-Selectable Self-Gating (DSSG).
IEEE Trans. Very Large Scale Integr. Syst.
Jihye Kim, Sangjun Lee, Sungho Kang
2019 — conf
Transition-delay Test Methodology for Designs with Self-gating.
ISOCC
Jihye Kim, Sangjun Lee, Minho Moon, Sungho Kang
2019 — conf
Tunable Compact Probing Detector with Fast Analysis Time Against Invasive Attacks.
ISOCC
Young-Woo Lee, Youngkwang Lee, Minho Moon, Sungho Kang
2018 — conf
2-D Failure Bitmap Compression Using Line Fault Marking Method.
ISOCC
Keewon Cho, Young-Woo Lee, Sungyoul Seo, Sungho Kang
2018 C conf
3D Memory Formed of Unrepairable Memory Dice and Spare Layer.
TENCON
Donghyun Han, Hayoung Lee, Seungtaek Lee, Minho Moon, Sungho Kang
2018 — conf
A Software-based Scan Chain Diagnosis for Double Faults in A Scan Chain.
ISOCC
Hyeonchan Lim, Seokjun Jang, Sungho Kang
2018 J jnl
A Statistic-Based Scan Chain Reordering for Energy-Quality Scalable Scan Test.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Sungyoul Seo, Keewon Cho, Young-Woo Lee, Sungho Kang
2018 — conf
A Test Methodology for Neural Computing Unit.
ISOCC
Minho Cheong, Ingeol Lee, Sungho Kang
2018 J jnl
An Area-Efficient BIRA With 1-D Spare Segments.
IEEE Trans. Very Large Scale Integr. Syst.
Donghyun Kim, Hayoung Lee, Sungho Kang
2018 — conf
Dynamic voltage Drop induced Path Delay Analysis for STV and NTV Circuits during At-speed Scan Test.
ISOCC
Hyunggoy Oh, Heetae Kim, Sangjun Lee, Sungho Kang
2018 J jnl
Fast Built-In Redundancy Analysis Based on Sequential Spare Line Allocation.
IEEE Trans. Reliab.
Hayoung Lee, Jooyoung Kim, Keewon Cho, Sungho Kang
2018 J jnl
Fault Group Pattern Matching With Efficient Early Termination for High-Speed Redundancy Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hayoung Lee, Kiwon Cho, Donghyun Kim, Sungho Kang
2018 — conf
Low Power Scan Chain Architecture Based on Circuit Topology.
ISOCC
Heetae Kim, Hyunggoy Oh, Sangjun Lee, Sungho Kang
2018 C conf
Neural Network Reliability Enhancement Approach Using Dropout Underutilization in GPU.
TENCON
Dongsu Lee, Hyunyul Lim, Tae Hyun Kim, Sungho Kang
2018 J jnl
Test Resource Reused Debug Scheme to Reduce the Post-Silicon Debug Cost.
IEEE Trans. Computers
Inhyuk Choi, Hyunggoy Oh, Young-Woo Lee, Sungho Kang
2018 J jnl
Thermal Aware Test Scheduling for NTV Circuit.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jaeil Lim, Hyunggoy Oh, Heetae Kim, Sungho Kang
2017 — conf
A new repair scheme for TSV-based 3D memory using base die repair cells.
ISOCC
Donghyun Han, Hayoung Lee, Donghyun Kim, Sungho Kang
2017 J jnl
A novel X-filling method for capture power reduction.
IEICE Electron. Express
Heetae Kim, Hyunggoy Oh, Jaeil Lim, Sungho Kang
2017 — conf
A selective error data capture method using on-chip DRAM for silicon debug of multi-core design.
ISOCC
Hyunggoy Oh, Heetae Kim, Jaeil Lim, Sungho Kang
2017 J jnl
An On-Chip Error Detection Method to Reduce the Post-Silicon Debug Time.
IEEE Trans. Computers
Hyunggoy Oh, Taewoo Han, Inhyuk Choi, Sungho Kang
2017 — conf
An efficient built-in self-repair scheme for area reduction.
ISOCC
Keewon Cho, Young-Woo Lee, Sungyoul Seo, Sungho Kang
2017 — conf
Broadcast scan compression based on deterministic pattern generation algorithm.
ISQED
Hyeonchan Lim, Sungyoul Seo, Soyeon Kang, Sungho Kang
2017 J jnl
Chain-Based Approach for Fast Through-Silicon-Via Coupling Delay Estimation.
IEEE Trans. Very Large Scale Integr. Syst.
Jaewon Jang, Minho Cheong, Jin-Ho Ahn, Sung Kyu Lim, Sungho Kang
2017 J jnl
DRAM-Based Error Detection Method to Reduce the Post-Silicon Debug Time for Multiple Identical Cores.
IEEE Trans. Computers
Hyunggoy Oh, Inhyuk Choi, Sungho Kang
2017 J jnl
FRESH: A New Test Result Extraction Scheme for Fast TSV Tests.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jaeseok Park, Hyunyul Lim, Sungho Kang
2017 J jnl
Grouping-Based TSV Test Architecture for Resistive Open and Bridge Defects in 3-D-ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Young-Woo Lee, Hyeonchan Lim, Sungho Kang
2017 J jnl
Hardware-Efficient Built-In Redundancy Analysis for Memory With Various Spares.
IEEE Trans. Very Large Scale Integr. Syst.
Jooyoung Kim, Woosung Lee, Keewon Cho, Sungho Kang
2017 — conf
LARECD: Low area overhead and reliable error correction DMR architecture.
ISOCC
Hyunyul Lim, Tae Hyun Kim, Dongsu Lee, Sungho Kang
2017 — conf
Off-chip test architecture for improving multi-site testing efficiency using tri-state decoder and 3V-level encoder.
ISQED
Sungyoul Seo, Hyeonchan Lim, Soyeon Kang, Sungho Kang
2017 J jnl
Proof of Concept of Home IoT Connected Vehicles.
Sensors
Younsun Kim, Hyunggoy Oh, Sungho Kang
2017 J jnl
R
IEEE Trans. Reliab.
Jaeseok Park, Minho Cheong, Sungho Kang
2017 J jnl
Reconfigurable scan architecture for test power and data volume reduction.
IEICE Electron. Express
Hyunggoy Oh, Heetae Kim, Jaeil Lim, Sungho Kang
2017 — conf
Test data reduction method based on berlekamp-massey algorithm.
ISOCC
Hyeonchan Lim, Junghwan Kim, Soyeon Kang, Sungho Kang
2016 J jnl
A New 3-D Fuse Architecture to Improve Yield of 3-D Memories.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wooheon Kang, Changwook Lee, Hyunyul Lim, Sungho Kang
2016 J jnl
A Survey of Repair Analysis Algorithms for Memories.
ACM Comput. Surv.
Keewon Cho, Wooheon Kang, Hyungjun Cho, Changwook Lee, Sungho Kang
2016 — conf
A new online test and debug methodology for automotive camera image processing system.
APCCAS
Hyunggoy Oh, Inhyuk Choi, Sungho Kang
2016 — conf
A test methodology to screen scan-path failures.
ISOCC
Junghwan Kim, Young-Woo Lee, Minho Cheong, Sungyoul Seo, Sungho Kang
2016 — conf
Discussion of cost-effective redundancy architectures.
ISOCC
Keewon Cho, Jooyoung Kim, Hayoung Lee, Sungho Kang
2016 J jnl
Optimized Built-In Self-Repair for Multiple Memories.
IEEE Trans. Very Large Scale Integr. Syst.
Wooheon Kang, Changwook Lee, Hyunyul Lim, Sungho Kang
2016 — conf
P-backtracking: A new scan chain diagnosis method with probability.
ISOCC
Tae Hyun Kim, Hyunyul Lim, Sungho Kang
2016 J jnl
Parallelized Network-on-Chip-Reused Test Access Mechanism for Multiple Identical Cores.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Taewoo Han, Inhyuk Choi, Hyunggoy Oh, Sungho Kang
2016 — conf
Process variation-aware bridge fault analysis.
ISOCC
Heetae Kim, Inhyuk Choi, Jaeil Lim, Hyunggoy Oh, Sungho Kang
2016 — conf
Software-based embedded core test using multi-polynomial for test data reduction.
ISOCC
Soyeon Kang, Inhyuk Choi, Hyeonchan Lim, Sungyoul Seo, Sungho Kang
2016 — conf
Test access mechaism for stack test time reduction of 3-dimensional integrated circuit.
APCCAS
Inhyuk Choi, Hyunggoy Oh, Sungho Kang
2016 J jnl
Tri-State Coding Using Reconfiguration of Twisted Ring Counter for Test Data Compression.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sungyoul Seo, Yong Lee, Sungho Kang
2015 J jnl
3-D Stacked DRAM Refresh Management With Guaranteed Data Reliability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jaeil Lim, Hyunyul Lim, Sungho Kang
2015 J jnl
A 3 Dimensional Built-In Self-Repair Scheme for Yield Improvement of 3 Dimensional Memories.
IEEE Trans. Reliab.
Wooheon Kang, Changwook Lee, Hyunyul Lim, Sungho Kang
2015 J jnl
A Novel Massively Parallel Testing Method Using Multi-Root for High Reliability.
IEEE Trans. Reliab.
Haksong Kim, Yong Lee, Sungho Kang
2015 — conf
A scan shifting method based on clock gating of multiple groups for low power scan testing.
ISQED
Sungyoul Seo, Yong Lee, Joohwan Lee, Sungho Kang
2015 J jnl
Eco Assist Techniques through Real-time Monitoring of BEV Energy Usage Efficiency.
Sensors
Younsun Kim, Ingeol Lee, Sungho Kang
2015 J jnl
Lifetime Reliability Enhancement of Microprocessors: Mitigating the Impact of Negative Bias Temperature Instability.
ACM Comput. Surv.
Hyejeong Hong, Jaeil Lim, Hyunyul Lim, Sungho Kang
2015 — conf
Low power scan bypass technique with test data reduction.
ISQED
Hyunyul Lim, Wooheon Kang, Sungyoul Seo, Yong Lee, Sungho Kang
2015 J jnl
Majority-Based Test Access Mechanism for Parallel Testing of Multiple Identical Cores.
IEEE Trans. Very Large Scale Integr. Syst.
Taewoo Han, Inhyuk Choi, Sungho Kang
2015 — conf
Near optimal repair rate built-in redundancy analysis with very small hardware overhead.
ISQED
Woosung Lee, Keewon Cho, Jooyoung Kim, Sungho Kang
2015 J jnl
Reduced-code test method using sub-histograms for pipelined ADCs.
IEICE Electron. Express
HyeonUk Son, Jaewon Jang, Heetae Kim, Sungho Kang
2015 — conf
Scan Chain Reordering-Aware X-Filling and Stitching for Scan Shift Power Reduction.
ATS
Sungyoul Seo, Yong Lee, Hyeonchan Lim, Joohwan Lee, Hongbom Yoo, Yojoung Kim, Sungho Kang
2014 J jnl
A BIRA for Memories With an Optimal Repair Rate Using Spare Memories for Area Reduction.
IEEE Trans. Very Large Scale Integr. Syst.
Wooheon Kang, Hyungjun Cho, Joohwan Lee, Sungho Kang
2014 J jnl
A Delay Test Architecture for TSV With Resistive Open Defects in 3-D Stacked Memories.
IEEE Trans. Very Large Scale Integr. Syst.
Hyungsu Sung, Keewon Cho, Kunsang Yoon, Sungho Kang
2014 J jnl
A New Fuse Architecture and a New Post-Share Redundancy Scheme for Yield Enhancement in 3-D-Stacked Memories.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Changwook Lee, Wooheon Kang, Donkoo Cho, Sungho Kang
2014 — conf
A Scalable and Parallel Test Access Strategy for NoC-Based Multicore System.
ATS
Taewoo Han, Inhyuk Choi, Hyunggoy Oh, Sungho Kang
2014 J jnl
A novel test access mechanism for parallel testing of multi-core system.
IEICE Electron. Express
Taewoo Han, Inhyuk Choi, Sungho Kang
2014 J jnl
Recovery-enhancing task scheduling for multicore processors under NBTI impact.
IEICE Electron. Express
Hyejeong Hong, Jaeil Lim, Sungho Kang
2013 — conf
A Die Selection and Matching Method with Two Stages for Yield Enhancement of 3-D Memories.
Asian Test Symposium
Wooheon Kang, Changwook Lee, Keewon Cho, Sungho Kang
2013 J jnl
Acceleration of Deep Packet Inspection Using a Multi-Byte Processing Prefilter.
IEICE Trans. Commun.
Hyejeong Hong, Sungho Kang
2013 — conf
Bit transmission error correction scheme for FlexRay based automotive communication systems.
GCCE
Inhyuk Choi, Taewoo Han, Sungho Kang
2013 J jnl
Built-In Self-Test for Static ADC Testing with a Triangle-Wave.
IEICE Trans. Electron.
Incheol Kim, Ingeol Lee, Sungho Kang
2013 J jnl
Dynamic thermal management for 3D multicore processors under process variations.
IEICE Electron. Express
Hyejeong Hong, Jaeil Lim, Hyunyul Lim, Sungho Kang
2013 J jnl
Thermal-aware dynamic voltage frequency scaling for many-core processors under process variations.
IEICE Electron. Express
Hyejeong Hong, Jaeil Lim, Hyunyul Lim, Sungho Kang
2012 J jnl
A method for the fast diagnosis of multiple defects using an efficient candidate selection algorithm.
IEICE Electron. Express
Yoseop Lim, Jaeseok Park, Sungho Kang
2012 J jnl
An accurate diagnosis of transition fault clusters based on single fault simulation.
IEICE Electron. Express
Yoseop Lim, Jaeseok Park, Sungho Kang
2012 J jnl
An efficient IP address lookup algorithm based on a small balanced tree using entry reduction.
Comput. Networks
Hyuntae Park, Hyejeong Hong, Sungho Kang
2012 — conf
Integration of dual channel timing formatter system for high speed memory test equipment.
ISOCC
Jaeseok Park, Ingeol Lee, Young-Seok Park, Sung-Geun Kim, Kyungho Ryu, Dong-Hoon Jung, Kangwook Jo, Choong Keun Lee, Hongil Yoon, Seong-Ook Jung, Woo-Young Choi, Sungho Kang
2011 J jnl
A Lossless Color Image Compression Architecture Using a Parallel Golomb-Rice Hardware CODEC.
IEEE Trans. Circuits Syst. Video Technol.
Hong-Sik Kim, Joohong Lee, HyunJin Kim, Sungho Kang, Woo-Chan Park
2011 J jnl
A Memory-Efficient Bit-Split Parallel String Matching Using Pattern Dividing for Intrusion Detection Systems.
IEEE Trans. Parallel Distributed Syst.
HyunJin Kim, Hong-Sik Kim, Sungho Kang
2011 J jnl
An Efficient IP Address Lookup Scheme Using Balanced Binary Search with Minimal Entry and Optimal Prefix Vector.
IEICE Trans. Commun.
Hyuntae Park, Hyejeong Hong, Sungho Kang
2011 J jnl
Communication-aware task scheduling and voltage selection for total energy minimization in a multiprocessor system using Ant Colony Optimization.
Inf. Sci.
HyunJin Kim, Sungho Kang
2011 J jnl
Noise-Tolerant DAC BIST Scheme Using Integral Calculus Approach.
IEICE Trans. Electron.
HyeonUk Son, Incheol Kim, Sang-Goog Lee, Jin-Ho Ahn, Jeong-Do Kim, Sungho Kang
2011 — conf
Path search engine for fast optimal path search using efficient hardware architecture.
ISOCC
Inhyuk Choi, Taewoo Han, Ilwoong Kim, Sungho Kang
2010 J jnl
A Fast IP Address Lookup Algorithm Based on Search Space Reduction.
IEICE Trans. Commun.
Hyuntae Park, HyunJin Kim, Hong-Sik Kim, Sungho Kang
2010 J jnl
A Hardware-Efficient Pattern Matching Architecture Using Process Element Tree for Deep Packet Inspection.
IEICE Trans. Commun.
Seongyong Ahn, Hyejeong Hong, HyunJin Kim, Jin-Ho Ahn, Dongmyong Baek, Sungho Kang
2010 J jnl
A Memory-Efficient Pattern Matching with Hardware-Based Bit-Split String Matchers for Deep Packet Inspection.
IEICE Trans. Commun.
HyunJin Kim, Hong-Sik Kim, Jung-Hee Lee, Jin-Ho Ahn, Sungho Kang
2010 J jnl
A Pattern Group Partitioning for Parallel String Matching using a Pattern Grouping Metric.
IEEE Commun. Lett.
HyunJin Kim, Sungho Kang
2010 J jnl
A Pattern Partitioning Algorithm for Memory-Efficient Parallel String Matching in Deep Packet Inspection.
IEICE Trans. Commun.
HyunJin Kim, Hyejeong Hong, Dongmyong Baek, Sungho Kang
2010 J jnl
A Selective Scan Chain Activation Technique for Minimizing Average and Peak Power Consumption.
IEICE Trans. Inf. Syst.
YongJoon Kim, Jaeseok Park, Sungho Kang
2010 J jnl
A high performance network-on-chip scheme using lossless data compression.
IEICE Electron. Express
Hong-Sik Kim, Young H. Jung, HyunJin Kim, Jin-Ho Ahn, Woo-Chan Park, Sungho Kang
2010 J jnl
A memory-efficient heterogeneous parallel pattern matching scheme in deep packet inspection.
IEICE Electron. Express
HyunJin Kim, Hyejeong Hong, Dongmyoung Baek, Jin-Ho Ahn, Sungho Kang
2010 J jnl
An Advanced BIRA for Memories With an Optimal Repair Rate and Fast Analysis Speed by Using a Branch Analyzer.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Woosik Jeong, Joohwan Lee, Taewoo Han, Kaangchil Lee, Sungho Kang
2010 J jnl
EOF: Efficient Built-In Redundancy Analysis Methodology With Optimal Repair Rate.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Myung-Hoon Yang, Hyungjun Cho, Wooheon Kang, Sungho Kang
2010 J jnl
Selective Scan Slice Grouping Technique for Efficient Test Data Compression.
IEICE Trans. Inf. Syst.
YongJoon Kim, Jaeseok Park, Sungho Kang
2009 Misc conf
A High-Level Signal Integrity Fault Model and Test Methodology for Long On-Chip Interconnections.
VTS
Sunghoon Chun, YongJoon Kim, Taejin Kim, Sungho Kang
2009 J jnl
A memory-efficient parallel string matching for intrusion detection systems.
IEEE Commun. Lett.
HyunJin Kim, Hyejeong Hong, Hong-Sik Kim, Sungho Kang
2009 — conf
An Ant Colony Optimization Approach for the Preference-Based Shortest Path Search.
FGIT-FGCN
Seung Ho Ok, Woo-Jin Seo, Jin-Ho Ahn, Sungho Kang, Byung In Moon
2009 J jnl
An Effective Programmable Memory BIST for Embedded Memory.
IEICE Trans. Inf. Syst.
Youngkyu Park, Jaeseok Park, Taewoo Han, Sungho Kang
2009 — conf
An Efficient Hardware Architecture of the A-star Algorithm for the Shortest Path Search Engine.
NCM
Woo-Jin Seo, Seung Ho Ok, Jin-Ho Ahn, Sungho Kang, Byung In Moon
2009 — conf
FPGA-based verification methodology of SoC-type CMOS image signal processor.
SoCC
Younsun Kim, Hong-Sik Kim, R. Lee, Sungho Kang
2009 J jnl
Grouped Scan Slice Repetition Method for Reducing Test Data Volume and Test Application Time.
IEICE Trans. Inf. Syst.
YongJoon Kim, Myung-Hoon Yang, Jaeseok Park, Eunsei Park, Sungho Kang
2009 J jnl
Selective scan slice repetition for simultaneous reduction of test power consumption and test data volume.
IEICE Electron. Express
YongJoon Kim, Jaeseok Park, Sungho Kang
2008 J jnl
A Low-Cost BIST Based on Histogram Testing for Analog to Digital Converters.
IEICE Trans. Electron.
Kicheol Kim, Youbean Kim, Incheol Kim, HyeonUk Son, Sungho Kang
2008 J jnl
A New Scan Architecture for Both Low Power Testing and Test Volume Compression Under SOC Test Environment.
J. Electron. Test.
Hong-Sik Kim, Sungho Kang, Michael S. Hsiao
2008 — conf
An Effective Hybrid Test Data Compression Method Using Scan Chain Compaction and Dictionary-Based Scheme.
ATS
Taejin Kim, Sunghoon Chun, YongJoon Kim, Myung-Hoon Yang, Sungho Kang
2008 J jnl
An Effective Power Reduction Methodology for Deterministic BIST Using Auxiliary LFSR.
J. Electron. Test.
Myung-Hoon Yang, YongJoon Kim, Sunghoon Chun, Sungho Kang
2008 Misc conf
An Efficient Scan Chain Diagnosis Method Using a New Symbolic Simulation.
VTS
Sunghoon Chun, Taejin Kim, YongJoon Kim, Sungho Kang
2008 J jnl
Ant colony based efficient triplet calculation methodology for arithmetic built-in self test.
IEICE Electron. Express
Hong-Sik Kim, HyunJin Kim, Sungho Kang
2008 J jnl
MTR-Fill: A Simulated Annealing-Based X-Filling Technique to Reduce Test Power Dissipation for Scan-Based Designs.
IEICE Trans. Inf. Syst.
DongSup Song, Jin-Ho Ahn, Taejin Kim, Sungho Kang
2008 J jnl
Total Energy Minimization of Real-Time Tasks in an On-Chip Multiprocessor Using Dynamic Voltage Scaling Efficiency Metric.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
HyunJin Kim, Hyejeong Hong, Hong-Sik Kim, Jin-Ho Ahn, Sungho Kang
2008 — conf
XPDF-ATPG: An Efficient Test Pattern Generation for Crosstalk-Induced Faults.
ATS
Sunghoon Chun, YongJoon Kim, Taejin Kim, Myung-Hoon Yang, Sungho Kang
2007 J jnl
A New Analog-to-Digital Converter BIST Considering a Transient Zone.
IEICE Trans. Electron.
Incheol Kim, Kicheol Kim, Youbean Kim, HyeonUk Son, Sungho Kang
2007 J jnl
Deterministic built-in self-test using split linear feedback shift register reseeding for low-power testing.
IET Comput. Digit. Tech.
Myung-Hoon Yang, Youbean Kim, Youngkyu Park, D. Lee, Sungho Kang
2007 — conf
High-MDSI: A High-level Signal Integrity Fault Test Pattern Generation Method for Interconnects.
ATS
Sunghoon Chun, YongJoon Kim, Sungho Kang
2007 J jnl
MDSI: Signal Integrity Interconnect Fault Modeling and Testing for SoCs.
J. Electron. Test.
Sunghoon Chun, YongJoon Kim, Sungho Kang
2006 J jnl
A Clustered RIN BIST Based on Signal Probabilities of Deterministic Test Sets.
IEICE Trans. Inf. Syst.
DongSup Song, Sungho Kang
2006 — conf
An Effective Test Pattern Generation for Testing Signal Integrity.
ATS
YongJoon Kim, Myung-Hoon Yang, Youngkyu Park, Daeyeal Lee, Sungho Kang
2006 J jnl
An Efficient Dictionary Organization for Maximum Diagnosis.
J. Electron. Test.
Sunghoon Chun, Sangwook Kim, Hong-Sik Kim, Sungho Kang
2006 — conf
Improved Reinforcement Computing to Implement AntNet-Based Routing Using General NPs for Ubiquitous Environments.
ICUCT
Hyuntae Park, Byung In Moon, Sungho Kang
2006 J jnl
Increasing encoding efficiency of LFSR reseeding-based test compression.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hong-Sik Kim, Sungho Kang
2006 J jnl
MICRO: a new hybrid test data compression/decompression scheme.
IEEE Trans. Very Large Scale Integr. Syst.
Sunghoon Chun, YongJoon Kim, Jung-Been Im, Sungho Kang
2006 — conf
SoC Test Scheduling Algorithm Using ACO-Based Rectangle Packing.
ICIC (2)
Jin-Ho Ahn, Sungho Kang
2006 — conf
System on a Chip Implementation of Social Insect Behavior for Adaptive Network Routing.
ICIC (2)
Jin-Ho Ahn, HyunJin Kim, Byung In Moon, Sungho Kang
2005 — conf
A New Low Power Test Pattern Generator using a Transition Monitoring Window based on BIST Architecture.
Asian Test Symposium
Youbean Kim, Myung-Hoon Yang, Yong Lee, Sungho Kang
2005 — conf
A Practical Test Scheduling Using Network-Based TAM in Network on Chip Architecture.
Asia-Pacific Computer Systems Architecture Conference
Jin-Ho Ahn, Byung In Moon, Sungho Kang
2005 J jnl
An Effective Built-In Self-Test for Chargepump PLL.
IEICE Trans. Electron.
Junseok Han, DongSup Song, Hagbae Kim, Youngyong Kim, Sungho Kang
2005 — conf
Increasing Embedding Probabilities of RPRPs in RIN Based BIST.
Asia-Pacific Computer Systems Architecture Conference
DongSup Song, Sungho Kang
2004 J jnl
A new maximal diagnosis algorithm for interconnect test.
IEEE Trans. Very Large Scale Integr. Syst.
YongJoon Kim, Hyun-Don Kim, Sungho Kang
2004 J jnl
An Acceleration Processor for Data Intensive Scientific Computing.
IEICE Trans. Inf. Syst.
Cheong Ghil Kim, Hong-Sik Kim, Sungho Kang, Shin-Dug Kim, Gunhee Han
2004 C conf
An In-Order SMT Architecture with Static Resource Partitioning for Consumer Applications.
PDCAT
Byung In Moon, Hongil Yoon, Ilgu Yun, Sungho Kang
2004 — conf
RAIN (RAndom Insertion) Scheduling Algorithm for SoC Test.
Asian Test Symposium
Jung-Been Im, Sunghoon Chun, Geunbae Kim, Jin-Ho Ahn, Sungho Kang
2004 — conf
Route Reinforcement for Efficient QoS Routing Based on Ant Algorithm.
ICOIN
Jae Seuk Oh, Sung-il Bae, Jin-Ho Ahn, Sungho Kang
2003 A conf
A New Maximal Diagnosis Algorithm for Bus-structured Systems.
ITC
YongJoon Kim, DongSub Song, YongSeung Shin, Sunghoon Chun, Sungho Kang
2003 J jnl
Accurate Logic Simulation by Overcoming the Unknown Value Propagation Problem.
Simul.
Sungho Kang, Stephen A. Szygenda
2003 J jnl
Test-decompression mechanism using a variable-length multiple-polynomial LFSR.
IEEE Trans. Very Large Scale Integr. Syst.
Hong-Sik Kim, YongJoon Kim, Sungho Kang
2002 — conf
A New DSP Architecture for Correcting Errors Using Viterbi Algorithm.
AISA
Sungchul Yoon, Sangwook Kim, Jae Seuk Oh, Sungho Kang
2002 — conf
An Efficient On-Line Monitoring BIST for Remote Service System.
AISA
Sangmin Bae, DongSup Song, Jihye Kim, Sungho Kang
2002 — conf
DPSC SRAM Transparent Test Algorithm.
Asian Test Symposium
Hong-Sik Kim, Sungho Kang
2001 C conf
A Heuristic for Multiple Weight Set Generation.
ICCD
Hong-Sik Kim, Jin-kyue Lee, Sungho Kang
2001 A conf
A new multiple weight set calculation algorithm.
ITC
Hong-Sik Kim, Jin-kyue Lee, Sungho Kang
1999 C conf
An Efficient Interconnect Test Using BIST Module in a Boundary-Scan Environment.
ICCD
HyunJin Kim, Jongchul Shin, Sungho Kang
1999 A conf
At-Speed Boundary-Scan Interconnect Testing in a Board with Multiple System Clocks.
DATE
Jongchul Shin, HyunJin Kim, Sungho Kang
1996 J jnl
A Hardware Accelerator for Fault Simulation Utilizing a Reconfigurable Array Architecture.
VLSI Design
Sungho Kang, Youngmin Hur, Stephen A. Szygenda
1995 A* conf
Massively Parallel Array Processor for Logic, Fault, and Design Error Simulation.
HPCA
Youngmin Hur, Stephen A. Szygenda, E. Scott Fehr, Granville E. Ott, Sungho Kang
1994 J jnl
Automatic Simulator Generation System.
Simul.
Sungho Kang, Stephen A. Szygenda
1994 J jnl
Design Validation: Comparing Theoretical and Empirical Results of Design Error Modeling.
IEEE Des. Test Comput.
Sungho Kang, Stephen A. Szygenda
1994 J jnl
The simulation automation system (SAS); concepts, implementation, and results.
IEEE Trans. Very Large Scale Integr. Syst.
Sungho Kang, Stephen A. Szygenda
1993 — conf
Automatic VHDL Model Generation System.
CHDL
Sungho Kang, Stephen A. Szygenda
1992 C conf
Modeling and Simulation of Design Errors.
ICCD
Sungho Kang, Stephen A. Szygenda
1992 — conf
New design error modeling and metrics for design validation.
EURO-DAC
Sungho Kang, Stephen A. Szygenda