Sung-Yun Lee

13 papers A 5Journal 5Unranked 3
YearRankTypeTitle / Venue / Authors
2026 J jnl
CTRL-B: Back-End-of-Line Configuration Optimization Using Cross-Domain Transferable Reinforcement Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jaeseung Lee, Sung-Yun Lee, Jinoh Cho, Daijoon Hyun, Seokhyeong Kang
2024 A conf
CTRL-B: Back-End-Of-Line Configuration Pathfinding Using Cross-Technology Transferable Reinforcement Learning.
DATE
Sung-Yun Lee, Kyungjun Min, Seokhyeong Kang
2024 A conf
RL-Fill: Timing-Aware Fill Insertion using Reinforcement Learning.
ICCAD
Jinoh Cho, SeongHyeon Park, Jakang Lee, Sung-Yun Lee, Jinmo Ahn, Seokhyeong Kang
2023 A conf
ClusterNet: Routing Congestion Prediction and Optimization Using Netlist Clustering and Graph Neural Networks.
ICCAD
Kyungjun Min, Seongbin Kwon, Sung-Yun Lee, Dohun Kim, Sunghye Park, Seokhyeong Kang
2023 J jnl
Construction of Realistic Place-and-Route Benchmarks for Machine Learning Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Daeyeon Kim, Sung-Yun Lee, Kyungjun Min, Seokhyeong Kang
2023 A conf
RL-Legalizer: Reinforcement Learning-based Cell Priority Optimization in Mixed-Height Standard Cell Legalization.
DATE
Sung-Yun Lee, SeongHyeon Park, Daeyeon Kim, Minjae Kim, Tuyen Pham Le, Seokhyeong Kang
2022 — conf
Signal-Integrity-Aware Interposer Bus Routing in 2.5D Heterogeneous Integration.
ASP-DAC
Sung-Yun Lee, Daeyeon Kim, Kyungjun Min, Seokhyeong Kang
2021 A conf
Machine Learning Framework for Early Routability Prediction with Artificial Netlist Generator.
DATE
Daeyeon Kim, Hyun-jeong Kwon, Sung-Yun Lee, Seungwon Kim, Mingyu Woo, Seokhyeong Kang
2020 J jnl
A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sunmean Kim, Sung-Yun Lee, Sunghye Park, Kyung Rok Kim, Seokhyeong Kang
2020 J jnl
Additive Statistical Leakage Analysis Using Exponential Mixture Model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hyun-jeong Kwon, Sung-Yun Lee, Young Hwan Kim, Seokhyeong Kang
2020 J jnl
Compact Topology-Aware Bus Routing for Design Regularity.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Daeyeon Kim, SangGi Do, Sung-Yun Lee, Seokhyeong Kang
2019 — conf
Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic.
ISMVL
Sunmean Kim, Sung-Yun Lee, Sunghye Park, Seokhyeong Kang
2019 — conf
Ternary Logic Synthesis with Modified Quine-McCluskey Algorithm.
ISMVL
Sung-Yun Lee, Sunmean Kim, Seokhyeong Kang