Sung-Yong Cho

23 papers A 1C 1Journal 12Unranked 9
YearRankTypeTitle / Venue / Authors
2025 — conf
30.3 A 24Gb 42.5Gb/s GDDR7 DRAM with Low-Power WCK Distribution, an RC-Optimized Dual-Emphasis TX, and Voltage/Time-Margin-Enhanced Power Reduction.
ISSCC
Sang-Hoon Kim, Jaehyeok Baek, Moon-Chul Choi, Daewoong Lee, Donggun An, Se-Mi Kim, Yeonggeun Song, Minkyo Shim, Sung-Yong Cho, Dongha Lee, Gun-hee Cho, Inwoo Jun, Juseop Park, Taeyoon Lee, Hwan-Chul Jung, Chanyong Lee, Gil-Young Kang, Hye-Ran Kim, Jongmyung Lee, Young Su Joo, Hyo-jin Jung, Bokyeon Won, Ji-Hak Yu, Sangkeun Han, Yechan Hwang, Chungman Kim, Seok-Jung Kim, Youngseok Lee, Young-Tae Kim, Myeong-O. Kim, Wonhwa Shin, Tae-Young Oh, Sangjoon Hwang
2025 J jnl
A 16-Gb 37-Gb/s GDDR7 DRAM With PAM3-Optimized TRX Equalization and ZQ Calibration.
IEEE J. Solid State Circuits
Sung-Yong Cho, Moon-Chul Choi, Jaehyeok Baek, Donggun An, Sang-Hoon Kim, Daewoong Lee, Seongyeal Yang, Se-Mi Kim, Gil-Young Kang, Juseop Park, Kyung-Ho Lee, Hwan-Chul Jung, Gun-hee Cho, Chan-Yong Lee, Hye-Ran Kim, Yong-Jae Shin, Hanna Park, Sang-Yong Lee, Jonghyuk Kim, Bokyeon Won, Jungil Mok, Kijin Kim, Unhak Lim, Hongjun Jin, Youngseok Lee, Young-Tae Kim, Heonjoo Ha, Jinchan Ahn, Wonju Sung, Yoontaek Jang, Hoyoung Song, Hyodong Ban, Taehoon Park, Changsik Yoo, Tae-Young Oh, Sangjoon Hwang
2024 — conf
13.6 A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration.
ISSCC
Sung-Yong Cho, Moon-Chul Choi, Jaehyeok Baek, Donggun An, Sanghoon Kim, Daewoong Lee, Seongyeal Yang, Gil-Young Kang, Juseop Park, Kyungho Lee, Hwan-Chul Jung, Gun-hee Cho, Chanyong Lee, Hye-Ran Kim, Yong-Jae Shin, Hanna Park, Sangyong Lee, Jonghyuk Kim, Bokyeon Won, Jungil Mok, Kijin Kim, Unhak Lim, Hongjun Jin, Youngseok Lee, Young-Tae Kim, Heonjoo Ha, Jinchan Ahn, Wonju Sung, Yoontaek Jang, Hoyoung Song, Hyodong Ban, Taehoon Park, Tae-Young Oh, Changsik Yoo, Sangjoon Hwang
2024 J jnl
A PAM-4 Crosstalk Compensation Receiver Using an RC Circuit per Pin for 4×24 Gb/s/Pin Single-Ended DRAM Interface.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ho-Jun Kim, Sung-Yong Cho, Tae-Young Oh, Hong-June Park
2021 J jnl
A 4-20-Gb/s 1.87-pJ/b Continuous-Rate Digital CDR Circuit With Unlimited Frequency Acquisition Capability in 65-nm CMOS.
IEEE J. Solid State Circuits
Kwanseo Park, Kwangho Lee, Sung-Yong Cho, Jinhyung Lee, Jeongho Hwang, Min-Seong Choo, Deog-Kyoon Jeong
2021 J jnl
A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration.
IEEE J. Solid State Circuits
Min-Seong Choo, Sungwoo Kim, Han-Gon Ko, Sung-Yong Cho, Kwanseo Park, Jinhyung Lee, Soyeong Shin, Hankyu Chi, Deog-Kyoon Jeong
2019 J jnl
A 10-Gb/s, 0.03-mm
IEEE J. Solid State Circuits
Min-Seong Choo, Kwanseo Park, Han-Gon Ko, Sung-Yong Cho, Kwangho Lee, Deog-Kyoon Jeong
2019 J jnl
A 15-GHz, 17.8-mW, 213-fs Injection-Locked PLL With Maximized Injection Strength Using Adjustment of Phase Domain Response.
IEEE Trans. Circuits Syst. II Express Briefs
Min-Seong Choo, Yeonggeun Song, Sung-Yong Cho, Han-Gon Ko, Kwanseo Park, Deog-Kyoon Jeong
2019 J jnl
A 2.5-28 Gb/s Multi-Standard Transmitter With Two-Step Time-Multiplexing Driver.
IEEE Trans. Circuits Syst. II Express Briefs
Moon-Chul Choi, Deog-Kyoon Jeong, Sung-Yong Cho, Minkyo Shim, Byungmin Kim, Han-Gon Ko, Haram Ju, Kwanseo Park, Hyojun Kim, Kwandong Kim
2019 — conf
A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR With Unlimited Frequency Detection Capability in 65nm CMOS.
VLSI Circuits
Kwanseo Park, Kwangho Lee, Sung-Yong Cho, Jinhyung Lee, Jeongho Hwang, Min-Seong Choo, Deog-Kyoon Jeong
2018 — conf
A 10-Gb/s, 0.03-mm
A-SSCC
Min-Seong Choo, Han-Gon Ko, Sung-Yong Cho, Kwangho Lee, Deog-Kyoon Jeong
2018 J jnl
A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sung-Yong Cho, Sungwoo Kim, Min-Seong Choo, Han-Gon Ko, Jinhyung Lee, Woo-Rham Bae, Deog-Kyoon Jeong
2018 J jnl
An Optimum Injection-Timing Tracking Loop for 5-GHz, 1.13-mW/GHz RO-Based Injection-Locked PLL With 152-fs Integrated Jitter.
IEEE Trans. Circuits Syst. II Express Briefs
Min-Seong Choo, Han-Gon Ko, Sung-Yong Cho, Kwangho Lee, Deog-Kyoon Jeong
2017 — conf
29.7 A 2.5GHz injection-locked ADPLL with 197fsrms integrated jitter and -65dBc reference spur using time-division dual calibration.
ISSCC
Sungwoo Kim, Han-Gon Ko, Sung-Yong Cho, Jinhyung Lee, Soyeong Shin, Min-Seong Choo, Hankyu Chi, Deog-Kyoon Jeong
2016 J jnl
A 0.36 pJ/bit, 0.025 mm
IEEE Trans. Circuits Syst. I Regul. Pap.
Woo-Rham Bae, Gyu-Seob Jeong, Kwanseo Park, Sung-Yong Cho, Yoonsoo Kim, Deog-Kyoon Jeong
2016 J jnl
A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant- G
IEEE J. Solid State Circuits
Gyu-Seob Jeong, Sang-Hyeok Chu, Yoonsoo Kim, Sungchun Jang, Sungwoo Kim, Woo-Rham Bae, Sung-Yong Cho, Haram Ju, Deog-Kyoon Jeong
2016 J jnl
A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS.
IEEE J. Solid State Circuits
Woo-Rham Bae, Haram Ju, Kwanseo Park, Sung-Yong Cho, Deog-Kyoon Jeong
2016 C conf
A theoretical analysis of phase shift in pulse injection-locked oscillators.
ISCAS
Jinhyung Lee, Sungwoo Kim, Min-Seong Choo, Sung-Yong Cho, Han-Gon Ko, Deog-Kyoon Jeong
2015 — conf
A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm.
A-SSCC
Gyu-Seob Jeong, Sang-Hyeok Chu, Yoonsoo Kim, Sungchun Jang, Sungwoo Kim, Woo-Rham Bae, Sung-Yong Cho, Haram Ju, Deog-Kyoon Jeong
2015 — conf
A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection.
ESSCIRC
Sung-Yong Cho, Sungwoo Kim, Min-Seong Choo, Jinhyung Lee, Han-Gon Ko, Sungchun Jang, Sang-Hyeok Chu, Woo-Rham Bae, Yoonsoo Kim, Deog-Kyoon Jeong
2015 — conf
A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS.
A-SSCC
Woo-Rham Bae, Haram Ju, Kwanseo Park, Sung-Yong Cho, Deog-Kyoon Jeong
2014 — conf
A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line.
ESSCIRC
Woo-Rham Bae, Gyu-Seob Jeong, Kwanseo Park, Sung-Yong Cho, Yoonsoo Kim, Deog-Kyoon Jeong
2004 A conf
A new micro biological cell injection system.
IROS
Sung-Yong Cho, Jae-Hong Shim