Sung-Mo Kang

195 papers A* 18A 24B 1C 31Misc 2Journal 70Unranked 48
YearRankTypeTitle / Venue / Authors
2023 J jnl
Remote robotic system for 3D measurement of concrete damage in tunnel with ground vehicle and manipulator.
Comput. Aided Civ. Infrastructure Eng.
Seung-Bo Shim, Seong-Won Lee, Gye-Chun Cho, Jin Kim, Sung-Mo Kang
2019 J jnl
Distributed Orientation Estimation in SO(d) and Applications to Formation Control and Network Localization.
IEEE Trans. Control. Netw. Syst.
Byung-Hun Lee, Sung-Mo Kang, Hyo-Sung Ahn
2019 C conf
Real Time Image Processing System for Detecting Infrastructure Damage: Crack.
ICCE
Sung-Mo Kang, Chan-Jun Chun, Seung-Bo Shim, Seung-Ki Ryu, Jong-Dae Baek
2018 — conf
Disturbance Attenuation in Distance-Based Formation Control: A Linear Matrix Inequality Approach.
CCTA
Yoo-Bin Bae, Young-Hun Lim, Sung-Mo Kang, Hyo-Sung Ahn
2018 — conf
Shape and Orientation Control of Moving Formation with Local Measurements in Three-Dimensional Space.
CCTA
Sung-Mo Kang, Jae-Gyeong Lee, Hyo-Sung Ahn
2018 J jnl
Shape and orientation control of moving formation in multi-agent systems without global reference frame.
Autom.
Sung-Mo Kang, Hyo-Sung Ahn
2017 J jnl
Distance-Based Cycle-Free Persistent Formation: Global Convergence and Experimental Test With a Group of Quadcopters.
IEEE Trans. Ind. Electron.
Sung-Mo Kang, Myoung-Chul Park, Hyo-Sung Ahn
2017 — conf
Global convergence of formation without global information in three-dimensional space.
ASCC
Sung-Mo Kang, Jin-Hee Son, Hyo-Sung Ahn
2016 J jnl
Design and Realization of Distributed Adaptive Formation Control Law for Multi-Agent Systems With Moving Leader.
IEEE Trans. Ind. Electron.
Sung-Mo Kang, Hyo-Sung Ahn
2016 C conf
RRAM-based TCAMs for pattern search.
ISCAS
Le Zheng, Sangho Shin, G. Scott Lloyd, Maya B. Gokhale, Kyungmin Kim, Sung-Mo Kang
2014 — conf
21.3 A 2GHz 130mW direct-digital frequency synthesizer with a nonlinear DAC in 55nm CMOS.
ISSCC
Taegeun Yoo, Yun-Hwan Jung, Hong Chang Yeoh, Yong Sin Kim, Sung-Mo Kang, Kwang-Hyun Baek
2014 J jnl
A 2 GHz 130 mW Direct-Digital Frequency Synthesizer With a Nonlinear DAC in 55 nm CMOS.
IEEE J. Solid State Circuits
Taegeun Yoo, Hong Chang Yeoh, Yun-Hwan Jung, Seong Jin Cho, Yong Sin Kim, Sung-Mo Kang, Kwang-Hyun Baek
2014 C conf
Distance-based formation control with a single moving leader.
ACC
Sung-Mo Kang, Myoung-Chul Park, Byung-Hun Lee, Hyo-Sung Ahn
2014 J jnl
Power Blurring: Fast Static and Transient Thermal Analysis Method for Packaged Integrated Circuits and Power Devices.
IEEE Trans. Very Large Scale Integr. Syst.
Amirkoushyar Ziabari, Je-Hyoung Park, Ehsan K. Ardestani, Jose Renau, Sung-Mo Kang, Ali Shakouri
2013 J jnl
Resistive Computing: Memristors-Enabled Signal Multiplication.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sangho Shin, Kyungmin Kim, Sung-Mo Kang
2013 — conf
Sliding mode controller design for spacecraft with manipulator.
ASCC
Sung-Mo Kang, Yun-Tae Kim, Hyo-Sung Ahn
2012 J jnl
Analysis of Passive Memristive Devices Array: Data-Dependent Statistical Model and Self-Adaptable Sense Resistance for RRAMs.
Proc. IEEE
Sangho Shin, Kyungmin Kim, Sung-Mo Kang
2012 J jnl
Fast settling frequency synthesizer with two-point channel control paths.
Int. J. Circuit Theory Appl.
Sangho Shin, Sung-Mo Kang
2012 C conf
Maximizing power harvest in a distributed photovoltaic system.
ISCAS
Yong Sin Kim, Sung-Mo Kang, Roland Winston
2012 C conf
Memristive computing- multiplication and correlation.
ISCAS
Sangho Shin, Kyungmin Kim, Sung-Mo Kang
2012 J jnl
Memristors: Devices, Models, and Applications [Scanning the Issue].
Proc. IEEE
Pinaki Mazumder, Sung-Mo Kang, Rainer Waser
2011 C conf
Complementary structure of memristive devices based passive memory arrays.
ISCAS
Sangho Shin, Kyungmin Kim, Sung-Mo Kang
2011 J jnl
Field Programmable Stateful Logic Array.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kyosun Kim, Sangho Shin, Sung-Mo Kang
2011 J jnl
Oxide-Tunneling Leakage Suppressed SRAM for Sub-65-nm Very Large Scale Integrated Circuits.
J. Low Power Electron.
Ji-Hye Bong, Kwan-Hee Jo, Kyeong-Sik Min, Sung-Mo Kang
2011 J jnl
Reconfigurable Stateful nor Gate for Large-Scale Logic-Array Integrations.
IEEE Trans. Circuits Syst. II Express Briefs
Sangho Shin, Kyosun Kim, Sung-Mo Kang
2011 C conf
Stateful logic pipeline architecture.
ISCAS
Kyosun Kim, Sangho Shin, Sung-Mo Kang
2010 J jnl
Compact Models for Memristors Based on Charge-Flux Constitutive Relationships.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sangho Shin, Kyungmin Kim, Sung-Mo Kang
2010 J jnl
Data-Dependent Statistical Memory Model for Passive Array of Memristive Devices.
IEEE Trans. Circuits Syst. II Express Briefs
Sangho Shin, Kyungmin Kim, Sung-Mo Kang
2009 J jnl
A compact Verilog-A model for Multi-Level-Cell Phase-change RAMs.
IEICE Electron. Express
Kwan-Hee Jo, Ji-Hye Bong, Kyeong-Sik Min, Sung-Mo Kang
2009 — conf
New word-line driving scheme for suppressing oxide-tunneling leakage in sub-65-nm SRAMs.
ISQED
Ji-Hye Bong, Yong-jin Kwon, Kyeong-Sik Min, Sung-Mo Kang
2008 C conf
0.18um CMOS integrated chipset for 5.8GHz DSRC systems with +10dBm output power.
ISCAS
Sangho Shin, Seokoh Yun, Sanghyun Cho, Jongmoon Kim, Minseok Kang, Wonkab Oh, Sung-Mo Kang
2008 C conf
A 8-Gb/s/pin current mode multi-level simultaneous bidirectional I/O.
ISCAS
Yong Sin Kim, Sung-Mo Kang
2008 C conf
Design of a 6 bit 1.25 GS/s DAC for WPAN.
ISCAS
Jae-Jin Jung, Kwang-Hyun Baek, Shin-Il Lim, Suki Kim, Sung-Mo Kang
2008 — conf
Fast Evaluation Method for Transient Hot Spots in VLSI ICs in Packages.
ISQED
Je-Hyoung Park, Ali Shakouri, Sung-Mo Kang
2007 C conf
Analytical thermal placement for VLSI lifetime improvement and minimum performance variation.
ICCD
Andrew B. Kahng, Sung-Mo Kang, Wei Li, Bao Liu
2007 J jnl
Fast- Frequency Offset Cancellation Loop Using Low-IF Receiver and Fractional-N PLL.
IEEE Trans. Circuits Syst. II Express Briefs
Sangho Shin, Kyungmin Kim, Kwyro Lee, Sung-Mo Kang
2007 — conf
Programmable High Speed Multi-Level Simultaneous Bidirectional I/O.
ISQED
Yong Sin Kim, Sung-Mo Kang
2006 C conf
2.4GHz ZigBee radio architecture with fast frequency offset cancellation loop.
ISCAS
Sangho Shin, Kwyro Lee, Sung-Mo Kang
2006 C conf
A 4-Gb/s/pin current mode 4-level simultaneous bidirectional I/O with current mismatch calibration.
ISCAS
Yong Sin Kim, Sangho Shin, Sung-Mo Kang
2006 C conf
Low-power 2.4GHz CMOS frequency synthesizer with differentially controlled MOS varactors.
ISCAS
Sangho Shin, Kwyro Lee, Sung-Mo Kang
2006 J jnl
Temperature-Aware Placement for SOCs.
Proc. IEEE
Jeng-Liang Tsai, Charlie Chung-Ping Chen, Guoqiang Chen, Brent Goplen, Haifeng Qian, Yong Zhan, Sung-Mo Kang, Martin D. F. Wong, Sachin S. Sapatnekar
2005 — conf
3.48mW 2.4GHz range Frequency Synthesizer Architecture with Two-Point Channel Control for Fast Settling Performance.
SoCC
Sangho Shin, Kwyro Lee, Sung-Mo Kang
2005 J jnl
A 32-bit carry lookahead adder using dual-path all-N logic.
IEEE Trans. Very Large Scale Integr. Syst.
Ge Yang, Seong-Ook Jung, Kwang-Hyun Baek, Soo Hwan Kim, Suki Kim, Sung-Mo Kang
2005 — conf
Current mode multi-level simultaneous bidirectional I/O scheme for chip-to-chip communications.
ISCAS (6)
Ge Yang, Yong Sin Kim, Sung-Mo Kang
2004 J jnl
A CMOS self-regulating VCO with low supply sensitivity.
IEEE J. Solid State Circuits
In-Chul Hwang, Chulwoo Kim, Sung-Mo Kang
2004 — conf
A low-power 1.85 GHz 32-bit carry lookahead adder using Dual Path All-N-Logic.
ISCAS (2)
Ge Yang, Seong-Ook Jung, Kwang-Hyun Baek, Soo Hwan Kim, Suki Kim, Sung-Mo Kang
2004 J jnl
Design of ESD power protection with diode structures for mixed-power supply systems.
IEEE J. Solid State Circuits
Jaesik Lee, Yoonjong Huh, Peter Bendix, Sung-Mo Kang
2004 Misc conf
Leakage-Proof Domino Circuit Design for Deep Sub-100nm Technologies.
VLSI Design
Ge Yang, Zhongda Wang, Sung-Mo Kang
2004 — conf
Low Power and High Performance Circuit Techniques for High Fan-In Dynamic Gates.
ISQED
Ge Yang, Zhongda Wang, Sung-Mo Kang
2004 — conf
Message from the General Chair.
SoCC
Sung-Mo Kang
2003 — conf
1-GS/s, 12-bit SiGe BiCMOS D/A converter for high-speed DDFs.
ISCAS (1)
Kwang-Hyun Baek, Myung-Jun Choe, Edward Merlo, Sung-Mo Kang
2003 — conf
An Efficient Calibration Technique for Systematic Current-Mismatch of D/A Converters.
ISVLSI
Kwang-Hyun Baek, Myung-Jun Choe, Sung-Mo Kang
2003 J jnl
Chip-level charged-device modeling and simulation in CMOS integrated circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jaesik Lee, Ki-Wook Kim, Yoonjong Huh, Peter Bendix, Sung-Mo Kang
2003 A conf
Elements of low power design for integrated systems.
ISLPED
Sung-Mo Kang
2003 J jnl
Energy-efficient skewed static logic with dual Vt: design and synthesis.
IEEE Trans. Very Large Scale Integr. Syst.
Chulwoo Kim, Ki-Wook Kim, Sung-Mo Kang
2003 J jnl
Minimum delay optimization for domino circuits - a coupling-aware approach.
ACM Trans. Design Autom. Electr. Syst.
Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Sung-Mo Kang
2003 Misc conf
Multiple Trigonometric Approximation of Sine-Amplitude with Small ROM Size for Direct Digital Frequency Synthesizers.
VLSI Design
Yong Sin Kim, Soo Hwan Kim, Kwang-Hyun Baek, Suki Kim, Sung-Mo Kang
2003 J jnl
Noise-aware interconnect power optimization in domino logic synthesis.
IEEE Trans. Very Large Scale Integr. Syst.
Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang
2003 J jnl
Timing constraints for domino logic gates with timing-dependent keepers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
2002 J jnl
A low-power small-area ±7.28-ps-jitter 1-GHz DLL-based clock generator.
IEEE J. Solid State Circuits
Chulwoo Kim, In-Chul Hwang, Sung-Mo Kang
2002 J jnl
A low-swing clock double-edge triggered flip-flop.
IEEE J. Solid State Circuits
Chulwoo Kim, Sung-Mo Kang
2002 — conf
A low-voltage high-speed BiCMOS current switch with enhanced-spectral performance.
ISCAS (5)
Kwang-Hyun Baek, Myung-Jun Choe, Sung-Mo Kang
2002 — conf
Design limitations in deep sub-0.1µm CMOS SRAM.
ACM Great Lakes Symposium on VLSI
Robert K. Grube, Qi Wang, Sung-Mo Kang
2002 J jnl
Domino logic synthesis based on implication graph.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ki-Wook Kim, Taewhan Kim, C. L. Liu, Sung-Mo Kang
2002 A conf
Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constrain.
DATE
Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
2002 J jnl
Logic transformation for low-power synthesis.
ACM Trans. Design Autom. Electr. Syst.
Ki-Wook Kim, Taewhan Kim, TingTing Hwang, Sung-Mo Kang, C. L. Liu
2002 A* conf
Low-swing clock domino logic incorporating dual supply and dual threshold voltages.
DAC
Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
2002 J jnl
Noise constrained transistor sizing and power optimization for dual Vs
IEEE Trans. Very Large Scale Integr. Syst.
Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
2002 — conf
On-chip thermal engineering for peta-scale integration.
ISPD
Sung-Mo Kang
2002 — conf
Optimal Timing for Skew-Tolerant High-Speed Domino Logic.
ISVLSI
Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
2002 A* conf
VeriCDF: a new verification methodology for charged device failures.
DAC
Jaesik Lee, Ki-Wook Kim, Sung-Mo Kang
2001 — conf
2-level LFSR scheme with asynchronous test pattern transfer for low cost and high efficiency build-in-self-test.
ACM Great Lakes Symposium on VLSI
Seung-Moon Yoo, Seong-Ook Jung, Sung-Mo Kang
2001 — conf
A low-power reduced swing single clock flip-flop.
ISCAS (4)
Chulwoo Kim, Sung-Mo Kang
2001 A* conf
Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique.
DAC
Ki-Wook Kim, Seong-Ook Jung, Prashant Saxena, C. L. Liu, Sung-Mo Kang
2001 — conf
Coupling-aware minimum delay optimization for domino logic circuits.
ISCAS (5)
Ki-Wook Kim, Seong-Ook Jung, Sung-Mo Kang
2001 J jnl
Crosstalk noise minimization in domino logic design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ki-Wook Kim, Sung-Mo Kang
2001 — conf
Design-for-ESD-reliability for high-frequency I/O interface circuits in deep-submicron CMOS technology.
ISCAS (4)
Jaesik Lee, Yoonjong Huh, Peter Bendix, Sung-Mo Kang
2001 — conf
ESD design rule checker.
ISCAS (5)
Q. Li, Yoonjong Huh, Jau-Wen Chen, Peter Bendix, Sung-Mo Kang
2001 — conf
Effective algorithms for cache-level compression.
ACM Great Lakes Symposium on VLSI
Edward Ahn, Seung-Moon Yoo, Sung-Mo Kang
2001 — conf
Energy-efficient skewed static logic design with dual Vt.
ISCAS (4)
Chulwoo Kim, Ki-Wook Kim, Sung-Mo Kang
2001 — conf
Full chip ESD design rule checking.
ISCAS (5)
Q. Li, Yoonjong Huh, Jau-Wen Chen, Peter Bendix, Sung-Mo Kang
2001 J jnl
Interconnections-addressing the next challenge of IC technology (part I: integration and packaging trends).
Proc. IEEE
José E. Schutt-Ainé, Sung-Mo Kang
2001 — conf
Low cost and high efficiency BIST scheme with 2-level LFSR and ATPT.
ISCAS (4)
Seung-Moon Yoo, Seong-Ook Jung, Sung-Mo Kang
2001 — conf
Model-order reduction of nonlinear MEMS devices through arclength-based Karhunen-Loeve decomposition.
ISCAS (3)
Jinghong Chen, Sung-Mo Kang
2001 — conf
New current-mode sense amplifiers for high density DRAM and PIM architectures.
ISCAS (4)
Seung-Moon Yoo, Chulwoo Kim, Seong-Ook Jung, Kwang-Hyun Baek, Sung-Mo Kang
2001 — conf
Noise constrained power optimization for dual VT domino logic.
ISCAS (4)
Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
2001 — ed.
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, West Lafayette, Indiana, USA, 2001
ACM Great Lakes Symposium on VLSI
Kaushik Roy, Sung-Mo Kang, Cheng-Kok Koh
2001 J jnl
Scanning the issue interconnections - addressing the next challenge of IC technology (part II: design, characterization, and modeling).
Proc. IEEE
José E. Schutt-Ainé, Sung-Mo Kang
2001 — conf
Skew-tolerant high-speed (STHS) domino logic.
ISCAS (4)
Seong-Ook Jung, Seung-Moon Yoo, Ki-Wook Kim, Sung-Mo Kang
2001 — conf
Transistor sizing for reliable domino logic design in dual threshold voltage technologies.
ACM Great Lakes Symposium on VLSI
Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
2001 — conf
Trapezoid-to-simple polygon recomposition for resistance extraction.
ISCAS (5)
Q. Li, Sung-Mo Kang
2001 C conf
Understanding and Addressing the Noise Induced By Electrostatic Discharge in Multiple Power Supply Systems.
ICCD
Jaesik Lee, Yoonjong Huh, Peter Bendix, Sung-Mo Kang
2000 J jnl
A temperature-aware simulation environment for reliable ULSI chipdesign.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yi-Kan Cheng, Sung-Mo Kang
2000 C conf
An algorithm for automatic model-order reduction of nonlinear MEMS devices.
ISCAS
Jinghong Chen, Sung-Mo Kang
2000 J jnl
Cell-level placement for improving substrate thermal distribution.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ching-Han Tsai, Sung-Mo Kang
2000 B conf
Compensation modeling for QoS support on a wireless network.
GLOBECOM
Stefan Bucheli, Jay R. Moorman, John W. Lockwood, Sung-Mo Kang
2000 A conf
Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design.
ICCAD
Ki-Wook Kim, Kwang-Hyun Baek, Naresh R. Shanbhag, C. L. Liu, Sung-Mo Kang
2000 C conf
Detection and elimination of initial transient for accurate power analysis.
ISCAS
Li-Pen Yuan, Sung-Mo Kang
2000 A* conf
Domino logic synthesis minimizing crosstalk.
DAC
Ki-Wook Kim, Unni Narayanan, Sung-Mo Kang
2000 — conf
Efficient algorithms for polygon to trapezoid decomposition and trapezoid corner stitching.
ACM Great Lakes Symposium on VLSI
Qiao Li, Sung-Mo Kang
2000 A* conf
Fast temperature calculation for transient electrothermal simulation by mixed frequency/time domain thermal model reduction.
DAC
Ching-Han Tsai, Sung-Mo Kang
2000 C conf
High-Performance, Low-Power Skewed Static Logic in Very Deep-Submicron (VDSM) Technology.
ICCD
Chulwoo Kim, Jaesik Lee, Kwang-Hyun Baek, Eric Martina, Sung-Mo Kang
2000 J jnl
Interconnect thermal modeling for accurate simulation of circuittiming and reliability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Danqing Chen, Erhong Li, Elyse Rosenbaum, Sung-Mo Kang
2000 C conf
New high performance sub-1 V circuit technique with reduced standby current and robust data holding.
ISCAS
Seung-Moon Yoo, Sung-Mo Kang
2000 A conf
Noise-aware power optimization for on-chip interconnect.
ISLPED
Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang
2000 C conf
Parallel dynamic logic (PDL) with speed-enhanced skewed static (SSS) logic.
ISCAS
Chulwoo Kim, Seong-Ook Jung, Kwang-Hyun Baek, Sung-Mo Kang
2000 C conf
Real-time prioritized call admission control in a base station scheduler.
WOWMOM
Jay R. Moorman, John W. Lockwood, Sung-Mo Kang
2000 — conf
Technology independent arbitrary device extractor.
ACM Great Lakes Symposium on VLSI
Qiao Li, Sung-Mo Kang
2000 A* conf
When bad things happen to good chips (panel session).
DAC
N. S. Nagaraj, Andrzej J. Strojwas, Sani R. Nassif, Ray Hokinson, Tak Young, Wonjae L. Kang, David Overhauser, Sung-Mo Kang
1999 — conf
A mixed frequency-time approach for quasi-periodic steady-state simulation of multi-level modeled circuits.
ISCAS (6)
Jinghong Chen, Sung-Mo Kang
1999 A conf
An efficient method for hot-spot identification in ULSI circuits.
ICCAD
Yi-Kan Cheng, Sung-Mo Kang
1999 — conf
CMOS Pass-gate No-race Charge-recycling Logic (CPNCL).
ISCAS (1)
Seung-Moon Yoo, Sung-Mo Kang
1999 A conf
Implication graph based domino logic synthesis.
ICCAD
Ki-Wook Kim, C. L. Liu, Sung-Mo Kang
1999 — conf
Interconnect thermal modeling for determining design limits on current density.
ISPD
Danqing Chen, Erhong Li, Elyse Rosenbaum, Sung-Mo Kang
1999 A conf
Logic Transformation for Low Power Synthesis.
DATE
Ki-Wook Kim, Sung-Mo Kang, TingTing Hwang, C. L. Liu
1999 — conf
Macrocell placement with temperature profile optimization.
ISCAS (6)
Ching-Han Tsai, Sung-Mo Kang
1999 — conf
NMOS Energy Recovery Logic.
Great Lakes Symposium on VLSI
Chulwoo Kim, Seung-Moon Yoo, Sung-Mo Kang
1999 — conf
No-Race Charge-Recycling Differential Logic (NCDL).
Great Lakes Symposium on VLSI
Seung-Moon Yoo, Sung-Mo Kang
1999 J jnl
ServerNet and ATM interconnects: Comparison for compressed video transmission.
J. Commun. Networks
Ashfaq Hossain, Sung-Mo Kang, Robert Horst
1999 — conf
Standard cell placement for even on-chip thermal distribution.
ISPD
Ching-Han Tsai, Sung-Mo Kang
1999 A* conf
Substrate Modeling and Lumped Substrate Resistance Extraction for CMOS ESD/Latchup Circuit Simulation.
DAC
Tong Li, Ching-Han Tsai, Elyse Rosenbaum, Sung-Mo Kang
1999 — conf
Temperature-driven power and timing analysis for CMOS ULSI circuits.
ISCAS (6)
Yi-Kan Cheng, Sung-Mo Kang
1998 J jnl
A study of hot-carrier-induced mismatch drift: a reliability issue for VLSI circuits.
IEEE J. Solid State Circuits
Yoonjong Huh, Yungkwon Sung, Sung-Mo Kang
1998 A conf
Efficient transient electrothermal simulation of CMOS VLSI circuits under electrical overstress.
ICCAD
Tong Li, Ching-Han Tsai, Sung-Mo Kang
1998 J jnl
ILLIADS-T: an electrothermal timing simulator for temperature-sensitive reliability diagnosis of CMOS VLSI chips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yi-Kan Cheng, Prasun Raha, Chin-Chi Teng, Elyse Rosenbaum, Sung-Mo Kang
1998 A* conf
Layout Extraction and Verification Methodology CMOS I/O Circuits.
DAC
Tong Li, Sung-Mo Kang
1998 J jnl
Matrix unit cell scheduler (MUCS) for input-buffered ATM switches.
IEEE Commun. Lett.
Haoran Duan, John W. Lockwood, Sung-Mo Kang
1998 J jnl
Statistical estimation of average power dissipation using nonparametric techniques.
IEEE Trans. Very Large Scale Integr. Syst.
Li-Pen Yuan, Chin-Chi Teng, Sung-Mo Kang
1997 A* conf
A High-Performance OC-12/OC-48 Queue Design Prototype for Input-buffered ATM Switches.
INFOCOM
Haoran Duan, John W. Lockwood, Sung-Mo Kang, J. D. Will
1997 A conf
A sequential procedure for average power analysis of sequential circuits.
ISLPED
Li-Pen Yuan, Sung-Mo Kang
1997 A* conf
An Efficient Transistor Folding Algorithm for Row-Based CMOS Layout Design.
DAC
Jaewon Kim, Sung-Mo Kang
1997 J jnl
Computer Modeling and Simulation of the Optoelectronic Technology Consortium (OETC) Optical Bus.
IEEE J. Sel. Areas Commun.
Brent K. Whitlock, Petar K. Pepeljugoski, Daniel M. Kuchta, John D. Crow, Sung-Mo Kang
1997 — conf
Data Link Level Support for Handoff in Wireless ATM Network.
ICC (2)
Sueng-Yong Park, Vaduvur Bharghavan, Sung-Mo Kang
1997 — conf
Performance Comparison of Video Transport over ATM and ServerNet Interconnects.
ICMCS
Ashfaq Hossain, Sung-Mo Kang, Bob Horst
1997 A* conf
Statistical Estimation of Average Power Dissipation in Sequential Circuits.
DAC
Li-Pen Yuan, Chin-Chi Teng, Sung-Mo Kang
1997 J jnl
iTEM: a temperature-dependent electromigration reliability diagnosis tool.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chin-Chi Teng, Yi-Kan Cheng, Elyse Rosenbaum, Sung-Mo Kang
1996 J jnl
A new triple-layer OTC channel router.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jaewon Kim, Sung-Mo Kang
1996 J jnl
Determining accuracy bounds for simulation-based switching activity estimation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Anthony M. Hill, Sung-Mo Kang
1996 — conf
ETS-A: A New Electrothermal Simulator for CMOS VLSI Circuits.
ED&TC
Yi-Kan Cheng, Elyse Rosenbaum, Sung-Mo Kang
1996 A* conf
Hierarchical Electromigration Reliability Diagnosis for VLSI Interconnects.
DAC
Chin-Chi Teng, Yi-Kan Cheng, Elyse Rosenbaum, Sung-Mo Kang
1996 A conf
Statistical estimation of average power dissipation in CMOS VLSI circuits using nonparametric techniques.
ISLPED
Li-Pen Yuan, Chin-Chi Teng, Sung-Mo Kang
1996 A* conf
iCET: A Complete Chip-Level Thermal Reliability Diagnosis Tool for CMOS VLSI Chips.
DAC
Yi-Kan Cheng, Chin-Chi Teng, Abhijit Dharchoudhury, Elyse Rosenbaum, Sung-Mo Kang
1995 A conf
A timing-driven data path layout synthesis with integer programming.
ICCAD
Jaewon Kim, Sung-Mo Kang
1995 C conf
An Analytic Method to Calculate Emitter Follower Delay Using Trial Functions in Coupled Node Equations.
ISCAS
Elizabeth J. Brauer, Sung-Mo Kang
1995 J jnl
An algorithm for functional verification of digital ECL circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Elizabeth J. Brauer, Sung-Mo Kang
1995 A conf
An empirical model for accurate estimation of routing delay in FPGAs.
ICCAD
Tanay Karnik, Sung-Mo Kang
1995 C conf
Chip-Level Thermal Simulator to Predict VLSI Chip Temperature.
ISCAS
Yi-Kan Cheng, Sung-Mo Kang
1995 — conf
Determining accuracy bounds for simulation-based switching activity estimation.
ISLPD
Anthony M. Hill, Sung-Mo Kang
1995 J jnl
Efficient approximation of the time domain response of lossy coupled transmission line trees.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mysore Sriram, Sung-Mo Kang
1995 C conf
Estimating Node Voltages in Bipolar Circuits Using Linear Programming.
ISCAS
Elizabeth J. Brauer, Sung-Mo Kang
1995 A conf
Estimation of maximum transition counts at internal nodes in CMOS VLSI circuits.
ICCAD
Chin-Chi Teng, Anthony M. Hill, Sung-Mo Kang
1995 C conf
Incremental Node Extraction Algorithms for Incremental Layout System.
ISCAS
Myong H. Cynn, Sung-Mo Kang
1995 J jnl
Worst-case analysis and optimization of VLSI circuit performances.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Abhijit Dharchoudhury, Sung-Mo Kang
1994 J jnl
Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Carlos H. Díaz, Sung-Mo Kang, Charvaka Duvvury
1994 J jnl
Convexity-based algorithms for design centering.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sachin S. Sapatnekar, Pravin M. Vaidya, Sung-Mo Kang
1994 A conf
Fast and accurate timing simulation with regionwise quadratic models of MOS I-V characteristics.
ICCAD
Abhijit Dharchoudhury, Sung-Mo Kang, K. H. (Kane) Kim, S. H. Lee
1994 A conf
Fast timing simulation of transient faults in digital circuits.
ICCAD
Abhijit Dharchoudhury, Sung-Mo Kang, Hungse Cha, Janak H. Patel
1994 C conf
Forum: From 100 Milliwatts/MIPS to 10 Microwatts/MIPS.
ISCAS
Eby G. Friedman, Sung-Mo Kang, Eric A. Vittoz, David J. Allstot, Erik P. Harris, Ran-Hong Yan
1994 A conf
Genetic Algorithm Based Design Optimization Of CMOS VLSI Circuits.
PPSN
Anthony M. Hill, Sung-Mo Kang
1994 C conf
High Performance CMOS Macromodule Layout Synthesis.
ISCAS
Jaewon Kim, Sung-Mo Kang, Sachin S. Sapatnekar
1993 J jnl
An exact solution to the transistor sizing problem for CMOS circuits using convex optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya, Sung-Mo Kang
1993 A* conf
Fast Approximation of the Transient Response of Lossy Transmision Line Trees.
DAC
Mysore Sriram, Sung-Mo Kang
1993 C conf
Feasible Region Approximation Using Convex Polytopes.
ISCAS
Sachin S. Sapatnekar, Pravin M. Vaidya, Sung-Mo Kang
1993 C conf
Functional Verification of ECL Circuits Including Voltage Regulators.
ISCAS
Elizabeth J. Brauer, Sung-Mo Kang
1993 J jnl
High-Performance MCM Routing.
IEEE Des. Test Comput.
Jun Dong Cho, Majid Sarrafzadeh, Mysore Sriram, Sung-Mo Kang
1993 J jnl
ILLIADS: a fast timing and reliability simulator for digital MOS circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yung-Ho Shih, Yusuf Leblebici, Sung-Mo Kang
1993 J jnl
Modeling and simulation of hot-carrier-induced device degradation in MOS circuits.
IEEE J. Solid State Circuits
Yusuf Leblebici, Sung-Mo Kang
1993 A* conf
Performance-Constrained Worst-Case Variability Minimization of VLSI Circuits.
DAC
Abhijit Dharchoudhury, Sung-Mo Kang
1993 C conf
Thermal Failure Simulation for Electrical Overstress in Semiconductor Devices.
ISCAS
Carlos H. Díaz, Charvaka Duvvury, Sung-Mo Kang
1992 J jnl
A new design of a fast barrel switch network.
IEEE J. Solid State Circuits
G. M. Tharakan, Sung-Mo Kang
1992 J jnl
A new global router using zero-one integer linear programming techniques for sea-of-gates and custom logic arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Richard W. Thaik, Ngee Lek, Sung-Mo Kang
1992 A* conf
An Integrated Approach to Realistic Worst-Case Design Optimization of MOS Analog Circuits.
DAC
Abhijit Dharchoudhury, Sung-Mo Kang
1992 J jnl
Analytic transient solution of general MOS circuit primitives.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yung-Ho Shih, Sung-Mo Kang
1992 A conf
Detailed layer assignment for MCM routing.
ICCAD
Mysore Sriram, Sung-Mo Kang
1992 J jnl
Modeling of nMOS transistors for simulation of hot-carrier-induced device and circuit degradation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yusuf Leblebici, Sung-Mo Kang
1992 J jnl
New algorithms for circuit simulation of device breakdown.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Carlos H. Díaz, Sung-Mo Kang
1991 J jnl
A new circuit optimization technique for high performance CMOS circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
H. Y. Chen, Sung-Mo Kang
1991 J jnl
An accurate analytical delay model for BiCMOS driver circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Carlos H. Díaz, Sung-Mo Kang, Yusuf Leblebici
1991 A* conf
ILLIADS: A New Fast MOS Timing Simulator Using Direct Equation-Solving Approach.
DAC
Yung-Ho Shih, Sung-Mo Kang
1991 A conf
New Simulation Methods for MOS VLSI Timing and Reliability.
ICCAD
Yung-Ho Shih, Yusuf Leblebici, Sung-Mo Kang
1991 J jnl
Parametric yield optimization of CMOS analogue circuits by quadratic statistical circuit performance models.
Int. J. Circuit Theory Appl.
Tat-Kwan Yu, Sung-Mo Kang, Jerome Sacks, William J. Welch
1991 J jnl
iCOACH: A circuit optimization aid for CMOS high-performance circuits.
Integr.
H. Y. Chen, Sung-Mo Kang
1990 J jnl
A global delay model for domino cmos circuits with application to transistor sizing.
Int. J. Circuit Theory Appl.
Sung-Mo Kang, H. Y. Chen
1990 A conf
An Integrated Hot-Carrier Degradation Simulator for VLSI Reliability Analysis.
ICCAD
Yusuf Leblebici, Sung-Mo Kang
1989 A conf
A custom cell generation system for double-metal CMOS technology.
ICCAD
P. Gee, Ibrahim N. Hajj, Sung-Mo Kang
1989 A conf
An efficient method for parametric yield optimization of MOS integrated circuits.
ICCAD
Tat-Kwan Yu, Sung-Mo Kang, Jerome Sacks, William J. Welch
1989 C conf
Simulation of MOS circuit performance degradation with emphasis on VLSI design-for-reliability.
ICCD
Yusuf Leblebici, Sung-Mo Kang
1988 A conf
An efficient method for circuit sensitivity calculation using piecewise linear waveform models.
ICCAD
Sung-Mo Kang, Yusuf Leblebici
1988 A conf
iCOACH: a circuit optimization aid for CMOS high-performance circuits.
ICCAD
H. Y. Chen, Sung-Mo Kang
1988 A conf
iEDISON: an interactive statistical design tool for MOS VLSI circuits.
ICCAD
Tat-Kwan Yu, Sung-Mo Kang, Ibrahim N. Hajj, Timothy N. Trick
1987 J jnl
An Efficient Approach to Gate Matrix Layout.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
D. K. Hwang, W. Kent Fuchs, Sung-Mo Kang
1987 J jnl
Metal--Metal Matrix (M
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sung-Mo Kang
1987 J jnl
Statistical Performance Modeling and Parametric Yield Estimation of MOS VLSI.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tat-Kwan Yu, Sung-Mo Kang, I. N. Haji, Timothy N. Trick
1983 J jnl
Gate Matrix Layout of Random Control Logic in a 32-bit CMOS CPU Chip Adaptable to Evolving Logic Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sung-Mo Kang, Robert H. Krambeck, Hung-Fai Stephen Law, Alexander D. Lopez
1982 A* conf
Gate matrix layout of random control logic in a 32-bit CMOS CPU chip adaptable to evolving logic design.
DAC
Sung-Mo Kang, Robert H. Krambeck, Hung-Fai Stephen Law