Sung-En Hsieh

13 papers C 2Journal 4Unranked 7
YearRankTypeTitle / Venue / Authors
2023 — conf
A 1.8GHz 12b Pre-Sampling Pipelined ADC with Reference Buffer and OP Power Relaxations.
ISSCC
Sung-En Hsieh, Tzu-Chien Wu, Chun-Chih Hou
2023 — conf
A 70.85-86.27TOPS/W PVT-Insensitive 8b Word-Wise ACIM with Post-Processing Relaxation.
ISSCC
Sung-En Hsieh, Chun-Hao Wei, Cheng-Xin Xue, Hung-Wei Lin, Wei-Hsuan Tu, En-Jui Chang, Kai-Taing Yang, Po-Heng Chen, Wei-Nan Liao, Li Lian Low, Chia-Da Lee, Allen-Cl Lu, Jenwei Liang, Chih-Chung Cheng, Tzung-Hung Kang
2019 J jnl
A 0.4-V 13-bit 270-kS/s SAR-ISDM ADC With Opamp-Less Time-Domain Integrator.
IEEE J. Solid State Circuits
Sung-En Hsieh, Chih-Cheng Hsieh
2018 J jnl
A 0.44-fJ/Conversion-Step 11-Bit 600-kS/s SAR ADC With Semi-Resting DAC.
IEEE J. Solid State Circuits
Sung-En Hsieh, Chih-Cheng Hsieh
2018 — conf
A 0.4V 13b 270kS/S SAR-ISDM ADC with an opamp-less time-domain integrator.
ISSCC
Sung-En Hsieh, Chih-Cheng Hsieh
2018 J jnl
A 0.5-V 12-bit SAR ADC Using Adaptive Time-Domain Comparator With Noise Optimization.
IEEE J. Solid State Circuits
Sung-En Hsieh, Chen-Che Kao, Chih-Cheng Hsieh
2018 — conf
A CMOS Imager for Reflective Pulse Oximeter with Motion Artifact and Ambient Interference Rejections.
A-SSCC
Hsiang-Lin Chen, Sung-En Hsieh, Tzu-Hsiang Hsu, Chih-Cheng Hsieh
2017 — conf
A 0.5 V 12-bit SAR ADC using adaptive timedomain comparator with noise optimization.
A-SSCC
Chen-Che Kao, Sung-En Hsieh, Chih-Cheng Hsieh
2016 J jnl
A 0.3-V 0.705-fJ/Conversion-Step 10-bit SAR ADC With a Shifted Monotonic Switching Procedure in 90-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Sung-En Hsieh, Chih-Cheng Hsieh
2016 C conf
A 0.3V 0.705fJ/conversion-step 10-bit SAR ADC with shifted monotonie switching scheme in 90nm CMOS.
ISCAS
Sung-En Hsieh, Chih-Cheng Hsieh
2016 — conf
A 0.44fJ/conversion-step 11b 600KS/s SAR ADC with semi-resting DAC.
VLSI Circuits
Sung-En Hsieh, Chih-Cheng Hsieh
2016 — conf
An integrated CMOS optical sensing chip for multiple bio-signal detections.
A-SSCC
Albert Yen-Chih Chiou, Sung-En Hsieh, Yan-Quan Pan, Chia-Chi Kuo, Chih-Cheng Hsieh
2015 C conf
A 1.2V 1MS/s 7.65fJ/conversion-step 12-bit hybrid SAR ADC with time-to-digital converter.
ISCAS
Sung-En Hsieh, Cheng-Kang Ho, Chih-Cheng Hsieh