Sunan Zou

11 papers A* 1A 2C 1Journal 5Unranked 2
YearRankTypeTitle / Venue / Authors
2025 J jnl
UltraSketchLLM: Saliency-Driven Sketching for Ultra-Low Bit LLM Compression.
CoRR
Sunan Zou, Ziyun Zhang, Xueting Sun, Guojie Luo
2024 A conf
AceRoute: Adaptive Compute-Efficient FPGA Routing with Pluggable Intra-Connection Bidirectional Exploration.
ICCAD
Xinming Wei, Ziyun Zhang, Sunan Zou, Kaiwen Sun, Jiahao Zhang, Jiaxi Zhang, Ping Fan, Guojie Luo
2024 A conf
BESWAC: Boosting Exact Synthesis via Wiser SAT Solver Call.
DATE
Sunan Zou, Jiaxi Zhang, Bizhao Shi, Guojie Luo
2024 J jnl
Erratum to: Large circuit models: opportunities and challenges.
Sci. China Inf. Sci.
Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Ru Huang, Yu Huang, Sadaf Khan, Min Li, Xingquan Li, Yu Li, Yun Liang, Jinwei Liu, Yi Liu, Yibo Lin, Guojie Luo, Hongyang Pan, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Junchi Yan, Jun Yang, Bei Yu, Mingxuan Yuan, Evangeline F. Y. Young, Xuan Zeng, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou
2024 — conf
ImageMap: Enabling Efficient Mapping from Image Processing DSL to CGRA.
Euro-Par (1)
Bizhao Shi, Tuo Dai, Sunan Zou, Xinming Wei, Guojie Luo
2024 — conf
Incremental SAT-based Exact Synthesis.
ACM Great Lakes Symposium on VLSI
Sunan Zou, Jiaxi Zhang, Guojie Luo
2024 J jnl
Large circuit models: opportunities and challenges.
Sci. China Inf. Sci.
Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Ru Huang, Yu Huang, Sadaf Khan, Min Li, Xingquan Li, Yu Li, Yun Liang, Jinwei Liu, Yi Liu, Yibo Lin, Guojie Luo, Hongyang Pan, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Junchi Yan, Jun Yang, Bei Yu, Mingxuan Yuan, Evangeline F. Y. Young, Xuan Zeng, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou
2024 C conf
MuSA: Multi-Sketch Accelerator with Hybrid Parallelism and Coalesced Memory Organization.
ICCD
Sunan Zou, Bizhao Shi, Ziyun Zhang, Guojie Luo
2024 A* conf
PONO: Power Optimization with Near Optimal SMT-based Sub-circuit Generation.
DAC
Sunan Zou, Guojie Luo
2024 J jnl
PowerSyn: A Logic Synthesis Framework With Early Power Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sunan Zou, Jiaxi Zhang, Bizhao Shi, Guojie Luo
2024 J jnl
The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models.
CoRR
Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Yu Huang, Sadaf Khan, Min Li, Xingquan Li, Yun Liang, Yibo Lin, Jinwei Liu, Yi Liu, Guojie Luo, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Evangeline F. Y. Young, Bei Yu, Mingxuan Yuan, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou