Sumanta Chaudhuri

42 papers A* 3A 3B 5Journal 15Unranked 16

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Defeating AutoLock: From Simulation to Real-World Cache-Timing Exploits against TrustZone. IACR Cryptol. ePrint Arch. Quentin Forcioli, Sumanta Chaudhuri, Jean-Luc Danger
2025	J	`jnl`	Efficient Learned Image Compression Through Knowledge Distillation. CoRR Fabien Allemand, Attilio Fiandrotti, Sumanta Chaudhuri, Alaa Eddine Mazouz
2025	J	`jnl`	Lightweight Embedded FPGA Deployment of Learned Image Compression with Knowledge Distillation and Hybrid Quantization. CoRR Alaa Mazouz, Sumanta Chaudhuri, Marco Cagnazzo, Mihai Mitrea, Enzo Tartaglione, Attilio Fiandrotti
2025	J	`jnl`	Security and Real-time FPGA integration for Learned Image Compression. CoRR Alaa Mazouz, Carl De Sousa Trias, Sumanta Chaudhuri, Attilio Fiandrotti, Marco Cagnazzo, Mihai Mitrea, Enzo Tartaglione
2024	A*	`conf`	Find the Lady: Permutation and Re-synchronization of Deep Neural Networks. AAAI Carl De Sousa Trias, Mihai Petru Mitrea, Attilio Fiandrotti, Marco Cagnazzo, Sumanta Chaudhuri, Enzo Tartaglione
2024	—	`conf`	TEE-Time: A Dynamic Cache Timing Analysis Tool for Trusted Execution Environments. ISQED Quentin Forcioli, Sumanta Chaudhuri, Jean-Luc Danger
2024	—	`conf`	WaterMAS: Sharpness-Aware Maximization for Neural Network Watermarking. ICPR (5) Carl De Sousa Trias, Mihai Mitrea, Attilio Fiandrotti, Marco Cagnazzo, Sumanta Chaudhuri, Enzo Tartaglione
2024	J	`jnl`	WaterMAS: Sharpness-Aware Maximization for Neural Network Watermarking. CoRR Carl De Sousa Trias, Mihai Mitrea, Attilio Fiandrotti, Marco Cagnazzo, Sumanta Chaudhuri, Enzo Tartaglione
2023	—	`conf`	A Hitchhiker's Guide to White-Box Neural Network Watermarking Robustness. EUVIP Carl De Sousa Trias, Mihai Mitrea, Enzo Tartaglione, Attilio Fiandrotti, Marco Cagnazzo, Sumanta Chaudhuri
2023	—	`conf`	A gem5 based Platform for Micro-Architectural Security Analysis. HASP@MICRO Quentin Forcioli, Jean-Luc Danger, Sumanta Chaudhuri
2023	J	`jnl`	Find the Lady: Permutation and Re-Synchronization of Deep Neural Networks. CoRR Carl De Sousa Trias, Mihai Petru Mitrea, Attilio Fiandrotti, Marco Cagnazzo, Sumanta Chaudhuri, Enzo Tartaglione
2022	B	`conf`	Minconvnets: a New Class of Multiplication-Less Neural Networks. ICIP Xuecan Yang, Sumanta Chaudhuri, Laurence Likforman, Lirida A. B. Naviner
2021	J	`jnl`	MinConvNets: A new class of multiplication-less Neural Networks. CoRR Xuecan Yang, Sumanta Chaudhuri, Laurence Likforman, Lirida A. B. Naviner
2020	—	`conf`	Quad-Approx CNNs for Embedded Object Detection Systems. ICECS Xuecan Yang, Sumanta Chaudhuri, Lirida A. B. Naviner, Laurence Likforman
2018	A*	`conf`	A security vulnerability analysis of SoCFPGA architectures. DAC Sumanta Chaudhuri
2018	—	`conf`	Beyond Bits: A Quaternary FPGA Architecture Using Multi-Vt Multi-Vdd FDSOI Devices. ISMVL Sumanta Chaudhuri
2017	A	`conf`	Cache Timing Attacks from The SoCFPGA Coherency Port (Abstract Only). FPGA Sumanta Chaudhuri
2016	J	`jnl`	Multi-Valued Routing Tracks for FPGAs in 28nm FDSOI Technology. CoRR Sumanta Chaudhuri, Tarik Graba, Yves Mathieu
2014	J	`jnl`	Classification on variation maps: a new placement strategy to alleviate process variation on FPGA. IEICE Electron. Express Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung
2014	J	`jnl`	Mitigation of process variation effect in FPGAs with partial rerouting method. IEICE Electron. Express Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung
2013	B	`conf`	A variation-adaptive retiming method exploiting reconfigurability. FPL Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung
2013	—	`conf`	Exploiting stochastic delay variability on FPGAs with adaptive partial rerouting. FPT Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung
2012	B	`conf`	A two-stage variation-aware placement method for FPGAS exploiting variation maps classification. FPL Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung
2012	J	`jnl`	Cross-point architecture for spin transfer torque magnetic random access memory CoRR Weisheng Zhao, Sumanta Chaudhuri, Celso Accoto, Jacques-Olivier Klein, Claude Chappert, Pascale Mazoyer
2011	J	`jnl`	A Secure Asynchronous FPGA Architecture, Experimental Results and Some Debug Feedback CoRR Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin
2011	J	`jnl`	Side-Channel Oscilloscope CoRR Sumanta Chaudhuri, Sylvain Guilley
2011	—	`conf`	Timing speculation in FPGAs: Probabilistic inference of data dependent failure rates. FPT Sumanta Chaudhuri, Justin S. J. Wong, Peter Y. K. Cheung
2010	—	`conf`	Design of embedded MRAM macros for memory-in-logic applications. ACM Great Lakes Symposium on VLSI Sumanta Chaudhuri, Weisheng Zhao, Jacques-Olivier Klein, Claude Chappert, Pascale Mazoyer
2010	B	`conf`	High Density Asynchronous LUT Based on Non-volatile MRAM Technology. FPL Sumanta Chaudhuri, Weisheng Zhao, Jacques-Olivier Klein, Claude Chappert, Pascale Mazoyer
2009	A	`conf`	Diagonal tracks in FPGAs: a performance evaluation. FPGA Sumanta Chaudhuri
2009	—	`conf`	Updates on the potential of clock-less logics to strengthen cryptographic circuits against side-channel attacks. ICECS Sylvain Guilley, Sumanta Chaudhuri, Laurent Sauvage, Jean-Luc Danger, Taha Beyrouthy, Laurent Fesquet
2008	J	`jnl`	A Reconfigurable Programmable Logic Block for a Multi-Style Asynchronous FPGA resistant to Side-Channel Attacks CoRR Philippe Hoogvorst, Sylvain Guilley, Sumanta Chaudhuri, Jean-Luc Danger, Taha Beyrouthy, Laurent Fesquet
2008	A*	`conf`	An 8x8 run-time reconfigurable FPGA embedded in a SoC. DAC Sumanta Chaudhuri, Sylvain Guilley, Florent Flament, Philippe Hoogvorst, Jean-Luc Danger
2008	A	`conf`	Efficient tiling patterns for reconfigurable gate arrays. FPGA Sumanta Chaudhuri, Jean-Luc Danger, Philippe Hoogvorst, Sylvain Guilley
2008	—	`conf`	Efficient tiling patterns for reconfigurable gate arrays. SLIP Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger
2008	—	`conf`	Physical Design of FPGA Interconnect to Prevent Information Leakage. ARC Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin
2008	—	`conf`	Place-and-Route Impact on the Security of DPL Designs in FPGAs. HOST Sylvain Guilley, Sumanta Chaudhuri, Jean-Luc Danger, Laurent Sauvage, Philippe Hoogvorst, Maxime Nassar, Tarik Graba, Vinh-Nga Vong
2008	J	`jnl`	Security Evaluation of WDDL and SecLib Countermeasures against Power Attacks. IEEE Trans. Computers Sylvain Guilley, Laurent Sauvage, Philippe Hoogvorst, Renaud Pacalet, Guido Marco Bertoni, Sumanta Chaudhuri
2007	—	`conf`	A Novel Asynchronous e-FPGA Architecture for Security Applications. FPT Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin, Sumanta Chaudhuri, Sylvain Guilley, Jean-Luc Danger, Philippe Hoogvorst
2007	—	`conf`	A Reconfigurable Cell for a Multi-Style Asynchronous FPGA. ReCoSoC Philippe Hoogvorst, Sylvain Guilley, Sumanta Chaudhuri, Alin Razafindraibe, Taha Beyrouthy, Laurent Fesquet
2007	B	`conf`	Efficient Modeling and Floorplanning of Embedded-FPGA Fabric. FPL Sumanta Chaudhuri, Jean-Luc Danger, Sylvain Guilley
2006	—	`conf`	FASE: An Open Run-Time Reconfigurable FPGA Architecture for Tamper-Resistant and Secure Embedded Systems. ReConFig Sumanta Chaudhuri, Jean-Luc Danger, Sylvain Guilley, Philippe Hoogvorst