Suman Sau - RankMe

18 papers C 1Journal 12Unranked 5

Year	Rank	Type	Title / Venue / Authors
2021	J	`jnl`	Blockchain based secure smart city architecture using low resource IoTs. Comput. Networks Rourab Paul, Nimisha Ghosh, Suman Sau, Amlan Chakrabarti, Prasant Mohapatra
2021	J	`jnl`	Voltage Scaling for Partitioned Systolic Array in A Reconfigurable Platform. CoRR Rourab Paul, Sreetama Sarkar, Suman Sau, Koushik Chakraborty, Sanghamitra Roy, Amlan Chakrabarti
2019	J	`jnl`	IoT based Smart Access Controlled Secure Smart City Architecture Using Blockchain. CoRR Rourab Paul, Nimisha Ghosh, Suman Sau, Amlan Chakrabarti, Prasant Mahapatra
2018	C	`conf`	A New High Throughput and Area Efficient SHA-3 Implementation. ISCAS Ming Ming Wong, Jawad Haj-Yahya, Suman Sau, Anupam Chattopadhyay
2017	J	`jnl`	Efficient dynamic priority based soft error mitigation techniques for configuration memory of FPGA hardware. Microprocess. Microsystems Swagata Mandal, Rourab Paul, Suman Sau, Amlan Chakrabarti, Subhasis Chattopadhyay
2017	—	`conf`	Survey of secure processors. SAMOS Suman Sau, Jawad Haj-Yahya, Ming Ming Wong, Kwok-Yan Lam, Anupam Chattopadhyay
2016	J	`jnl`	A Novel Method for Soft Error Mitigation in FPGA Using Modified Matrix Code. IEEE Embed. Syst. Lett. Swagata Mandal, Rourab Paul, Suman Sau, Amlan Chakrabarti, Subhasis Chattopadhyay
2015	J	`jnl`	A Novel Method for Soft Error Mitigation in FPGA using Adaptive Cross Parity Code. CoRR Swagata Mandal, Rourab Paul, Suman Sau, Amlan Chakrabarti, Subhasis Chattopadhyay
2015	—	`conf`	FPGA Based Novel High Speed DAQ System Design with Error Correction. ISVLSI Swagata Mandal, Suman Sau, Amlan Chakrabarti, Jogendra Saini, Sushanta Kumar Pal, Subhasish Chattopadhyay
2015	—	`conf`	FPGA Implementation of High Speed Latency Optimized Optical Communication System Based on Orthogonal Concatenated Code. ATS Swagata Mandal, Suman Sau, Amlan Chakrabarti, Sushanta Kumar Pal, Subhasish Chattopadhyay
2015	J	`jnl`	FPGA based High Speed Data Acquisition System for High Energy Physics Application. CoRR Swagata Mandal, Suman Sau, Amlan Chakrabarti, Subhasis Chattopadhyay
2015	J	`jnl`	FPGA based Novel High Speed DAQ System Design with Error Correction. CoRR Swagata Mandal, Suman Sau, Amlan Chakrabarti, Jogendra Saini, Sushanta Kumar Pal, Subhasish Chattopadhyay
2015	J	`jnl`	High speed fault tolerant secure communication for muon chamber using fpga based gbt emulator. CoRR Suman Sau, Swagata Mandal, Jogender Saini, Amlan Chakrabarti, Subhasis Chattopadhyay
2012	J	`jnl`	A brief experience on journey through hardware developments for image processing and its applications on Cryptography CoRR Sangeet Saha, Chandrajit Pal, Rourab Paul, Satyabrata Maity, Suman Sau
2012	—	`conf`	A novel AES-256 implementation on FPGA using co-processor based architecture. ICACCI Suman Sau, Rourab Paul, Tanmay Biswas, Amlan Chakrabarti
2012	J	`jnl`	Architecture for real time continuous sorting on large width data volume for fpga based applications CoRR Rourab Paul, Suman Sau, Amlan Chakrabarti
2012	J	`jnl`	Design and implementation of real time AES-128 on real time operating system for multiple FPGA communication CoRR Rourab Paul, Sangeet Saha, Suman Sau, Amlan Chakrabarti
2011	—	`conf`	Design and implementation of real time secured RS232 link for multiple FPGA communication. ICCCS Suman Sau, Chandrajit Pal, Amlan Chakrabarti