Sujit Kumar Patel

18 papers Journal 17Unranked 1
YearRankTypeTitle / Venue / Authors
2026 J jnl
Chua-oscillator-driven modified RC4 stream cipher and its FPGA prototyping for secure communication.
Integr.
Navneet Sharma, Pravindra Kumar, Shireesh Kumar Rai, Sujit Kumar Patel
2024 J jnl
Design of Frequency Sampling Rational Rate Polyphase FIR Converter.
IEEE Trans. Circuits Syst. II Express Briefs
Konudula Anjali Rao, Abhishek Kumar, Sujit Kumar Patel, Dmitry I. Kaplun, Neetesh Purohit
2023 J jnl
An area-delay efficient single-precision floating-point multiplier for VLSI systems.
Microprocess. Microsystems
Anuradha, Sujit Kumar Patel, Subodh Kumar Singhal
2023 J jnl
Design of low complexity parallel polyphase finite impulse response filter using coefficient symmetry.
IET Circuits Devices Syst.
Konudula Anjali Rao, Abhishek Kumar, Dmitrii I. Kaplun, Sujit Kumar Patel, Neetesh Purohit
2021 J jnl
A novel design of current differencing transconductance amplifier with high transconductance gain and enhanced bandwidth.
Turkish J. Electr. Eng. Comput. Sci.
Shireesh Kumar Rai, Rishikesh Pandey, Bharat Garg, Sujit Kumar Patel
2021 J jnl
Area-delay efficient Radix-4 8×8 Booth multiplier for DSP applications.
Turkish J. Electr. Eng. Comput. Sci.
Subodh Kumar Singhal, Sujit Kumar Patel, Anurag Mahajan, Gaurav Saxena
2021 J jnl
Reconfigurable Carry Look-Ahead Adder Trading Accuracy for Energy Efficiency.
J. Signal Process. Syst.
Bharat Garg, Sujit Kumar Patel
2021 J jnl
Reconfigurable Rounding Based Approximate Multiplier for Energy Efficient Multimedia Applications.
Wirel. Pers. Commun.
Bharat Garg, Sujit Kumar Patel
2020 J jnl
A power and area efficient approximate carry skip adder for error resilient applications.
Turkish J. Electr. Eng. Comput. Sci.
Sujit Kumar Patel, Bharat Garg, Shireesh Kumar Rai
2020 J jnl
An Efficient Accuracy Reconfigurable CLA Adder Designs Using Complementary Logic.
J. Electron. Test.
Sujit Kumar Patel, Bharat Garg, Shireesh Kumar Rai
2020 J jnl
Area-delay and energy efficient multi-operand binary tree adder.
IET Circuits Devices Syst.
Sujit Kumar Patel, Subodh Kumar Singhal
2020 J jnl
Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix Adder.
J. Circuits Syst. Comput.
Subodh Kumar Singhal, Basant K. Mohanty, Sujit Kumar Patel, Gaurav Saxena
2020 J jnl
LoBA: A Leading One Bit Based Imprecise Multiplier for Efficient Image Processing.
J. Electron. Test.
Bharat Garg, Sujit Kumar Patel, Sunil Dutt
2019 — conf
Area-Delay Efficient and Low-Power Carry Skip Adder for High Performance Computing Systems.
iSES
Sujit Kumar Patel, Bharat Garg, Anurag Mahajan, Shireesh Kumar Rai
2016 J jnl
LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter.
IEEE Trans. Very Large Scale Integr. Syst.
Basant K. Mohanty, Pramod Kumar Meher, Sujit Kumar Patel
2015 J jnl
Efficient VLSI Architecture for Decimation-in-Time Fast Fourier Transform of Real-Valued Data.
IEEE Trans. Circuits Syst. I Regul. Pap.
Pramod Kumar Meher, Basant Kumar Mohanty, Sujit Kumar Patel, Soumya Ganguly, Thambipillai Srikanthan
2015 J jnl
Efficient very large-scale integration architecture for variable length block least mean square adaptive filter.
IET Signal Process.
Basant Kumar Mohanty, Sujit Kumar Patel
2014 J jnl
Area-Delay-Power Efficient Carry-Select Adder.
IEEE Trans. Circuits Syst. II Express Briefs
Basant Kumar Mohanty, Sujit Kumar Patel