Sujan Pandey - RankMe

18 papers A* 1A 2B 2C 7Journal 1Unranked 5

Year	Rank	Type	Title / Venue / Authors
2014	A	`conf`	Transient errors resiliency analysis technique for automotive safety critical applications. DATE Sujan Pandey, Bart Vermeulen
2012	C	`conf`	Soft-errors resilient logic optimization for low power. IOLTS Sujan Pandey, Klaas Brink
2008	C	`conf`	Process variations aware robust on-chip bus architecture synthesis for MPSoCs. ISCAS Sujan Pandey, Rolf Drechsler, Tudor Murgan, Manfred Glesner
2008	—	`conf`	Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival. ASP-DAC Sujan Pandey, Rolf Drechsler
2008	A	`conf`	Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs. DATE Sujan Pandey, Rolf Drechsler
2007	C	`conf`	Co-synthesis of custom on-chip bus and memory for MPSoC architectures. VLSI-SoC Sujan Pandey, Christian Genz, Rolf Drechsler
2007	—	`conf`	On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects. PATMOS Tudor Murgan, Petru Bogdan Bacinschi, Sujan Pandey, Alberto García Ortiz, Manfred Glesner
2007	J	`jnl`	Simultaneous On-Chip Bus Synthesis and Voltage Scaling Under Random On-Chip Data Traffic. IEEE Trans. Very Large Scale Integr. Syst. Sujan Pandey, Manfred Glesner
2006	C	`conf`	Energy Conscious Simultaneous Voltage Scaling and On-chip Communication Bus Synthesis. VLSI-SoC Sujan Pandey, Tudor Murgan, Manfred Glesner
2006	B	`conf`	Energy Efficient Statistical On-Chip Communication Bus Synthesis for a Reconfigurable Architecture. FPL Sujan Pandey, Manfred Glesner
2006	C	`conf`	Energy efficient MPSoC on-chip communication bus synthesis using voltage scaling technique. ISCAS Sujan Pandey, Manfred Glesner
2006	C	`conf`	Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters. VLSI-SoC Tudor Murgan, Oliver Mitea, Sujan Pandey, Petru Bogdan Bacinschi, Manfred Glesner
2006	A*	`conf`	Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint. DAC Sujan Pandey, Manfred Glesner
2006	C	`conf`	Tabu Search Based On-Chip Communication Bus Synthesis for Shared Multi-Bus Based Architecture. VLSI-SoC Sujan Pandey, Nurten Utlu, Manfred Glesner
2005	—	`conf`	Advanced On-Chip Communication Architectures and Routing Methods for Systems-on-Chip. ReCoSoC Thomas Hollstein, Sujan Pandey, Manfred Glesner
2005	—	`conf`	High level hardware/software communication estimation in shared memory architecture. ISCAS (1) Sujan Pandey, Heiko Zimmer, Manfred Glesner, Max Mühlhäuser
2005	B	`conf`	On-Chip Communication Topology Synthesis for a Shared Memory Architecture. FPL Sujan Pandey, Manfred Glesner, Max Mühlhäuser
2005	—	`conf`	Performance aware on-chip communication synthesis and optimization for shared multi-bus based architecture. SBCCI Sujan Pandey, Manfred Glesner, Max Mühlhäuser