Suhail Basalama

14 papers A* 1A 2B 1Misc 2Journal 5Unranked 3
YearRankTypeTitle / Venue / Authors
2026 — conf
FIFOAdvisor: A DSE Framework for Automated FIFO Sizing of High-Level Synthesis Designs.
ASP-DAC
Stefan Abi-Karam, Rishov Sarkar, Suhail Basalama, Jason Cong, Callie Hao
2025 J jnl
FIFOAdvisor: A DSE Framework for Automated FIFO Sizing of High-Level Synthesis Designs.
CoRR
Stefan Abi-Karam, Rishov Sarkar, Suhail Basalama, Jason Cong, Callie Hao
2025 Misc conf
NoH: NoC Compilation in High-Level Synthesis.
FCCM
Huifeng Ke, Sihao Liu, Licheng Guo, Zifan He, Linghao Song, Suhail Basalama, Yuze Chi, Tony Nowatzki, Jason Cong
2025 A conf
Stream-HLS: Towards Automatic Dataflow Acceleration.
FPGA
Suhail Basalama, Jason Cong
2025 J jnl
Stream-HLS: Towards Automatic Dataflow Acceleration.
CoRR
Suhail Basalama, Jason Cong
2024 — conf
TAPA-CS: Enabling Scalable Accelerator Design on Distributed HBM-FPGAs.
ASPLOS (3)
Neha Prakriya, Yuze Chi, Suhail Basalama, Linghao Song, Jason Cong
2023 A* conf
A Comprehensive Automated Exploration Framework for Systolic Array Designs.
DAC
Suhail Basalama, Jie Wang, Jason Cong
2023 A conf
Callipepla: Stream Centric Instruction Set and Mixed Precision for Accelerating Conjugate Gradient Solver.
FPGA
Linghao Song, Licheng Guo, Suhail Basalama, Yuze Chi, Robert F. Lucas, Jason Cong
2023 J jnl
FlexCNN: An End-to-end Framework for Composing CNN Accelerators on FPGA.
ACM Trans. Reconfigurable Technol. Syst.
Suhail Basalama, Atefeh Sohrabizadeh, Jie Wang, Licheng Guo, Jason Cong
2023 J jnl
TAPA-CS: Enabling Scalable Accelerator Design on Distributed HBM-FPGAs.
CoRR
Neha Prakriya, Yuze Chi, Suhail Basalama, Linghao Song, Jason Cong
2022 Misc conf
A Versatile Systolic Array for Transposed and Dilated Convolution on FPGA.
FCCM
Suhail Basalama, Atefeh Sohrabizadeh, Jie Wang, Jason Cong
2022 J jnl
Callipepla: Stream Centric Instruction Set and Mixed Precision for Accelerating Conjugate Gradient Solver.
CoRR
Linghao Song, Licheng Guo, Suhail Basalama, Yuze Chi, Robert F. Lucas, Jason Cong
2021 B conf
A Customizable Domain-Specific Memory-Centric FPGA Overlay for Machine Learning Applications.
FPL
Atiyehsadat Panahi, Suhail Basalama, Ange-Thierry Ishimwe, Joel Mandebi Mbongue, David Andrews
2020 — conf
SPAR-2: A SIMD Processor Array for Machine Learning in IoT Devices.
ICDIS
Suhail Basalama, Atiyehsadat Panahi, Ange-Thierry Ishimwe, David Andrews