Sudipta Bhawmik

30 papers A* 4A 4C 1Misc 5Journal 12Unranked 4
YearRankTypeTitle / Venue / Authors
2015 J jnl
Built-In Self-Test and Test Scheduling for Interposer-Based 2.5D IC.
ACM Trans. Design Autom. Electr. Syst.
Ran Wang, Krishnendu Chakrabarty, Sudipta Bhawmik
2015 J jnl
Interconnect Testing and Test-Path Scheduling for Interposer-Based 2.5-D ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ran Wang, Krishnendu Chakrabarty, Sudipta Bhawmik
2014 Misc conf
At-speed interconnect testing and test-path optimization for 2.5D ICs.
VTS
Ran Wang, Krishnendu Chakrabarty, Sudipta Bhawmik
2014 C conf
Built-in self-test for interposer-based 2.5D ICs.
ICCD
Ran Wang, Krishnendu Chakrabarty, Sudipta Bhawmik
2013 — conf
Impact of mid-bond testing in 3D stacked ICs.
DFTS
Mottaqiallah Taouil, Said Hamdioui, Erik Jan Marinissen, Sudipta Bhawmik
2013 — conf
Using 3D-COSTAR for 2.5D test cost optimization.
3DIC
Mottaqiallah Taouil, Said Hamdioui, Erik Jan Marinissen, Sudipta Bhawmik
2003 A conf
The P1500 DFT Disclosure Document: A Standard to Communicate Mergeable Core DFT Data.
ITC
Michael G. Wahl, Sudipta Bhawmik, Kamran Zarrineh, Pradipta Ghosh, Scott Davidson, Peter Harrod
2002 J jnl
An Integrated Approach to Testing Embedded Cores and Interconnects Using Test Access Mechanism (TAM) Switch.
J. Electron. Test.
Subhayu Basu, Indranil Sengupta, Dipanwita Roy Chowdhury, Sudipta Bhawmik
2002 — conf
Reformatting Test Patterns for Testing Embedded Core Based System Using Test Access Mechanism (TAM) Switch.
ASP-DAC/VLSI Design
Subhayu Basu, Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury, Indranil Sengupta, Sudipta Bhawmik
2001 Misc conf
Introduction to SystemC.
VLSI Design
Sudipta Bhawmik
2000 J jnl
A BIST scheme for RTL circuits based on symbolic testabilityanalysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik
2000 Misc conf
Core Based ASIC Design.
VLSI Design
Frank P. Higgins, Sudipta Bhawmik
2000 J jnl
On improving test quality of scan-based BIST.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Huan-Chih Tsai, Kwang-Ting Cheng, Sudipta Bhawmik
1999 A* conf
Improving the Test Quality for Scan-Based BIST Using a General Test Application Scheme.
DAC
Huan-Chih Tsai, Kwang-Ting Cheng, Sudipta Bhawmik
1999 Misc conf
POWERTEST: A Tool for Energy Conscious Weighted Random Pattern Testing.
VLSI Design
Xiaodong Zhang, Kaushik Roy, Sudipta Bhawmik
1998 A* conf
A BIST Scheme for RTL Controller-Data Paths Based on Symbolic Testability Analysis.
DAC
Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik
1998 A conf
A BIST scheme for the detection of path-delay faults.
ITC
Nilanjan Mukherjee, Tapan J. Chakraborty, Sudipta Bhawmik
1998 A conf
An almost full-scan BIST solution-higher fault coverage and shorter test application time.
ITC
Huan-Chih Tsai, Sudipta Bhawmik, Kwang-Ting Cheng
1998 J jnl
Efficient test-point selection for scan-based BIST.
IEEE Trans. Very Large Scale Integr. Syst.
Huan-Chih Tsai, Kwang-Ting Cheng, Chih-Jen Lin, Sudipta Bhawmik
1997 A* conf
A Hybrid Algorithm for Test Point Selection for Scan-Based BIST.
DAC
Huan-Chih Tsai, Kwang-Ting Cheng, Chih-Jen Lin, Sudipta Bhawmik
1997 Misc conf
A Practical Method for Selecting Partial Scan Flip-flops for Large Circuits.
VLSI Design
Sudipta Bhawmik, Indradeep Ghosh
1995 J jnl
Integration of partial scan and built-in self-test.
J. Electron. Test.
Chih-Jen Lin, Yervant Zorian, Sudipta Bhawmik
1993 A conf
PSBIST: A Partial-Scan Based Built-In Self-Test Scheme.
ITC
Chih-Jen Lin, Yervant Zorian, Sudipta Bhawmik
1991 A* conf
Enhanced Controllability for
DAC
Tapan J. Chakraborty, Sudipta Bhawmik, Robert Bencivenga, Chih-Jen Lin
1989 J jnl
DFT Expert: designing testable VLSI circuits.
IEEE Des. Test
Sudipta Bhawmik, Parimal Palchaudhuri
1989 J jnl
Design of Testable VLSI Circuits with Minumum Area Overhead.
IEEE Trans. Computers
Prasad R. Chalasani, Sudipta Bhawmik, Anurag Acharya, Parimal Palchaudhuri
1989 J jnl
Expert system to configure global design for testability structure in a VLSI circuit.
Microprocess. Microsystems
Sudipta Bhawmik, Parimal Pal Chaudhuri
1989 J jnl
KIDLAN: A hardware description language.
Microprocessing and Microprogramming
Anurag Acharya, Sudipta Bhawmik, C. R. K. Prasad, Parimal Palchaudhuri
1989 J jnl
Selecting test methodologies for PLAs and random logic modules in VLSI circuits - an expert systems approach.
Integr.
Sudipta Bhawmik, V. K. Narang, Parimal Pal Chaudhuri
1988 — conf
DFTEXPERT: An Expert System for Design of Testable VLSI Circuits.
IEA/AIE (Vol. 1)
Sudipta Bhawmik, Parimal Pal Chaudhuri