Sudhir S. Kudva

19 papers B 1C 1Misc 1Journal 3Unranked 13

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	17.6 A 100MHz Self-Calibrating RC Oscillator Capable of Clock-Glitch Detection for Hardware Security in a 3nm FinFET Process. ISSCC Nandish Mehta, Stephen G. Tell, Sanquan Song, Sudhir S. Kudva, Brian Zimmer, Mahmut E. Sinangil, C. Thomas Gray
2024	—	`conf`	16.4 High-Density and Low-Power PUF Designs in 5nm Achieving 23× and 39× BER Reduction After Unstable Bit Detection and Masking. ISSCC Sudhir S. Kudva, Mahmut Ersin Sinangil, Stephen G. Tell, Nikola Nedovic, Sanquan Song, Brian Zimmer, C. Thomas Gray
2024	—	`conf`	A Distributed Power Supply Scheme with Dropout Voltage in Range 6mv-500mv and a Low Overhead Retention Mode. CICC Siddharth Saxena, Sudhir S. Kudva, Vijay Srinivasan, Miguel Rodriguez, Walter Li, Shalimar Rasheed, Gaurav Ajwani, Tezaswi Raja, Santosh A, C. Thomas Gray
2022	—	`conf`	An FLL-Based Clock Glitch Detector for Security Circuits in a 5nm FINFET Process. VLSI Technology and Circuits Sanquan Song, Stephen G. Tell, Brian Zimmer, Sudhir S. Kudva, Nikola Nedovic, C. Thomas Gray
2020	—	`conf`	6.6 Reference-Noise Compensation Scheme for Single-Ended Package-to-Package Links. ISSCC Xi Chen, Nikola Nedovic, Stephen G. Tell, Sudhir S. Kudva, Brian Zimmer, Thomas H. Greer, John W. Poulton, Sanquan Song, Walker J. Turner, John M. Wilson, C. Thomas Gray
2019	J	`jnl`	A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator. IEEE J. Solid State Circuits John W. Poulton, John M. Wilson, Walker J. Turner, Brian Zimmer, Xi Chen, Sudhir S. Kudva, Sanquan Song, Stephen G. Tell, Nikola Nedovic, Wenxu Zhao, Sunil R. Sudhakaran, C. Thomas Gray, William J. Dally
2019	—	`conf`	A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET. CICC Sanquan Song, John Poulton, Xi Chen, Brian Zimmer, Stephen G. Tell, Walker J. Turner, Sudhir S. Kudva, Nikola Nedovic, John M. Wilson, C. Thomas Gray, William J. Dally
2018	—	`conf`	A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator. ISSCC John M. Wilson, Walker J. Turner, John W. Poulton, Brian Zimmer, Xi Chen, Sudhir S. Kudva, Sanquan Song, Stephen G. Tell, Nikola Nedovic, Wenxu Zhao, Sunil R. Sudhakaran, C. Thomas Gray, William J. Dally
2018	—	`conf`	A switching linear regulator based on a fast-self-clocked comparator with very low probability of meta-stability and a parallel analog ripple control module. CICC Sudhir S. Kudva, Sanquan Song, John W. Poulton, John M. Wilson, Wenxu Zhao, C. Thomas Gray
2018	—	`conf`	Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects. CICC Walker J. Turner, John W. Poulton, John M. Wilson, Xi Chen, Stephen G. Tell, Matthew Fojtik, Thomas H. Greer, Brian Zimmer, Sanquan Song, Nikola Nedovic, Sudhir S. Kudva, Sunil R. Sudhakaran, Rizwan Bashirullah, Wenxu Zhao, William J. Dally, C. Thomas Gray
2016	—	`conf`	Modeling and Analysis of Power Supply Noise Tolerance with Fine-Grained GALS Adaptive Clocks. ASYNC Divya Akella Kamakshi, Matthew Fojtik, Brucek Khailany, Sudhir S. Kudva, Yaping Zhou, Benton H. Calhoun
2014	—	`conf`	High power-density, hybrid inductive/capacitive converter with area reuse for multi-domain DVS. CICC Sudhir S. Kudva, Saurabh Chaubey, Ramesh Harjani
2013	J	`jnl`	Fully Integrated Capacitive DC-DC Converter With All-Digital Ripple Mitigation Technique. IEEE J. Solid State Circuits Sudhir S. Kudva, Ramesh Harjani
2012	—	`conf`	Fully integrated capacitive converter with all digital ripple mitigation. CICC Sudhir S. Kudva, Ramesh Harjani
2011	J	`jnl`	Fully-Integrated On-Chip DC-DC Converter With a 450X Output Range. IEEE J. Solid State Circuits Sudhir S. Kudva, Ramesh Harjani
2010	—	`conf`	Fully integrated on-chip DC-DC converter with a 450x output range. CICC Sudhir S. Kudva, Ramesh Harjani
2008	C	`conf`	Quadrature generation techniques for frequency multiplication based oscillators. ISCAS Jagdish Nayayan Pandey, Bharadwaj Amrutur, Sudhir S. Kudva
2007	Misc	`conf`	A Low Power Frequency Multiplication Technique for ZigBee Transciever. VLSI Design Jagdish Nayayan Pandey, Sudhir S. Kudva, Bharadwaj Amrutur
2004	B	`conf`	Quality and complexity comparison of H.264 intra mode with JPEG2000 and JPEG. ICIP Aravind Al, Bindu P. Rao, Sudhir S. Kudva, Sreenu Babu, David S. Sumam, Ajit V. Rao