Sudhakar Yalamanchili

180 papers A* 17A 15B 10C 8Misc 12Journal 50Unranked 63
YearRankTypeTitle / Venue / Authors
2021 J jnl
Efficiently Solving Partial Differential Equations in a Partially Reconfigurable Specialized Hardware.
IEEE Trans. Computers
Bahar Asgari, Ramyad Hadidi, Tushar Krishna, Hyesoon Kim, Sudhakar Yalamanchili
2021 J jnl
MAHASIM: Machine-Learning Hardware Acceleration Using a Software-Defined Intelligent Memory System.
J. Signal Process. Syst.
Bahar Asgari, Saibal Mukhopadhyay, Sudhakar Yalamanchili
2021 — conf
VDPred: Predicting Voltage Droop for Power-Effient 3D Multi-core Processor Design.
ICCAE
He Xiao, Monodeep Kar, Saibal Mukhopadhyay, Sudhakar Yalamanchili
2020 A* conf
ALRESCHA: A Lightweight Reconfigurable Sparse-Computation Accelerator.
HPCA
Bahar Asgari, Ramyad Hadidi, Tushar Krishna, Hyesoon Kim, Sudhakar Yalamanchili
2020 J jnl
Slim NoC: A Low-Diameter On-Chip Network Topology for High Energy Efficiency and Scalability.
CoRR
Maciej Besta, Syed Minhaj Hassan, Sudhakar Yalamanchili, Rachata Ausavarungnirun, Onur Mutlu, Torsten Hoefler
2020 A conf
Tango: An Optimizing Compiler for Just-In-Time RTL Simulation.
DATE
Blaise-Pascal Tine, Sudhakar Yalamanchili, Hyesoon Kim
2019 J jnl
ERIDANUS: Efficiently Running Inference of DNNs Using Systolic Arrays.
IEEE Micro
Bahar Asgari, Ramyad Hadidi, Hyesoon Kim, Sudhakar Yalamanchili
2019 J jnl
Heterogeneous integration for artificial intelligence: Challenges and opportunities.
IBM J. Res. Dev.
Saibal Mukhopadhyay, Yun Long, Burhan Ahmad Mudassar, C. S. Nair, Bartlet H. DeProspo, Hakki Mert Torun, M. Kathaperumal, V. Smet, Duckhwan Kim, Sudhakar Yalamanchili, Madhavan Swaminathan
2019 A* conf
LODESTAR: Creating Locally-Dense CNNs for Efficient Inference on Systolic Arrays.
DAC
Bahar Asgari, Ramyad Hadidi, Hyesoon Kim, Sudhakar Yalamanchili
2019 B conf
POSTER: Tango: An Optimizing Compiler for Just-In-Time RTL Simulation.
PACT
Blaise-Pascal Tine, Sudhakar Yalamanchili, Hyesoon Kim, Jeffrey S. Vetter
2018 A conf
A ferroelectric FET based power-efficient architecture for data-intensive computing.
ICCAD
Yun Long, Taesik Na, Prakshi Rastogi, Karthik Rao, Asif Islam Khan, Sudhakar Yalamanchili, Saibal Mukhopadhyay
2018 J jnl
DeepTrain: A Programmable Embedded Platform for Training Deep Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Duckhwan Kim, Taesik Na, Sudhakar Yalamanchili, Saibal Mukhopadhyay
2018 J jnl
Instruction-throughput regulation in computer processors with data-center applications.
Discret. Event Dyn. Syst.
Xinwei Chen, Yorai Wardi, Sudhakar Yalamanchili
2018 J jnl
Memory Slices: A Modular Building Block for Scalable, Intelligent Memory Systems.
CoRR
Bahar Asgari, Saibal Mukhopadhyay, Sudhakar Yalamanchili
2018 A* conf
Slim NoC: A Low-Diameter On-Chip Network Topology for High Energy Efficiency and Scalability.
ASPLOS
Maciej Besta, Syed Minhaj Hassan, Sudhakar Yalamanchili, Rachata Ausavarungnirun, Onur Mutlu, Torsten Hoefler
2018 J jnl
TRINITY: Coordinated Performance, Energy and Temperature Management in 3D Processor-Memory Stacks.
CoRR
Karthik Rao, William J. Song, Yorai Wardi, Sudhakar Yalamanchili
2017 A* conf
Application-Specific Performance-Aware Energy Optimization on Android Mobile Devices.
HPCA
Karthik Rao, Jun Wang, Sudhakar Yalamanchili, Yorai Wardi, Handong Ye
2017 J jnl
Demystifying the Characteristics of 3D-Stacked Memories: A Case Study for Hybrid Memory Cube.
CoRR
Ramyad Hadidi, Bahar Asgari, Burhan Ahmad Mudassar, Saibal Mukhopadhyay, Sudhakar Yalamanchili, Hyesoon Kim
2017 — conf
Demystifying the characteristics of 3D-stacked memories: A case study for Hybrid Memory Cube.
IISWC
Ramyad Hadidi, Bahar Asgari, Burhan Ahmad Mudassar, Saibal Mukhopadhyay, Sudhakar Yalamanchili, Hyesoon Kim
2017 — conf
Lightweight SIMT core designs for intelligent 3D stacked DRAM.
MEMSYS
Chad D. Kersey, Hyesoon Kim, Sudhakar Yalamanchili
2017 J jnl
NeuroTrainer: An Intelligent Memory Module for Deep Learning Training.
CoRR
Duckhwan Kim, Taesik Na, Sudhakar Yalamanchili, Saibal Mukhopadhyay
2017 — conf
Pagevault: securing off-chip memory using page-based authentication.
MEMSYS
Blaise-Pascal Tine, Sudhakar Yalamanchili
2017 J jnl
Power Regulation in High Performance Multicore Processors.
CoRR
X. Chen, Yorai Wardi, Sudhakar Yalamanchili
2017 — conf
Power regulation in high performance multicore processors.
CDC
Xinwei Chen, Yorai Wardi, Sudhakar Yalamanchili
2016 A* conf
Amdahl's law for lifetime reliability scaling in heterogeneous multicore processors.
HPCA
William J. Song, Saibal Mukhopadhyay, Sudhakar Yalamanchili
2016 J jnl
FNM: An Enhanced Null-Message Algorithm for Parallel Simulation of Multicore Systems.
ACM Trans. Model. Comput. Simul.
Jun Wang, Zhenjiang Dong, Sudhakar Yalamanchili, George F. Riley
2016 — conf
General-purpose join algorithms for large graph triangle listing on heterogeneous systems.
GPGPU@PPoPP
Daniel Zinn, Haicheng Wu, Jin Wang, Molham Aref, Sudhakar Yalamanchili
2016 J jnl
IPA in the Loop: Control Design for Throughput Regulation in Computer Processors.
CoRR
Xinwei Chen, Yorai Wardi, Sudhakar Yalamanchili
2016 — conf
IPA in the loop: Control design for throughput regulation in computer processors.
WODES
Xinwei Chen, Yorai Wardi, Sudhakar Yalamanchili
2016 A* conf
LaPerm: Locality Aware Scheduler for Dynamic Parallelism on GPUs.
ISCA
Jin Wang, Norm Rubin, Albert Sidelnik, Sudhakar Yalamanchili
2016 A* conf
Neurocube: A Programmable Digital Neuromorphic Architecture with High-Density 3D Memory.
ISCA
Duckhwan Kim, Jaeha Kung, Sek M. Chai, Sudhakar Yalamanchili, Saibal Mukhopadhyay
2016 — conf
Power-Constrained Performance Scheduling of Data Parallel Tasks.
E2SC@SC
Eric Anger, Jeremiah J. Wilke, Sudhakar Yalamanchili
2016 J jnl
Thermally Adaptive Cache Access Mechanisms for 3D Many-Core Architectures.
IEEE Comput. Archit. Lett.
He Xiao, Wen Yueh, Saibal Mukhopadhyay, Sudhakar Yalamanchili
2016 — conf
Understanding the Impact of Air and Microfluidics Cooling on Performance of 3D Stacked Memory Systems.
MEMSYS
Syed Minhaj Hassan, Sudhakar Yalamanchili
2015 — conf
Application Modeling for Scalable Simulation of Massively Parallel Systems.
HPCC/CSS/ICESS
Eric Anger, Damian Dechev, Gilbert Hendry, Jeremiah J. Wilke, Sudhakar Yalamanchili
2015 J jnl
Architectural Reliability: Lifetime Reliability Characterization and Management ofMany-Core Processors.
IEEE Comput. Archit. Lett.
William J. Song, Saibal Mukhopadhyay, Sudhakar Yalamanchili
2015 A* conf
Dynamic thread block launch: a lightweight execution mechanism to support irregular applications on GPUs.
ISCA
Jin Wang, Norm Rubin, Albert Sidelnik, Sudhakar Yalamanchili
2015 A* conf
Harmonia: balancing compute and memory power in high-performance GPUs.
ISCA
Indrani Paul, Wei Huang, Manish Arora, Sudhakar Yalamanchili
2015 — conf
Managing performance-reliability tradeoffs in multicore processors.
IRPS
William J. Song, Saibal Mukhopadhyay, Sudhakar Yalamanchili
2015 — conf
Near Data Processing: Impact and Optimization of 3D Memory System Architecture on the Uncore.
MEMSYS
Syed Minhaj Hassan, Sudhakar Yalamanchili, Saibal Mukhopadhyay
2015 — conf
SIMT-based Logic Layers for Stacked DRAM Architectures: A Prototype.
MEMSYS
Chad D. Kersey, Sudhakar Yalamanchili, Hyesoon Kim
2015 C conf
Temperature regulation in multicore processors using adjustable-gain integral controllers.
CCA
Karthik Rao, William J. Song, Sudhakar Yalamanchili, Yorai Wardi
2015 Misc conf
Throughput Regulation in Shared Memory Multicore Processors.
HiPC
X. Chen, H. Xiao, Yorai Wardi, Sudhakar Yalamanchili
2015 — conf
Understanding Energy Aspects of Processing-near-Memory for HPC Workloads.
MEMSYS
Hyojong Kim, Hyesoon Kim, Sudhakar Yalamanchili, Arun F. Rodrigues
2014 — conf
An efficient front-end for timing-directed parallel simulation of multi-core system.
SimuTools
Zhenjiang Dong, Jun Wang, George F. Riley, Sudhakar Yalamanchili
2014 — conf
Architecture-independent modeling of intra-node data movement.
LLVM@SC
Eric Anger, Sudhakar Yalamanchili, Scott Pakin, Patrick S. McCormick
2014 — conf
Bubble sharing: Area and energy efficient adaptive routers using centralized buffers.
NOCS
Syed Minhaj Hassan, Sudhakar Yalamanchili
2014 — conf
Characterization and analysis of dynamic parallelism in unstructured GPU applications.
IISWC
Jin Wang, Sudhakar Yalamanchili
2014 J jnl
Co-design of multicore architectures and microfluidic cooling for 3D stacked ICs.
Microelectron. J.
Zhimin Wan, He Xiao, Yogendra Joshi, Sudhakar Yalamanchili
2014 J jnl
Control Principles and On-Chip Circuits for Active Cooling Using Integrated Superlattice-Based Thin-Film Thermoelectric Devices.
IEEE Trans. Very Large Scale Integr. Syst.
Borislav Alexandrov, Owen Sullivan, William J. Song, Sudhakar Yalamanchili, Satish Kumar, Saibal Mukhopadhyay
2014 J jnl
Coordinated energy management in heterogeneous processors.
Sci. Program.
Indrani Paul, Vignesh T. Ravi, Srilatha Manne, Manish Arora, Sudhakar Yalamanchili
2014 — conf
Efficient Instrumentation of GPGPU Applications Using Information Flow Analysis and Symbolic Execution.
GPGPU@ASPLOS
Naila Farooqui, Karsten Schwan, Sudhakar Yalamanchili
2014 — ed.
Eighth IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014, Ferrara, Italy, September 17-19, 2014
NoCS
Davide Bertozzi, Luca Benini, Sudhakar Yalamanchili, Jörg Henkel
2014 B conf
Energy Introspector: A parallel, composable framework for integrated power-reliability-thermal modeling for multicore architectures.
ISPASS
William J. Song, Saibal Mukhopadhyay, Sudhakar Yalamanchili
2014 Misc conf
Harmonica: An FPGA-Based Data Parallel Soft Core.
FCCM
Chad D. Kersey, Sudhakar Yalamanchili, Hyojong Kim, Nimit Nigania, Hyesoon Kim
2014 B conf
Manifold: A parallel simulation framework for multicore systems.
ISPASS
Jun Wang, Jesse G. Beu, Rishiraj A. Bheda, Tom Conte, Zhenjiang Dong, Chad D. Kersey, Mitchelle Rasquinha, George F. Riley, William J. Song, He Xiao, Peng Xu, Sudhakar Yalamanchili
2014 — conf
Multipredicate Join Algorithms for Accelerating Relational Graph Processing on GPUs.
ADMS@VLDB
Haicheng Wu, Daniel Zinn, Molham Aref, Sudhakar Yalamanchili
2014 — conf
ParallelJS: An Execution Framework for JavaScript on Heterogeneous Systems.
GPGPU@ASPLOS
Jin Wang, Norman Rubin, Sudhakar Yalamanchili
2014 J jnl
Power Modeling for GPU Architectures Using McPAT.
ACM Trans. Design Autom. Electr. Syst.
Jieun Lim, Nagesh B. Lakshminarayana, Hyesoon Kim, William J. Song, Sudhakar Yalamanchili, Wonyong Sung
2014 A conf
Red Fox: An Execution Environment for Relational Query Processing on GPUs.
CGO
Haicheng Wu, Gregory F. Diamos, Tim Sheard, Molham Aref, Sean Baxter, Michael Garland, Sudhakar Yalamanchili
2013 B conf
A Study of the Effect of Partitioning on Parallel Simulation of Multicore Systems.
MASCOTS
Zhenjiang Dong, Jun Wang, George F. Riley, Sudhakar Yalamanchili
2013 — conf
Accelerating simulation of agent-based models on heterogeneous architectures.
GPGPU@ASPLOS
Jin Wang, Norman Rubin, Haicheng Wu, Sudhakar Yalamanchili
2013 J jnl
Adaptive virtual channel partitioning for network-on-chip in heterogeneous architectures.
ACM Trans. Design Autom. Electr. Syst.
Jaekyu Lee, Si Li, Hyesoon Kim, Sudhakar Yalamanchili
2013 — conf
Centralized buffer router: A low latency, low power router for high radix NOCs.
NOCS
Syed Minhaj Hassan, Sudhakar Yalamanchili
2013 A* conf
Cooperative boosting: needy versus greedy power management.
ISCA
Indrani Paul, Srilatha Manne, Manish Arora, William Lloyd Bircher, Sudhakar Yalamanchili
2013 A conf
Coordinated energy management in heterogeneous processors.
SC
Indrani Paul, Vignesh T. Ravi, Srilatha Manne, Manish Arora, Sudhakar Yalamanchili
2013 J jnl
Design space exploration of on-chip ring interconnection for a CPU-GPU heterogeneous architecture.
J. Parallel Distributed Comput.
Jaekyu Lee, Si Li, Hyesoon Kim, Sudhakar Yalamanchili
2013 C conf
Oncilla: A GAS runtime for efficient resource allocation and data movement in accelerated clusters.
CLUSTER
Jeffrey S. Young, Se Hoon Shon, Sudhakar Yalamanchili, Alex Merritt, Karsten Schwan, Holger Fröning
2013 — conf
Optimizing parallel simulation of multicore systems using domain-specific knowledge.
SIGSIM-PADS
Jun Wang, Zhenjiang Dong, Sudhakar Yalamanchili, George F. Riley
2013 B conf
Relational algorithms for multi-bulk-synchronous processors.
PPoPP
Gregory Frederick Diamos, Haicheng Wu, Jin Wang, Ashwin Sanjay Lele, Sudhakar Yalamanchili
2012 C conf
A power capping controller for multicore processors.
ACC
Nawaf I. Almoosa, William J. Song, Yorai Wardi, Sudhakar Yalamanchili
2012 — conf
A universal parallel front-end for execution driven microarchitecture simulation.
RAPIDO
Chad D. Kersey, Arun Rodrigues, Sudhakar Yalamanchili
2012 J jnl
Characterization and transformation of unstructured control flow in bulk synchronous GPU applications.
Int. J. High Perform. Comput. Appl.
Haicheng Wu, Gregory F. Diamos, Jin Wang, Si Li, Sudhakar Yalamanchili
2012 — conf
Commodity Converged Fabrics for Global Address Spaces in Accelerator Clouds.
HPCC-ICESS
Jeffrey S. Young, Sudhakar Yalamanchili
2012 — conf
Designing Configurable, Modifiable and Reusable Components for Simulation of Multicore Systems.
SC Companion
Jun Wang, Jesse G. Beu, Sudhakar Yalamanchili, Tom Conte
2012 A conf
Dynamic compilation of data-parallel kernels for vector processors.
CGO
Andrew Kerr, Gregory Frederick Diamos, Sudhakar Yalamanchili
2012 Misc conf
Eiger: A framework for the automated synthesis of statistical performance models.
HiPC
Andrew Kerr, Eric Anger, Gilbert Hendry, Sudhakar Yalamanchili
2012 — conf
Instruction-based energy estimation methodology for asymmetric manycore processor simulations.
SimuTools
William J. Song, Sudhakar Yalamanchili, Arun F. Rodrigues, Saibal Mukhopadhyay
2012 A* conf
Kernel Weaver: Automatically Fusing Database Primitives for Efficient GPU Computation.
MICRO
Haicheng Wu, Gregory Frederick Diamos, Srihari Cadambi, Sudhakar Yalamanchili
2012 B conf
Lynx: A dynamic instrumentation system for data-parallel applications on GPGPU architectures.
ISPASS
Naila Farooqui, Andrew Kerr, Greg Eisenhauer, Karsten Schwan, Sudhakar Yalamanchili
2012 — conf
Optimizing Data Warehousing Applications for GPUs Using Kernel Fusion/Fission.
IPDPS Workshops
Haicheng Wu, Gregory F. Diamos, Jin Wang, Srihari Cadambi, Sudhakar Yalamanchili, Srimat T. Chakradhar
2012 C conf
Performance impact of virtual machine placement in a datacenter.
IPCCC
Indrani Paul, Sudhakar Yalamanchili, Lizy K. John
2012 — conf
Satisfying Data-Intensive Queries Using GPU Clusters.
SC Companion
Jeffrey S. Young, Haicheng Wu, Sudhakar Yalamanchili
2012 — conf
Throughput regulation in multicore processors via IPA.
CDC
Nawaf I. Almoosa, William J. Song, Sudhakar Yalamanchili, Yorai Wardi
2011 J jnl
A Scalable Design Methodology for Energy Minimization of STTRAM: A Circuit and Architecture Perspective.
IEEE Trans. Very Large Scale Integr. Syst.
Subho Chatterjee, Mitchelle Rasquinha, Sudhakar Yalamanchili, Saibal Mukhopadhyay
2011 — conf
A framework for dynamically instrumenting GPU compute applications within GPU Ocelot.
GPGPU
Naila Farooqui, Andrew Kerr, Gregory Frederick Diamos, Sudhakar Yalamanchili, Karsten Schwan
2011 — ch.
Interconnection Networks.
Encyclopedia of Parallel Computing
Sudhakar Yalamanchili
2011 J jnl
Keeneland: Bringing Heterogeneous GPU Computing to the Computational Science Community.
Comput. Sci. Eng.
Jeffrey S. Vetter, Richard Glassbrook, Jack J. Dongarra, Karsten Schwan, Bruce Loftis, Stephen Taylor McNally, Jeremy S. Meredith, James H. Rogers, Philip C. Roth, Kyle Spafford, Sudhakar Yalamanchili
2011 B conf
Regulating Locality vs. Parallelism Tradeoffs in Multiple Memory Controller Environments.
PACT
Syed Minhaj Hassan, Dhruv Choudhary, Mitchelle Rasquinha, Sudhakar Yalamanchili
2011 A* conf
SIMD re-convergence at thread frontiers.
MICRO
Gregory Frederick Diamos, Benjamin Ashbaugh, Subramaniam Maiyuran, Andrew Kerr, Haicheng Wu, Sudhakar Yalamanchili
2011 — ch.
Switching Techniques.
Encyclopedia of Parallel Computing
Sudhakar Yalamanchili
2010 A conf
An energy efficient cache design using spin torque transfer (STT) RAM.
ISLPED
Mitchelle Rasquinha, Dhruv Choudhary, Subho Chatterjee, Saibal Mukhopadhyay, Sudhakar Yalamanchili
2010 — conf
Controller design for tracking induced miss-rates in cache memories.
ICCA
Nawaf I. Almoosa, Yorai Wardi, Sudhakar Yalamanchili
2010 — conf
Dynamic Partitioned Global Address Spaces for power efficient DRAM virtualization.
Green Computing Conference
Jeffrey S. Young, Sudhakar Yalamanchili
2010 — conf
HyVM - Hybrid Virtual Machines - Efficient Use of Future Heterogeneous Chip Multiprocessors.
ARCS
Karsten Schwan, Ada Gavrilovska, Sudhakar Yalamanchili
2010 — conf
Modeling GPU-CPU workloads and systems.
GPGPU
Andrew Kerr, Gregory F. Diamos, Sudhakar Yalamanchili
2010 B conf
Ocelot: a dynamic optimization framework for bulk-synchronous applications in heterogeneous systems.
PACT
Gregory Frederick Diamos, Andrew Kerr, Sudhakar Yalamanchili, Nathan Clark
2010 A conf
Speculative execution on multi-GPU systems.
IPDPS
Gregory F. Diamos, Sudhakar Yalamanchili
2009 — conf
A characterization and analysis of PTX kernels.
IISWC
Andrew Kerr, Gregory F. Diamos, Sudhakar Yalamanchili
2009 A conf
A methodology for robust, energy efficient design of Spin-Torque-Transfer RAM arrays at scaled technologies.
ICCAD
Subho Chatterjee, Mitchelle Rasquinha, Sudhakar Yalamanchili, Saibal Mukhopadhyay
2009 — conf
High Performance Non-blocking Switch Design in 3D Die-Stacking Technology.
ISVLSI
Dean L. Lewis, Sudhakar Yalamanchili, Hsien-Hsin S. Lee
2008 Misc conf
An Utilization Driven Framework for Energy Efficient Caches.
HiPC
Subramanian Ramaswamy, Sudhakar Yalamanchili
2008 A conf
Harmony: an execution model and runtime for heterogeneous many core systems.
HPDC
Gregory F. Diamos, Sudhakar Yalamanchili
2008 Misc conf
ShareStreams-V: A Virtualized QoS Packet Scheduling Accelerator.
FCCM
Kangtao Kendall Chuang, Sudhakar Yalamanchili, Ada Gavrilovska, Karsten Schwan
2007 — conf
Customized Placement for High Performance Embedded Processor Caches.
ARCS
Subramanian Ramaswamy, Sudhakar Yalamanchili
2007 C conf
Improving cache efficiency via resizing + remapping.
ICCD
Subramanian Ramaswamy, Sudhakar Yalamanchili
2006 C conf
Customizable Fault Tolerant Caches for Embedded Processors.
ICCD
Subramanian Ramaswamy, Sudhakar Yalamanchili
2006 J jnl
Data trace cache: an application specific cache architecture.
SIGARCH Comput. Archit. News
Subramanian Ramaswamy, Jaswanth Sreeram, Sudhakar Yalamanchili, Krishna V. Palem
2006 J jnl
MMR: A MultiMedia Router architecture to support hybrid workloads.
J. Parallel Distributed Comput.
María Blanca Caminero, Carmen Carrión, Francisco J. Quiles, José Duato, Sudhakar Yalamanchili
2005 J jnl
Traffic Scheduling Solutions with QoS Support for an Input-Buffered MultiMedia Router.
IEEE Trans. Parallel Distributed Syst.
María Blanca Caminero, Carmen Carrión, Francisco J. Quiles, José Duato, Sudhakar Yalamanchili
2004 — conf
A Framework for Compiler Driven Design Space Exploration for Embedded System Customization.
ASIAN
Krishna V. Palem, Lakshmi N. Chakrapani, Sudhakar Yalamanchili
2004 Misc conf
ShareStreams: A Scalable Architecture and Hardware Support for High-Speed QoS Packet Schedulers.
FCCM
Raj Krishnamurthy, Sudhakar Yalamanchili, Karsten Schwan, Richard West
2003 Misc conf
A Hardware Approach to QoS Support in Cluster Environments: The Multimedia Router MMR.
PDPTA
María Blanca Caminero, Carmen Carrión, Francisco J. Quiles, José Duato, Sudhakar Yalamanchili
2003 A conf
A Solution for Handling Hybrid Traffic in Clustered Environments: The MultiMedia Router MMR.
IPDPS
María Blanca Caminero, Carmen Carrión, Francisco J. Quiles, José Duato, Sudhakar Yalamanchili
2003 A conf
Leveraging Block Decisions and Aggregation in the ShareStreams QoS Architecture.
IPDPS
Raj Krishnamurthy, Sudhakar Yalamanchili, Karsten Schwan, Richard West
2002 Misc conf
A Tunable Communications Library for Data Injection.
PDPTA
Craig D. Ulmer, Sudhakar Yalamanchili
2002 — conf
A multimedia router architecture to provide high performance and QoS guarantees to mixed traffic.
ICME (1)
María Blanca Caminero, Carmen Carrión, Francisco J. Quiles, José Duato, Sudhakar Yalamanchili
2002 C conf
A new switch scheduling algorithm to improve QoS in the multimedia router.
IEEE Workshop on Multimedia Signal Processing
María Blanca Caminero, Carmen Carrión, Francisco J. Quiles, José Duato, Sudhakar Yalamanchili
2002 Misc conf
Algorithms for Switch-Scheduling in the Multimedia Router for LANs.
HiPC
Indrani Paul, Sudhakar Yalamanchili, José Duato
2002 — conf
Architecture and Hardware for Scheduling Gigabit Packet Streams.
Hot Interconnects
Raj Krishnamurthy, Sudhakar Yalamanchili, Karsten Schwan, Richard West
2002 A conf
Investigating Switch Scheduling Algorithms to Support QoS in the Multimedia Router.
IPDPS
María Blanca Caminero, Carmen Carrión, Francisco J. Quiles, José Duato, Sudhakar Yalamanchili
2002 Misc conf
The Customization Landscape for Embedded Systems.
HiPC
Sudhakar Yalamanchili
2001 — conf
A Cost-Effective Hardware Link Scheduling Algorithm for the Multimedia Router (MMR).
ICN (2)
María Blanca Caminero, Carmen Carrión, Francisco J. Quiles, José Duato, Sudhakar Yalamanchili
2001 A conf
Tuning Buffer Size in the Multimedia Router (MMR).
IPDPS
María Blanca Caminero, Carmen Carrión, Francisco J. Quiles, José Duato, Sudhakar Yalamanchili
2000 Misc conf
An Extensible Message Layer for High-Performance Clusters.
PDPTA
Craig D. Ulmer, Sudhakar Yalamanchili
2000 J jnl
Configurable Algorithms for Complete Exchange in 2D Meshes.
IEEE Trans. Parallel Distributed Syst.
Young-Joo Suh, Sudhakar Yalamanchili
2000 J jnl
Software-Based Rerouting for Fault-Tolerant Pipelined Communication.
IEEE Trans. Parallel Distributed Syst.
Young-Joo Suh, Binh Vien Dao, José Duato, Sudhakar Yalamanchili
2000 A conf
Switch Scheduling in the Multimedia Router (MMR).
IPDPS
Damon S. Love, Sudhakar Yalamanchili, José Duato, María Blanca Caminero, Francisco J. Quiles
1999 J jnl
Dynamically Configurable Message Flow Control for Fault-Tolerant Routing.
IEEE Trans. Parallel Distributed Syst.
Binh Vien Dao, José Duato, Sudhakar Yalamanchili
1999 A* conf
MMR: A High-Performance Multimedia Router - Architecture and Design Trade-Offs.
HPCA
José Duato, Sudhakar Yalamanchili, María Blanca Caminero, Damon S. Love, Francisco J. Quiles
1999 — conf
Performance Evaluation of the Multimedia Router with MPEG-2 Video Traffic.
CANPC
María Blanca Caminero, Francisco J. Quiles, José Duato, Damon S. Love, Sudhakar Yalamanchili
1999 — conf
QUIC: A Quality of Service Network Interface Layer for Communication in NOWs.
Heterogeneous Computing Workshop
Richard West, Raj Krishnamurthy, W. K. Norton, Karsten Schwan, Sudhakar Yalamanchili, Marcel-Catalin Rosu, V. Sarat
1999 — conf
Teaching Pipelining and Concurrency using Hardware Description Languages.
MSE
Tsai Chi Huang, Sudhakar Yalamanchili, Roy W. Melton, Philip R. Bingham, Cecil O. Alford
1998 J jnl
All-To-All Communication with Minimum Start-Up Costs in 2D/3D Tori and Meshes.
IEEE Trans. Parallel Distributed Syst.
Young-Joo Suh, Sudhakar Yalamanchili
1998 — conf
FARA - A Framework for Adaptive Resource Allocation in Complex Real-Time Systems.
IEEE Real Time Technology and Applications Symposium
Daniela Rosu, Karsten Schwan, Sudhakar Yalamanchili
1998 — ed.
Parallel Computer Routing and Communication, Second International Workshop, PCRCW'97, Atlanta, Georgia, USA, June 26-27, 1997, Proceedings
PCRCW
Sudhakar Yalamanchili, José Duato
1997 A* conf
Architectural Support for Reducing Communication Overhead in Multiprocessor Interconnection Networks.
HPCA
Binh Vien Dao, Sudhakar Yalamanchili, José Duato
1997 — conf
Deadlock- and Livelock-Free Routing Protocols for Wave Switching.
IPPS
José Duato, Pedro López, Sudhakar Yalamanchili
1997 — book
Interconnection networks - an engineering approach.
José Duato, Sudhakar Yalamanchili, Lionel M. Ni
1997 A conf
On adaptive resource allocation for complex real-time application.
RTSS
Daniela Rosu, Karsten Schwan, Sudhakar Yalamanchili, Rakesh Jha
1997 C conf
Power Constrained Design of Multiprocessor Interconnection Networks.
ICCD
Chirag S. Patel, Sek M. Chai, Sudhakar Yalamanchili, David E. Schimmel
1997 — conf
Power/Performance Trade-offs for Direct Networks.
PCRCW
Chirag S. Patel, Sek M. Chai, Sudhakar Yalamanchili, David E. Schimmel
1996 — conf
A High Performance Router Architecture for Interconnection Networks.
ICPP, Vol. 1
José Duato, Pedro López, Federico Silla, Sudhakar Yalamanchili
1996 Misc conf
Adaptive resource allocation for embedded parallel applications.
HiPC
Rakesh Jha, Mustafa Muhammad, Sudhakar Yalamanchili, Karsten Schwan, Daniela Ivan-Rosu, Chris deCastro
1996 — conf
Algorithms for All-to-All Personalized Exchange in 2D and 3D Tori.
IPPS
Young-Joo Suh, Sudhakar Yalamanchili
1996 J jnl
Augmented Binary Hypercube: A New Architecture for Processor Management.
IEEE Trans. Computers
Hari Lalgudi, Ian F. Akyildiz, Sudhakar Yalamanchili
1996 J jnl
Distributed Deadlock-Free Routing in Faulty, Pipelined, Direct Interconnection Networks.
IEEE Trans. Computers
Patrick T. Gaughan, Binh Vien Dao, Sudhakar Yalamanchili, David E. Schimmel
1996 — conf
Incorporating Multi-Chip Module Packaging Constraints into System Design.
ED&TC
Vivek Garg, Steve Lacy, David E. Schimmel, Darrell Stogner, Craig D. Ulmer, D. Scott Wills, Sudhakar Yalamanchili
1996 — conf
Optimistic parallel computation: an example from computational chemistry.
SPDP
Emily Angerer Crawford, Karsten Schwan, Sudhakar Yalamanchili
1996 J jnl
Paradigms for Modeling and Simulation of Multiprocessor Architectures.
Int. J. Comput. Simul.
Sudhakar Yalamanchili, Todd Carpenter
1996 — conf
Using rapid prototyping in computer architecture design laboratories.
WCAE@HPCA
James O. Hamblen, Henry Owen, Sudhakar Yalamanchili, Binh Vien Dao
1995 J jnl
A Family of Fault-Tolerant Routing Protocols for Direct Multiprocessor Networks.
IEEE Trans. Parallel Distributed Syst.
Patrick T. Gaughan, Sudhakar Yalamanchili
1995 J jnl
A Performance Model of Pipelined K-ary n-cubes.
IEEE Trans. Computers
Patrick T. Gaughan, Sudhakar Yalamanchili
1995 A* conf
Configurable Flow Control Mechanisms for Fault-Tolerant Routing.
ISCA
Binh Vien Dao, José Duato, Sudhakar Yalamanchili
1995 J jnl
Parallelism in Sequential Multiprocessor Simulation Models: A Case Study.
ACM Trans. Model. Comput. Simul.
Hatem Sellami, Sudhakar Yalamanchili
1995 J jnl
Partitioning and mapping in embedded multiprocessor architectures in the presence of constraints.
Concurr. Pract. Exp.
Sudhakar Yalamanchili, Lynn E. Te Winkel, David L. Perschbacher, Belle Shenoy
1995 — conf
Software Based Fault-Tolerant Oblivious Routing in Pipelined Networks.
ICPP (1)
Young-Joo Suh, Binh Vien Dao, José Duato, Sudhakar Yalamanchili
1995 — conf
Time scale combining of conservative parallel discrete event simulations.
IPPS
Hatem Sellami, Sudhakar Yalamanchili
1994 A* conf
Ariadne - An Adaptive Router for Fault-Tolerant Multicomputers.
ISCA
James D. Allen, Patrick T. Gaughan, David E. Schimmel, Sudhakar Yalamanchili
1994 J jnl
Large Join Optimization on a Hypercube Multiprocessor.
IEEE Trans. Knowl. Data Eng.
Eileen Tien Lin, Edward Omiecinski, Sudhakar Yalamanchili
1994 J jnl
Partitioning Coarse-Grain Signal Flow Graphs for Heterogeneous DSP Architectures.
Int. J. Comput. Simul.
Christopher H. de Castro, Sudhakar Yalamanchili
1994 B conf
Scouting: Fully Adaptive, Deadlock-Free Routing in Faulty Pipelined Networks.
ICPADS
José Duato, V. B. Dao, Patrick T. Gaughan, Sudhakar Yalamanchili
1994 B conf
Simulation of Marked Graphs on SIMD Architectures Using Efficient Memory Management.
MASCOTS
Hatem Sellami, James D. Allen, David E. Schimmel, Sudhakar Yalamanchili
1993 J jnl
Adaptive Routing Protocols for Hypercube Interconnection Networks.
Computer
Patrick T. Gaughan, Sudhakar Yalamanchili
1993 — conf
Analytical Models of Bandwidth Allocation in Pipelined
IPPS
Patrick T. Gaughan, Sudhakar Yalamanchili
1993 — conf
Genie: An Environment for Partitioning and Mapping in Embedded Multiprocessors.
SPDP
Sudhakar Yalamanchili, Lynn E. Te Winkel, David L. Perschbacher, Belle Shenoy
1993 — conf
Partitioning and Mapping a Class of Parallel Multiprocessor Simulation Models.
SPDP
Hatem Sellami, Sudhakar Yalamanchili
1992 — conf
Dominant Representations: A Paradigm for Mapping Parallel Computations.
IPPS
Ajay Mohindra, Sudhakar Yalamanchili
1992 — conf
Parallel Optimization and Execution of Large Join Queries.
FGCS
Eileen Tien Lin, Edward Omiecinski, Sudhakar Yalamanchili
1992 — conf
Pipelined Circuit-Switching: A Fault-Tolerant Variant of Wormhole Routing.
SPDP
Patrick T. Gaughan, Sudhakar Yalamanchili
1991 — conf
Adaptive routing in generalized hypercube architectures.
SPDP
Steven D. Young, Sudhakar Yalamanchili
1987 J jnl
A Characterization and Analysis of Parallel Processor Interconnection Networks.
IEEE Trans. Computers
Sudhakar Yalamanchili, Jake K. Aggarwal
1987 J jnl
Parallel image normalization on a mesh connected array processor.
Pattern Recognit.
S. Y. Lee, Sudhakar Yalamanchili, Jake K. Aggarwal
1985 J jnl
A system organization for parallel image processing.
Pattern Recognit.
Sudhakar Yalamanchili, Jake K. Aggarwal
1985 J jnl
Analysis of a model for parallel image processing.
Pattern Recognit.
Sudhakar Yalamanchili, Jake K. Aggarwal
1985 J jnl
Reconfiguration Strategies for Parallel Architectures.
Computer
Sudhakar Yalamanchili, Jake K. Aggarwal
1984 A* conf
Algebraic Properties of some Parallel Processor Interconnection Networks.
ICDE
Sudhakar Yalamanchili, Jake K. Aggarwal
1984 J jnl
Formulation of parallel image processing tasks.
Pattern Recognit. Lett.
Sudhakar Yalamanchili, Jake K. Aggarwal
1984 J jnl
Workstations in a Local Area Network Environment.
Computer
Sudhakar Yalamanchili, Miroslaw Malek, Jake K. Aggarwal
1982 J jnl
Extraction of moving object descriptions via differencing.
Comput. Graph. Image Process.
Sudhakar Yalamanchili, Worthy N. Martin, Jake K. Aggarwal