Sudhakar Pamarti

105 papers A* 1A 5C 9Misc 2Journal 54Unranked 34

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A 180-nm Voltage-Controlled Magneto-Electric RAM With Sub-1-ns Switching Time. IEEE J. Solid State Circuits Haris Suhail, Haoran He, Vinod Kurian Jacob, Jiyue Yang, Kang L. Wang, Sudhakar Pamarti
2026	J	`jnl`	MXFormer: A Microscaling Floating-Point Charge-Trap Transistor Compute-in-Memory Transformer Accelerator. CoRR George Karfakis, Samyak Chakrabarty, Vinod Kurian Jacob, Siyun Qiao, Subramanian S. Iyer, Sudhakar Pamarti, Puneet Gupta
2025	J	`jnl`	A 65-nm Digital Stochastic Compute-in-Memory CNN Processor With 8-bit Precision. IEEE J. Solid State Circuits Jiyue Yang, Tianmu Li, Wojciech Romaszkan, Puneet Gupta, Sudhakar Pamarti
2025	J	`jnl`	A Comparative Analysis of Low Temperature and Room Temperature Circuit Operation. IEEE Trans. Very Large Scale Integr. Syst. Zhichao Chen, Ali H. Hassan, Rhesa Muhammad Ramadhan, Yingheng Li, Chih-Kong Ken Yang, Sudhakar Pamarti, Puneet Gupta
2025	J	`jnl`	Corrections to "Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <-103-dBc Spurious Tones Using Digital Spur Cancellation". IEEE J. Solid State Circuits Mohammadreza Zeinali, Sudhakar Pamarti
2024	—	`conf`	A 278-514M Event/s ADC-Less Stochastic Compute-In-Memory Convolution Accelerator for Event Camera. VLSI Technology and Circuits Jiyue Yang, Alexander Graening, Wojciech Romaszkan, Vinod Kurian Jacob, Puneet Gupta, Sudhakar Pamarti
2024	—	`conf`	A Sub-Sampling 35GHz PLL in 45nm PDSOI BiCMOS with 37fs Integrated Jitter and a FoM of -252dB. BCICTS Christopher Chen, Yan Zhang, Hao-Yu Chien, Jiazhang Song, Jia Zhou, Chao-Jen Tien, Sudhakar Pamarti, Chih-Kong Ken Yang, Mau-Chung Frank Chang
2024	—	`conf`	Cryogenic Alternative: CMOS Versus Dynamic-Based Logic. MWSCAS Ali H. Hassan, Puneet Gupta, Sudhakar Pamarti, Chih-Kong Ken Yang
2024	J	`jnl`	Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <-103-dBc Spurious Tones Using Digital Spur Cancellation. IEEE J. Solid State Circuits Mohammadreza Zeinali, Szu-Yao Hung, Sudhakar Pamarti
2024	J	`jnl`	Digital Residual Alias Cancellation for Filtering-by-Aliasing Receivers. IEEE Trans. Circuits Syst. I Regul. Pap. Shi Bu, Vinod Kurian Jacob, Sudhakar Pamarti
2024	J	`jnl`	FPGA Crystal Oscillator Circuit Emulation Based on Wave Digital Filter. IEEE Trans. Very Large Scale Integr. Syst. Abdulaziz Alshaya, Sudhakar Pamarti, Christos Papavassiliou
2024	—	`conf`	Novel Energy-Efficient and Latency-Improved PVT Tolerant Read Scheme for SRAM Design in Video Processing and Machine Learning Applications. MWSCAS Soumitra Pal, Jiyue Yang, Stephen Bauer, Puneet Gupta, Sudhakar Pamarti
2024	J	`jnl`	SCIMITAR: Stochastic Computing In-Memory In-Situ Tracking ARchitecture for Event-Based Cameras. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wojciech Romaszkan, Jiyue Yang, Alexander Graening, Vinod Kurian Jacob, Jishnu Sen, Sudhakar Pamarti, Puneet Gupta
2024	J	`jnl`	Voltage-Controlled Magnetoelectric Devices for Neuromorphic Diffusion Process. CoRR Yang Cheng, Qingyuan Shu, Albert Lee, Haoran He, Ivy Zhu, Haris Suhail, Minzhang Chen, Renhe Chen, Zirui Wang, Hantao Zhang, Chih-Yao Wang, Shan-Yi Yang, Yu-Chen Hsin, Cheng-Yi Shih, Hsin-Han Lee, Ran Cheng, Sudhakar Pamarti, Xufeng Kou, Kang L. Wang
2023	—	`conf`	A Spur-free Dynamic Element Matching Scheme for Bandpass DACs. NEWCAS Jarrah Bergeron, Sudhakar Pamarti
2023	—	`conf`	Analytical Array-Level Comparison of Read/Write Performance Between Voltage Controlled-MRAM and STT-MRAM. MWSCAS Haris Suhail, Jiyue Yang, Haoran He, Kang L. Wang, Sudhakar Pamarti
2023	J	`jnl`	REX-SC: Range-Extended Stochastic Computing Accumulation for Neural Network Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tianmu Li, Wojciech Romaszkan, Sudhakar Pamarti, Puneet Gupta
2022	C	`conf`	A 14-bit 1-GS/s SiGe Bootstrap Sampler for High Resolution ADC with 250-MHz Input. ISCAS Jiazhang Song, Li-Yang Chen, Mau-Chung Frank Chang, Sudhakar Pamarti, Chih-Kong Ken Yang
2022	C	`conf`	A Digital Alias Cancellation Technique for Filtering-by-Aliasing Receivers. ISCAS Shi Bu, Vinod Kurian Jacob, Sudhakar Pamarti
2022	J	`jnl`	A Dual-Channel High-Linearity Filtering-by-Aliasing Receiver Front-End Supporting Carrier Aggregation. IEEE J. Solid State Circuits Shi Bu, Sudhakar Pamarti
2021	—	`conf`	6.3 A 0.9V Dual-Channel Filtering-by-Aliasing Receiver Front-End Achieving +35dBm IIP3 and <-81dBm LO Leakage Supporting Intra-and Inter-Band Carrier Aggregation. ISSCC Shi Bu, Sudhakar Pamarti
2021	—	`conf`	A Calibration-Free In-Memory True Random Number Generator Using Voltage-Controlled MRAM. ESSCIRC Jiyue Yang, Di Wu, Albert Lee, Seyed Armin Razavi, Puneet Gupta, Kang L. Wang, Sudhakar Pamarti
2021	—	`conf`	A Calibration-Free In-Memory True Random Number Generator Using Voltage-Controlled MRAM. ESSDERC Jiyue Yang, Di Wu, Albert Lee, Seyed Armin Razavi, Puneet Gupta, Kang L. Wang, Sudhakar Pamarti
2021	—	`conf`	A Sub-50fs-Jitter Sub-Sampling PLL with a Harmonic-Enhanced 30-GHz-Fundemental Class-C VCO in 0.18µm SiGe BiCMOS. ESSCIRC Yan Zhang, Chia-Jen Liang, Christopher Chen, Andrew Liu, Jason Woo, Sudhakar Pamarti, Chih-Kong Ken Yang, Mau-Chung Frank Chang
2021	A*	`conf`	Designing a 2048-Chiplet, 14336-Core Waferscale Processor. DAC Saptadeep Pal, Jingyang Liu, Irina Alam, Nicholas Cebry, Haris Suhail, Shi Bu, Subramanian S. Iyer, Sudhakar Pamarti, Rakesh Kumar, Puneet Gupta
2021	A	`conf`	GEO: Generation and Execution Optimized Stochastic Computing Accelerator for Neural Networks. DATE Tianmu Li, Wojciech Romaszkan, Sudhakar Pamarti, Puneet Gupta
2021	J	`jnl`	Periodically Time-Varying Noise Cancellation for Filtering-by-Aliasing Receiver Front Ends. IEEE J. Solid State Circuits Shi Bu, Sameed Hameed, Sudhakar Pamarti
2021	—	`conf`	Session 6 Overview: High-Performance Receivers and Transmitters for Sub-6GHz Radios Wireless Subcommittee. ISSCC Yiwu Tang, Yuan-Hung Chung, Sudhakar Pamarti
2020	A	`conf`	ACOUSTIC: Accelerating Convolutional Neural Networks through Or-Unipolar Skipped Stochastic Computing. DATE Wojciech Romaszkan, Tianmu Li, Tristan Melton, Sudhakar Pamarti, Puneet Gupta
2020	J	`jnl`	Introduction to the Special Issue on the 2020 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits David T. Blaauw, Hoi Lee, John P. Keane, Jaehyouk Choi, Sudhakar Pamarti
2019	—	`conf`	A 0.5-to-2.5GHz Multi-Output Fractional Frequency Synthesizer with 90fs Jitter and -106dBc Spurious Tones Based on Digital Spur Cancellation. ISSCC Szu-Yao Hung, Sudhakar Pamarti
2019	—	`conf`	A 0.55nW/0.5V 32kHz Crystal Oscillator Based on a DC-Only Sustaining Amplifier for IoT. ISSCC Hani Esmaeelzadeh, Sudhakar Pamarti
2019	J	`jnl`	A Sub-nW 32-kHz Crystal Oscillator Architecture Based on a DC-Only Sustaining Amplifier. IEEE J. Solid State Circuits Hani Esmaeelzadeh, Sudhakar Pamarti
2019	—	`conf`	An 8.5pJ/bit Ultra-Low Power Wake-Up Receiver Using Schottky Diodes for IoT Applications. ESSCIRC Mahmoud R. Elhebeary, Li-Yang Chen, Sudhakar Pamarti, Chih-Kong Ken Yang
2019	—	`conf`	An LPTV Noise Cancellation Technique for a 0.9-V Filtering-by-Aliasing Receiver Front-End with >67-dB Stopband Rejection. CICC Shi Bu, Sameed Hameed, Sudhakar Pamarti
2018	J	`jnl`	A Broadband Class-AB Power Amplifier With Instantaneous Supply-Switching Efficiency Enhancement for Cable TV Application. IEEE J. Solid State Circuits Jeffrey Lee, Ray Gomez, Sudhakar Pamarti
2018	J	`jnl`	A Quick Startup Technique for High-Q Oscillators Using Precisely Timed Energy Injection. IEEE J. Solid State Circuits Hani Esmaeelzadeh, Sudhakar Pamarti
2018	J	`jnl`	Design and Analysis of a Programmable Receiver Front End Based on Baseband Analog-FIR Filtering Using an LPTV Resistor. IEEE J. Solid State Circuits Sameed Hameed, Sudhakar Pamarti
2018	J	`jnl`	Design and Analysis of a Programmable Receiver Front End With Time-Interleaved Baseband Analog-FIR Filtering. IEEE J. Solid State Circuits Sameed Hameed, Sudhakar Pamarti
2018	J	`jnl`	Errata for "Design and Analysis of a Programmable Receiver Front End Based on Baseband Analog-FIR Filtering Using an LPTV Resistor". IEEE J. Solid State Circuits Sameed Hameed, Sudhakar Pamarti
2018	J	`jnl`	Impedance Matching and Reradiation in LPTV Receiver Front-Ends: An Analysis Using Conversion Matrices. IEEE Trans. Circuits Syst. I Regul. Pap. Sameed Hameed, Sudhakar Pamarti
2018	J	`jnl`	Theoretical Analysis of Circuit Non-Idealities in a Passive Spectrum Scanner Based on Periodically Time-Varying Circuit Components. IEEE Trans. Circuits Syst. I Regul. Pap. Neha Sinha, Sudhakar Pamarti
2017	—	`conf`	24.6 A time-interleaved filtering-by-aliasing receiver front-end with >70dB suppression at <4× bandwidth frequency offset. ISSCC Sameed Hameed, Sudhakar Pamarti
2017	—	`conf`	A 10-to-650MHz 1.35W class-AB power amplifier with instantaneous supply-switching efficiency enhancement. CICC Jeffrey Lee, Sudhakar Pamarti, Ramon A. Gomez
2017	J	`jnl`	A 36-V 49% Efficient Hybrid Charge Pump in Nanometer-Scale Bulk CMOS Technology. IEEE J. Solid State Circuits Yousr Ismail, Haechang Lee, Sudhakar Pamarti, Chih-Kong Ken Yang
2017	J	`jnl`	A MEMS-Assisted Temperature Sensor With 20-µK Resolution, Conversion Rate of 200 S/s, and FOM of 0.04 pJK2. IEEE J. Solid State Circuits Meisam Heidarpour Roshan, Samira Zaliasl, Kimo Joo, Kamran Souri, Rajkumar Palwai, Lijun Will Chen, Amanpreet Singh, Sudhakar Pamarti, Nicholas Miller, Joseph C. Doll, Carl Arft, Sassan Tabatabaei, Carl Sechen, Aaron Partridge, Vinod Menon
2017	—	`conf`	A precisely-timed energy injection technique achieving 58/10/2μs start-up in 1.84/10/50MHz crystal oscillators. CICC Hani Esmaeelzadeh, Sudhakar Pamarti
2017	J	`jnl`	Design and Analysis of an 8 mW, 1 GHz Span, Passive Spectrum Scanner With >+31 dBm Out-of-Band IIP3 Using Periodically Time-Varying Circuit Components. IEEE J. Solid State Circuits Neha Sinha, Mansour Rachid, Shanthi Pavan, Sudhakar Pamarti
2017	J	`jnl`	High-Efficiency Millimeter-Wave Energy-Harvesting Systems With Milliwatt-Level Output Power. IEEE Trans. Circuits Syst. II Express Briefs Med Nariman, Farid Shirinfar, Sudhakar Pamarti, Ahmadreza Rofougaran, Franco De Flaviis
2017	—	`conf`	Session 3 - Clocking techniques. CICC Sudhakar Pamarti, Nan Sun
2016	—	`conf`	11.1 Dual-MEMS-resonator temperature-to-digital converter with 40 K resolution and FOM of 0.12pJK2. ISSCC Meisam Heidarpour Roshan, Samira Zali Asl, Kimo Joo, Kamran Souri, Rajkumar Palwai, Lijun Will Chen, Sudhakar Pamarti, Joseph C. Doll, Nicholas Miller, Carl Arft, Sassan Tabatabaei, Carl Sechen, Aaron Partridge, Vinod Menon
2016	—	`conf`	26.6 A programmable receiver front-end achieving >17dBm IIP3 at <1.25×BW frequency offset. ISSCC Sameed Hameed, Neha Sinha, Mansour Rachid, Sudhakar Pamarti
2016	J	`jnl`	Frequency-Domain Analysis of N-Path Filters Using Conversion Matrices. IEEE Trans. Circuits Syst. II Express Briefs Sameed Hameed, Mansour Rachid, Babak Daneshrad, Sudhakar Pamarti
2016	—	`conf`	Time-varying circuit approaches for software defined and cognitive radio applications. ISOCC Sudhakar Pamarti, N. Sinha, Sameed Hameed, Mansour Rachid
2016	C	`conf`	Wave digital filter based analog circuit emulation on FPGA. ISCAS Wei Wu, Yen-Lung Chen, Yue Ma, Chien-Nan Jimmy Liu, Jing-Yang Jou, Sudhakar Pamarti, Lei He
2015	J	`jnl`	A 3 ppm 1.5 × 0.8 mm 2 1.0 µA 32.768 kHz MEMS-Based Oscillator. IEEE J. Solid State Circuits Samira Zali Asl, James C. Salvia, Ginel C. Hill, Lijun Will Chen, Kimo Joo, Rajkumar Palwai, Niveditha Arumugam, Meghan Phadke, Shouvik Mukherjee, Haechang Lee, Charles Grosjean, Paul M. Hagelin, Sudhakar Pamarti, Terri S. Fiez, Kofi A. A. Makinwa, Aaron Partridge, Vinod Menon
2015	—	`conf`	A sharp programmable passive filter based on filtering by Aliasing. VLSIC Neha Sinha, Mansour Rachid, Sudhakar Pamarti
2015	C	`conf`	Frequency-domain analysis of a mixer-first receiver using conversion matrices. ISCAS Sameed Hameed, Mansour Rachid, Babak Daneshrad, Sudhakar Pamarti
2015	J	`jnl`	Linearization Through Dithering: A 50 MHz Bandwidth, 10-b ENOB, 8.2 mW VCO-Based ADC. IEEE J. Solid State Circuits Abhishek Ghosh, Sudhakar Pamarti
2015	A	`conf`	Toward Wave Digital Filter based Analog Circuit Emulation on FPGA (Abstract Only). FPGA Wei Wu, Peng Gu, Yen-Lung Chen, Chien-Nan Liu, Sudhakar Pamarti, Chang Wu, Lei He
2014	—	`conf`	12.9 A 1.55×0.85mm ISSCC Samira Zali Asl, Shouvik Mukherjee, Lijun Will Chen, Kimo Joo, Rajkumar Palwai, Niveditha Arumugam, P. Galle, Meghan Phadke, Charles Grosjean, Jim Salvia, Haechang Lee, Sudhakar Pamarti, Terri S. Fiez, Kofi A. A. Makinwa, Aaron Partridge, Vinod Menon
2014	—	`conf`	23.8 A 34V charge pump in 65nm bulk CMOS technology. ISSCC Yousr Ismail, Haechang Lee, Sudhakar Pamarti, Chih-Kong Ken Yang
2014	—	`conf`	RF digital predistorter implementation using polynomial optimization. MWSCAS Hojat Parta, Milos D. Ercegovac, Sudhakar Pamarti
2013	J	`jnl`	A 2.4 GHz 0.1-Fref-Bandwidth All-Digital Phase-Locked Loop With Delay-Cell-Less TDC. IEEE Trans. Circuits Syst. I Regul. Pap. Minyoung Song, Inhwa Jung, Sudhakar Pamarti, Chulwoo Kim
2013	—	`conf`	A 50MHz bandwidth, 10-b ENOB, 8.2mW VCO-based ADC enabled by filtered-dithering based linearization. CICC Abhishek Ghosh, Sudhakar Pamarti
2013	J	`jnl`	A Temperature-to-Digital Converter for a MEMS-Based Programmable Oscillator With < ±0.5-ppm Frequency Stability and < 1-ps Integrated Jitter. IEEE J. Solid State Circuits Michael H. Perrott, James C. Salvia, Fred S. Lee, Aaron Partridge, Shouvik Mukherjee, Carl Arft, Jin-Tae Kim, Niveditha Arumugam, Pavan Gupta, Sassan Tabatabaei, Sudhakar Pamarti, Haechang Lee, Fari Assaderaghi
2013	—	`conf`	Adaptive signal conditioning algorithms to enable wideband signal digitization. ICC Abhishek Ghosh, Sudhakar Pamarti
2013	—	`conf`	Enabling high-speed, high-resolution ADCs using signal conditioning algorithms. MWSCAS Abhishek Ghosh, Sudhakar Pamarti
2013	J	`jnl`	Filtering by Aliasing. IEEE Trans. Signal Process. Mansour Rachid, Sudhakar Pamarti, Babak Daneshrad
2013	Misc	`conf`	Filtering of subtractive discrete dither in quantizers: Some new results. ICASSP Abhishek Ghosh, Sudhakar Pamarti
2013	C	`conf`	Mitigating timing errors in time-interleaved ADCs: A signal conditioning approach. ISCAS Abhishek Ghosh, Sudhakar Pamarti
2012	—	`conf`	A temperature-to-digital converter for a MEMS-based programmable oscillator with better than ±0.5ppm frequency stability. ISSCC Michael H. Perrott, Jim Salvia, Fred S. Lee, Aaron Partridge, Shouvik Mukherjee, Carl Arft, Jin-Tae Kim, Niveditha Arumugam, Pavan Gupta, Sassan Tabatabaei, Sudhakar Pamarti, Haechang Lee, Fari Assaderaghi
2012	J	`jnl`	Clock/Frequency Generation Circuits and Systems. J. Electr. Comput. Eng. Woogeun Rhee, Antonio Liscidini, Jae-Yoon Sim, Kenichi Okada, Sudhakar Pamarti
2012	J	`jnl`	Dithered quantizers with negligible in-band dither power CoRR Abhishek Ghosh, Sudhakar Pamarti
2012	J	`jnl`	Mitigating Timing Errors in Time-Interleaved ADCs: a signal conditioning approach CoRR Abhishek Ghosh, Sudhakar Pamarti
2012	Misc	`conf`	Robustness of xampling-based RF receivers against analog mismatches. ICASSP Chiranjib Choudhuri, Abhishek Ghosh, Urbashi Mitra, Sudhakar Pamarti
2012	J	`jnl`	Worst-Case Estimation for Data-Dependent Timing Jitter and Amplitude Noise in High-Speed Differential Link. IEEE Trans. Very Large Scale Integr. Syst. Wei Yao, Yiyu Shi, Lei He, Sudhakar Pamarti
2011	J	`jnl`	A 2.4 GHz Wideband Open-Loop GFSK Transmitter With Phase Quantization Noise Cancellation. IEEE J. Solid State Circuits Pin-En Su, Sudhakar Pamarti
2011	J	`jnl`	A Spur-Free MASH DDSM With High-Order Filtered Dither. IEEE Trans. Circuits Syst. II Express Briefs Brian Fitzgibbon, Sudhakar Pamarti, Michael Peter Kennedy
2011	C	`conf`	A novel reconfigurable alias interference cancellation technique for A-to-D conversion. ISCAS Mansour Rachid, Sudhakar Pamarti, Babak Daneshrad
2011	C	`conf`	A progammable baseband anti-alias filter for a passive-mixer-based, SAW-less, multi-band, multi-mode WEDGE transmitter. ISCAS Sandeep D'Souza, Mau-Chung Frank Chang, Sudhakar Pamarti, Bipul Agarwal, Hossein Zarei, Tirdad Sowlati, Roc Berenguer
2011	J	`jnl`	Open-Loop Wide-Bandwidth Phase Modulation Techniques. J. Electr. Comput. Eng. Nitin Nidhi, Pin-En Su, Sudhakar Pamarti
2010	—	`conf`	A 16 Gb/s four-wire CDMA-based high speed I/O link with transmitter timing adjustment. CICC Tzu-Chien Hsueh, Sudhakar Pamarti
2010	J	`jnl`	A 3 , ˟, 3.8 Gb/s Four-Wire High Speed I/O Link Based on CDMA-Like Crosstalk Cancellation. IEEE J. Solid State Circuits Tzu-Chien Hsueh, Pin-En Su, Sudhakar Pamarti
2010	J	`jnl`	A Digital Envelope Combiner for Switching Power Amplifier Linearization. IEEE Trans. Circuits Syst. II Express Briefs Nitesh Singhal, Sudhakar Pamarti
2010	J	`jnl`	A Low Area, Switched-Resistor Based Fractional-N Synthesizer Applied to a MEMS-Based Programmable Oscillator. IEEE J. Solid State Circuits Michael H. Perrott, Sudhakar Pamarti, Eric G. Hoffman, Fred S. Lee, Shouvik Mukherjee, Cathy Lee, Vadim Tsinker, Sathi Perumal, Benjamin Soto, Niveditha Arumugam, Bruno W. Garlepp
2010	—	`conf`	A low-area switched-resistor loop-filter technique for fractional-N synthesizers applied to a MEMS-based programmable oscillator. ISSCC Michael H. Perrott, Sudhakar Pamarti, Eric G. Hoffman, Fred S. Lee, Shouvik Mukherjee, Cathy Lee, Vadim Tsinker, Sathi Perumal, Benjamin Soto, Niveditha Arumugam, Bruno W. Garlepp
2010	C	`conf`	A power amplifier with minimal efficiency degradation under back-off. ISCAS Nitesh Singhal, Nitin Nidhi, Sudhakar Pamarti
2010	J	`jnl`	Mismatch Shaping Techniques to Linearize Charge Pump Errors in Fractional-N PLLs. IEEE Trans. Circuits Syst. I Regul. Pap. Pin-En Su, Sudhakar Pamarti
2009	—	`conf`	A 3×3.8Gb/s four-wire high speed I/O link based on CDMA-like crosstalk cancellation. CICC Tzu-Chien Hsueh, Pin-En Su, Sudhakar Pamarti
2009	J	`jnl`	Digital techniques for integrated frequency synthesizers: A tutorial. IEEE Commun. Mag. Sudhakar Pamarti
2009	J	`jnl`	Fractional-N Phase-Locked-Loop-Based Frequency Synthesis: A Tutorial. IEEE Trans. Circuits Syst. II Express Briefs Pin-En Su, Sudhakar Pamarti
2009	A	`conf`	Joint design-time and post-silicon optimization for digitally tuned analog circuits. ICCAD Wei Yao, Yiyu Shi, Lei He, Sudhakar Pamarti
2009	—	`conf`	Worst case timing jitter and amplitude noise in differential signaling. ISQED Wei Yao, Yiyu Shi, Lei He, Sudhakar Pamarti, Yu Hu
2008	J	`jnl`	A Spur Elimination Technique for Phase Interpolation-Based Fractional-N PLLs. IEEE Trans. Circuits Syst. I Regul. Pap. Sudhakar Pamarti, Siamak Delshadpour
2008	J	`jnl`	A Theoretical Study of the Quantization Noise in Split Delta-Sigma ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. Sudhakar Pamarti
2008	J	`jnl`	The Effect of Noise Cross-Coupling on Time-Interleaved Delta-Sigma ADCs. IEEE Trans. Circuits Syst. II Express Briefs Sudhakar Pamarti
2007	C	`conf`	A Theoretical Analysis of Split Delta-Sigma ADCs. ISCAS Sudhakar Pamarti
2007	J	`jnl`	LSB Dithering in MASH Delta-Sigma D/A Converters. IEEE Trans. Circuits Syst. I Regul. Pap. Sudhakar Pamarti, Ian Galton
2007	J	`jnl`	Statistics of the Quantization Noise in 1-Bit Dithered Single-Quantizer Digital Delta-Sigma Modulators. IEEE Trans. Circuits Syst. I Regul. Pap. Sudhakar Pamarti, Jared Welz, Ian Galton
2006	A	`conf`	Power-efficient pulse width modulation DC/DC converters with zero voltage switching control. ISLPED Changbo Long, Sasank Reddy, Sudhakar Pamarti, Lei He, Tanay Karnik
2006	J	`jnl`	Replica compensated linear regulators for supply-regulated phase-locked loops. IEEE J. Solid State Circuits Elad Alon, Jaeha Kim, Sudhakar Pamarti, Ken Chang, Mark Horowitz
2005	J	`jnl`	Addition to "A Wideband 2.4-GHz Delta-Sigma Fractional-$N$PLL With 1-Mb/s In-Loop Modulation". IEEE J. Solid State Circuits Sudhakar Pamarti, Lars C. Jansson, Ian Galton
2004	J	`jnl`	A wideband 2.4-GHz delta-sigma fractional-NPLL with 1-Mb/s in-loop modulation. IEEE J. Solid State Circuits Sudhakar Pamarti, Lars C. Jansson, Ian Galton
2003	J	`jnl`	Phase-noise cancellation design tradeoffs in delta-sigma fractional-N PLLs. IEEE Trans. Circuits Syst. II Express Briefs Sudhakar Pamarti, Ian Galton