Sudhakar Muddu

23 papers A* 3A 4B 1Misc 2Journal 7Unranked 6
YearRankTypeTitle / Venue / Authors
2010 J jnl
Accurate Predictive Interconnect Modeling for System-Level Design.
IEEE Trans. Very Large Scale Integr. Syst.
Luca P. Carloni, Andrew B. Kahng, Sudhakar Muddu, Alessandro Pinto, Kambiz Samadi, Puneet Sharma
2008 J jnl
Defocus-Aware Leakage Estimation and Control.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Andrew B. Kahng, Sudhakar Muddu, Puneet Sharma
2002 — conf
Estimation needs for future networking systems interconnect.
SLIP
Sudhakar Muddu
2002 J jnl
Provably good global buffering by generalized multiterminalmulticommodity flow approximation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky
2001 — conf
Noise Model for Multiple Segmented Coupled RC Interconnects.
ISQED
Andrew B. Kahng, Sudhakar Muddu, Niranjan Pol, Devendra Vidhani
2001 B conf
Practical Approximation Algorithms for Separable Packing Linear Programs.
WADS
Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky
2001 — conf
Provably good global buffering by multi-terminal multicommodity flow approximation.
ASP-DAC
Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky
2000 A conf
Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Design.
ICCAD
Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Sudhakar Muddu, Dirk Stroobandt, Dennis Sylvester
2000 A* conf
On switch factor based analysis of coupled
DAC
Andrew B. Kahng, Sudhakar Muddu, Egino Sarto
2000 A conf
Provably Good Global Buffering Using an Available Buffer Block Plan.
ICCAD
Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky
1999 Misc conf
Improved Effective Capacitance Computations for Use in Logic and Layout Optimization.
VLSI Design
Andrew B. Kahng, Sudhakar Muddu
1999 Misc conf
Interconnect Optimization Strategies for High-Performance VLSI Designs.
VLSI Design
Andrew B. Kahng, Sudhakar Muddu, Egino Sarto
1999 J jnl
Tuning Strategies for Global Interconnects in High-Performance Deep-Submicron ICs.
VLSI Design
Andrew B. Kahng, Sudhakar Muddu, Egino Sarto
1998 A conf
Interconnect Tuning Strategies for High-Performance Ics.
DATE
Andrew B. Kahng, Sudhakar Muddu, Egino Sarto, Rahul Sharma
1998 — conf
New efficient algorithms for computing effective capacitance.
ISPD
Andrew B. Kahng, Sudhakar Muddu
1998 — conf
Repeater and Interconnect Strategies for High-Performance Physical Designs.
SBCCI
Sudhakar Muddu, Egino Sarto, M. Hofmann, A. Bashteen
1997 J jnl
An analytical delay model for RLC interconnects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Andrew B. Kahng, Sudhakar Muddu
1997 J jnl
Analysis of RC interconnections under ramp input.
ACM Trans. Design Autom. Electr. Syst.
Andrew B. Kahng, Sudhakar Muddu
1996 A* conf
Analysis of RC Interconnections Under Ramp Input.
DAC
Andrew B. Kahng, Sudhakar Muddu
1996 A conf
Analytical delay models for VLSI interconnects under ramp input.
ICCAD
Andrew B. Kahng, Kei Masuko, Sudhakar Muddu
1994 J jnl
A new adaptive multi-start technique for combinatorial global optimizations.
Oper. Res. Lett.
Kenneth D. Boese, Andrew B. Kahng, Sudhakar Muddu
1994 A* conf
Delay Analysis of VLSI Interconnections Using the Diffusion Equation Model.
DAC
Andrew B. Kahng, Sudhakar Muddu
1994 — conf
Optimal equivalent circuits for interconnect delay calculations using moments.
EURO-DAC
Sudhakar Muddu, Andrew B. Kahng