Sudhakar M. Reddy

662 papers A* 28A 116B 19C 27Misc 87Journal 230Unranked 154

Year	Rank	Type	Title / Venue / Authors
2022	Misc	`conf`	Accurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel Configurations. VTS Shi-Xuan Zheng, Chung-Yu Yeh, Kuen-Jong Lee, Chen Wang, Wu-Tung Cheng, Mark Kassab, Janusz Rajski, Sudhakar M. Reddy
2022	J	`jnl`	Efficient Test Compression Configuration Selection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chong-Siao Ye, Shi-Xuan Zheng, Fong-Jyun Tsai, Chen Wang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Justyna Zawada, Mark Kassab, Janusz Rajski
2020	J	`jnl`	Deterministic Stellar BIST for Automotive ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yingdi Liu, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer
2020	B	`conf`	Efficient Prognostication of Pattern Count with Different Input Compression Ratios. ETS Fong-Jyun Tsai, Chong-Siao Ye, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski
2020	—	`conf`	Estimation of Test Data Volume for Scan Architectures with Different Numbers of Input Channels. ITC-Asia Fong-Jyun Tsai, Chong-Siao Ye, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski, Shi-Xuan Zheng
2020	J	`jnl`	Generating Single- and Double-Pattern Tests for Multiple CMOS Fault Models in One ATPG Run. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yi-Cheng Kung, Kuen-Jong Lee, Sudhakar M. Reddy
2020	J	`jnl`	LFSR generation for high test coverage and low hardware overhead. IET Comput. Digit. Tech. Leonel Hernández Martínez, S. Saqib Khursheed, Sudhakar M. Reddy
2020	A	`conf`	Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations. ITC Fong-Jyun Tsai, Chong-Siao Ye, Kuen-Jong Lee, Shi-Xuan Zheng, Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski, Chen Wang, Justyna Zawada
2019	B	`conf`	A supervised machine learning application in volume diagnosis. ETS Yue Tian, Gaurav Veda, Wu-Tung Cheng, Manish Sharma, Huaxing Tang, Neerja Bawaskar, Sudhakar M. Reddy
2019	J	`jnl`	An Efficient Diagnosis-Aware ATPG Procedure to Enhance Diagnosis Resolution and Test Compaction. IEEE Trans. Very Large Scale Integr. Syst. Cheng-Hung Wu, Kuen-Jong Lee, Sudhakar M. Reddy
2019	—	`conf`	Deep Learning Based Test Compression Analyzer. ATS Cheng-Hung Wu, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Gaurav Veda, Sudhakar M. Reddy, Chun-Cheng Hu, Chong-Siao Ye
2019	J	`jnl`	Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design. ACM Trans. Design Autom. Electr. Syst. Naixing Wang, Irith Pomeranz, Sudhakar M. Reddy, Arani Sinha, Srikanth Venkataraman
2019	B	`conf`	On Generating Fault Diagnosis Patterns for Designs with X Sources. ETS Xijiang Lin, Sudhakar M. Reddy
2019	A	`conf`	Resynthesis for Avoiding Undetectable Faults Based on Design-for-Manufacturability Guidelines. DATE Naixing Wang, Irith Pomeranz, Sudhakar M. Reddy, Arani Sinha, Srikanth Venkataraman
2018	J	`jnl`	A Repair-for-Diagnosis Methodology for Logic Circuits. IEEE Trans. Very Large Scale Integr. Syst. Cheng-Hung Wu, Sheng-Lin Lin, Kuen-Jong Lee, Sudhakar M. Reddy
2018	A	`conf`	Deterministic Stellar BIST for In-System Automotive Test. ITC Yingdi Liu, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer
2018	J	`jnl`	Exploiting Aging Benefits for the Design of Reliable Drowsy Cache Memories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Daniele Rossi, Vasileios Tenentes, Sudhakar M. Reddy, Bashir M. Al-Hashimi, Andrew D. Brown
2018	A	`conf`	Generating Compact Test Patterns for DC and AC Faults Using One ATPG Run. ITC Yi-Cheng Kung, Kuen-Jong Lee, Sudhakar M. Reddy
2018	—	`conf`	Generating Compact Test Patterns for Stuck-at Faults and Transition Faults in One ATPG Run. ITC-Asia Yi-Cheng Kung, Kuen-Jong Lee, Sudhakar M. Reddy
2018	J	`jnl`	On the Generation of Waveform-Accurate Hazard and Charge-Sharing Aware Tests for Transistor Stuck-Off Faults in CMOS Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jan Burchard, Dominik Erb, Sudhakar M. Reddy, Adit D. Singh, Bernd Becker
2018	B	`conf`	Recycled IC detection through aging sensor. ETS Daniele Rossi, Vasileios Tenentes, S. Saqib Khursheed, Sudhakar M. Reddy
2018	Misc	`conf`	Staggered ATPG with capture-per-cycle observation test points. VTS Yingdi Liu, Janusz Rajski, Sudhakar M. Reddy, Jedrzej Solecki, Jerzy Tyszer
2017	Misc	`conf`	Accurate Diagnosis of Interconnect Open Defects Based on the Robust Enhanced Aggressor Victim Model. VLSID Pascal Raiola, Dominik Erb, Sudhakar M. Reddy, Bernd Becker
2017	—	`conf`	Automatic Identification of Yield Limiting Layout Patterns Using Root Cause Deconvolution on Volume Scan Diagnosis Data. ATS Wu-Tung Cheng, Randy Klingenberg, Brady Benware, Wu Yang, Manish Sharma, Geir Eide, Yue Tian, Sudhakar M. Reddy, Yan Pan, Sherwin Fernandes, Atul Chittora
2017	Misc	`conf`	Efficient SAT-based generation of hazard-activated TSOF tests. VTS Jan Burchard, Dominik Erb, Sudhakar M. Reddy, Adit D. Singh, Bernd Becker
2017	J	`jnl`	Embedded Deterministic Test Points. IEEE Trans. Very Large Scale Integr. Syst. Cesar Acero, Derek Feltham, Yingdi Liu, Elham K. Moghaddam, Nilanjan Mukherjee, Marek Patyra, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Justyna Zawada
2017	A	`conf`	Fast and waveform-accurate hazard-aware SAT-based TSOF ATPG. DATE Jan Burchard, Dominik Erb, Adit D. Singh, Sudhakar M. Reddy, Bernd Becker
2017	—	`conf`	Test generation for open and delay faults in CMOS circuits. ITC-Asia Cheng-Hung Wu, Kuen-Jong Lee, Sudhakar M. Reddy
2017	B	`conf`	Volume diagnosis data mining. ETS Wu-Tung Cheng, Yue Tian, Sudhakar M. Reddy
2016	A	`conf`	Minimal area test points for deterministic patterns. ITC Yingdi Liu, Elham K. Moghaddam, Nilanjan Mukherjee, Sudhakar M. Reddy, Janusz Rajski, Jerzy Tyszer
2016	—	`conf`	On Achieving Maximal Chain Diagnosis Resolution through Test Pattern Selection. ATS Xijiang Lin, Sudhakar M. Reddy, Wu-Tung Cheng
2016	—	`conf`	On the Switching Activity in Faulty Circuits During Test Application. ATS Irith Pomeranz, Sudhakar M. Reddy
2016	B	`conf`	Transistor stuck-on fault detection tests for digital CMOS circuits. ETS Xijiang Lin, Sudhakar M. Reddy, Janusz Rajski
2015	Misc	`conf`	Embedded Tutorial ET2: Volume Diagnosis for Yield Improvement. VLSID Wu-Tung Cheng, Sudhakar M. Reddy
2015	Misc	`conf`	Improving diagnosis resolution of a fault detection test set. VTS Andreas Riefert, Matthias Sauer, Sudhakar M. Reddy, Bernd Becker
2015	J	`jnl`	Isometric Test Data Compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Amit Kumar, Mark Kassab, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Chen Wang
2015	Misc	`conf`	Multi-cycle Circuit Parameter Independent ATPG for interconnect open defects. VTS Dominik Erb, Karsten Scheibler, Matthias Sauer, Sudhakar M. Reddy, Bernd Becker
2015	A	`conf`	On generating high quality tests based on cell functions. ITC Xijiang Lin, Sudhakar M. Reddy
2015	Misc	`conf`	Using Boolean Tests to Improve Detection of Transistor Stuck-Open Faults in CMOS Digital Logic Circuits. VLSID Xijiang Lin, Sudhakar M. Reddy, Janusz Rajski
2014	Misc	`conf`	A Cube-Aware Compaction Method for Scan ATPG. VLSID Sharada Jha, Kameshwar Chandrasekar, Weixin Wu, Ramesh Sharma, Sanjay Sengupta, Sudhakar M. Reddy
2014	—	`conf`	Circuit Parameter Independent Test Pattern Generation for Interconnect Open Defects. ATS Dominik Erb, Karsten Scheibler, Matthias Sauer, Sudhakar M. Reddy, Bernd Becker
2014	Misc	`conf`	Efficient SAT-Based Circuit Initialization for Larger Designs. VLSID Matthias Sauer, Sven Reimer, Sudhakar M. Reddy, Bernd Becker
2014	—	`ch.`	Fundamentals of Small-Delay Defect Testing. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits Sudhakar M. Reddy, Peter Maxwell
2014	A	`conf`	Isometric test compression with low toggling activity. ITC Amit Kumar, Mark Kassab, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Chen Wang
2014	J	`jnl`	On achieving minimal size test sets for scan designs. it Inf. Technol. Sudhakar M. Reddy, Zhuo Zhang
2014	Misc	`conf`	SAT-Based Test Pattern Generation with Improved Dynamic Compaction. VLSID Alexander Czutro, Sudhakar M. Reddy, Ilia Polian, Bernd Becker
2013	Misc	`conf`	Distributed dynamic partitioning based diagnosis of scan chain. VTS Yu Huang, Xiaoxin Fan, Huaxing Tang, Manish Sharma, Wu-Tung Cheng, Brady Benware, Sudhakar M. Reddy
2013	—	`conf`	On the Generation of Compact Deterministic Test Sets for BIST Ready Designs. Asian Test Symposium Amit Kumar, Janusz Rajski, Sudhakar M. Reddy, Thomas Rinderknecht
2013	A	`conf`	On the generation of compact test sets. ITC Amit Kumar, Janusz Rajski, Sudhakar M. Reddy, Chen Wang
2012	Misc	`conf`	Analysis of Reachable Sensitisable Paths in Sequential Circuits with SAT and Craig Interpolation. VLSI Design Matthias Sauer, Stefan Kupferschmid, Alejandro Czutro, Sudhakar M. Reddy, Bernd Becker
2012	—	`conf`	Diagnosis of Cell Internal Defects with Multi-cycle Test Patterns. Asian Test Symposium Xiaoxin Fan, Manish Sharma, Wu-Tung Cheng, Sudhakar M. Reddy
2012	A	`conf`	Functional test of small-delay faults using SAT and Craig interpolation. ITC Matthias Sauer, Stefan Kupferschmid, Alexander Czutro, Ilia Polian, Sudhakar M. Reddy, Bernd Becker
2012	A	`conf`	Improved volume diagnosis throughput using dynamic design partitioning. ITC Xiaoxin Fan, Huaxing Tang, Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Brady Benware
2012	—	`conf`	Performance aware partitioning for 3D-SOCs. ISOCC Amit Kumar, Sudhakar M. Reddy, Bernd Becker, Irith Pomeranz
2012	J	`jnl`	Reset and partial-reset-based functional broadside tests. IET Comput. Digit. Tech. Irith Pomeranz, Sudhakar M. Reddy
2012	J	`jnl`	Resolution of Diagnosis Based on Transition Faults. IEEE Trans. Very Large Scale Integr. Syst. Irith Pomeranz, Sudhakar M. Reddy
2012	—	`conf`	Session Summary III: Power-Aware Testing: Present and Future. Asian Test Symposium Xiaoqing Wen, Sudhakar M. Reddy
2012	—	`conf`	TSV and DFT cost aware circuit partitioning for 3D-SOCs. ISQED Amit Kumar, Sudhakar M. Reddy, Irith Pomeranz, Bernd Becker
2011	—	`conf`	Analysis of Resistive Bridge Defect Delay Behavior in the Presence of Process Variation. Asian Test Symposium Shida Zhong, S. Saqib Khursheed, Bashir M. Al-Hashimi, Sudhakar M. Reddy, Krishnendu Chakrabarty
2011	J	`jnl`	Broadside and Functional Broadside Tests for Partial-Scan Circuits. IEEE Trans. Very Large Scale Integr. Syst. Irith Pomeranz, Sudhakar M. Reddy
2011	—	`conf`	Diagnosis of Multiple Faults Based on Fault-Tuple Equivalence Tree. DFT Xun Tang, Wu-Tung Cheng, Ruifeng Guo, Huaxing Tang, Sudhakar M. Reddy
2011	—	`conf`	Fault diagnosis aware ATE assisted test response compaction. ASP-DAC J. M. Howard, Sudhakar M. Reddy, Irith Pomeranz, Bernd Becker
2011	J	`jnl`	Fixed-State Tests for Delay Faults in Scan Designs. IEEE Trans. Very Large Scale Integr. Syst. Irith Pomeranz, Sudhakar M. Reddy
2011	—	`conf`	Genetic algorithm based approach for segmented testing. DSN Workshops Xiaoxin Fan, Sudhakar M. Reddy, Senling Wang, Seiji Kajihara, Yasuo Sato
2011	A	`conf`	Hyper-graph based partitioning to reduce DFT cost for pre-bond 3D-IC testing. DATE Amit Kumar, Sudhakar M. Reddy, Irith Pomeranz, Bernd Becker
2011	J	`jnl`	Input Necessary Assignments for Testing of Path Delay Faults in Standard-Scan Circuits. IEEE Trans. Very Large Scale Integr. Syst. Irith Pomeranz, Sudhakar M. Reddy
2011	—	`conf`	Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-Gating. Asian Test Symposium Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Jakub Janicki
2011	A	`conf`	Low power compression utilizing clock-gating. ITC Janusz Rajski, Elham K. Moghaddam, Sudhakar M. Reddy
2011	C	`conf`	Max-Fill: A method to generate high quality delay tests. DDECS Xiaoxin Fan, Sudhakar M. Reddy, Irith Pomeranz
2011	J	`jnl`	Modeling and Mitigating Transient Errors in Logic Circuits. IEEE Trans. Dependable Secur. Comput. Ilia Polian, John P. Hayes, Sudhakar M. Reddy, Bernd Becker
2011	J	`jnl`	On Functional Broadside Tests With Functional Propagation Conditions. IEEE Trans. Very Large Scale Integr. Syst. Irith Pomeranz, Sudhakar M. Reddy
2011	—	`conf`	On Using Design Partitioning to Reduce Diagnosis Memory Footprint. Asian Test Symposium Xiaoxin Fan, Huaxing Tang, Sudhakar M. Reddy, Wu-Tung Cheng, Brady Benware
2011	J	`jnl`	Primary input cones based on test sequences in synchronous sequential circuits. IET Comput. Digit. Tech. Irith Pomeranz, Sudhakar M. Reddy
2011	J	`jnl`	Ranking of input cubes based on their lingering synchronisation effects and their use in random sequential test generation. IET Comput. Digit. Tech. Irith Pomeranz, Sudhakar M. Reddy
2011	J	`jnl`	Reducing the Storage Requirements of a Test Sequence by Using One or Two Background Vectors. IEEE Trans. Very Large Scale Integr. Syst. Irith Pomeranz, Sudhakar M. Reddy
2011	J	`jnl`	Reducing the switching activity of test sequences under transparent-scan. ACM Trans. Design Autom. Electr. Syst. Irith Pomeranz, Sudhakar M. Reddy
2011	J	`jnl`	Sizes of test sets for path delay faults using strong and weak non-robust tests. IET Comput. Digit. Tech. Irith Pomeranz, Sudhakar M. Reddy
2011	J	`jnl`	Static Test Data Volume Reduction Using Complementation or Modulo- M Addition. IEEE Trans. Very Large Scale Integr. Syst. Irith Pomeranz, Sudhakar M. Reddy
2011	J	`jnl`	Test Strength: A Quality Metric for Transition Fault Tests in Full-Scan Circuits. IEEE Trans. Very Large Scale Integr. Syst. Irith Pomeranz, Sudhakar M. Reddy
2011	J	`jnl`	Transparent-Segmented-Scan without the Routing Overhead of Segmented-Scan. J. Low Power Electron. Irith Pomeranz, Sudhakar M. Reddy
2011	J	`jnl`	Two-dimensional partially functional broadside tests. IET Comput. Digit. Tech. Irith Pomeranz, Sudhakar M. Reddy
2010	Misc	`conf`	At-speed scan test with low switching activity. VTS Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Mark Kassab
2010	—	`conf`	Deterministic broadside test generation for transition path delay faults. ACM Great Lakes Symposium on VLSI Bo Yao, Irith Pomeranz, Sudhakar M. Reddy
2010	—	`conf`	Diagnosis of Multiple Physical Defects Using Logic Fault Models. Asian Test Symposium Xun Tang, Wu-Tung Cheng, Ruifeng Guo, Sudhakar M. Reddy
2010	J	`jnl`	Diagnosis of path delay faults based on low-coverage tests. IET Comput. Digit. Tech. Irith Pomeranz, Sudhakar M. Reddy
2010	J	`jnl`	Equivalence, Dominance, and Similarity Relations between Fault Pairs and a Fault Pair Collapsing Process for Fault Diagnosis. IEEE Trans. Computers Irith Pomeranz, Sudhakar M. Reddy
2010	Misc	`conf`	Forming multi-cycle tests for delay faults by concatenating broadside tests. VTS Irith Pomeranz, Sudhakar M. Reddy
2010	—	`conf`	Functional and partially-functional skewed-load tests. ASP-DAC Irith Pomeranz, Sudhakar M. Reddy
2010	—	`conf`	Gradual Diagnostic Test Generation Based on the Structural Distance between Indistinguished Fault Pairs. DFT Irith Pomeranz, Sudhakar M. Reddy
2010	J	`jnl`	Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Scan-Based Tests. IEEE Trans. Very Large Scale Integr. Syst. Irith Pomeranz, Sudhakar M. Reddy
2010	J	`jnl`	Hazard-Based Detection Conditions for Improved Transition Path Delay Fault Coverage. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
2010	Misc	`conf`	Identifying Tests for Logic Fault Models Involving Subsets of Lines without Fault Enumeration. VLSI Design Irith Pomeranz, Sudhakar M. Reddy
2010	B	`conf`	Input test data volume reduction based on test vector chains. ETS Irith Pomeranz, Sudhakar M. Reddy
2010	A	`conf`	Low capture power at-speed test in EDT environment. ITC Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Xijiang Lin, Nilanjan Mukherjee, Mark Kassab
2010	A	`conf`	Multiple fault activation cycle tests for transistor stuck-open faults. ITC Narendra Devta-Prasanna, Arun Gunda, Sudhakar M. Reddy, Irith Pomeranz
2010	—	`conf`	On Bias in Transition Coverage of Test Sets for Path Delay Faults. Asian Test Symposium Irith Pomeranz, Sudhakar M. Reddy
2010	J	`jnl`	On Clustering of Undetectable Single Stuck-At Faults and Test Quality in Full-Scan Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
2010	J	`jnl`	On Test Generation With Test Vector Improvement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
2010	J	`jnl`	On Undetectable Faults and Fault Diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
2010	Misc	`conf`	On multiple bridging faults. VTS Irith Pomeranz, Sudhakar M. Reddy
2010	A	`conf`	On reset based functional broadside tests. DATE Irith Pomeranz, Sudhakar M. Reddy
2010	Misc	`conf`	Output-Dependent Diagnostic Test Generation. VLSI Design Irith Pomeranz, Sudhakar M. Reddy
2010	J	`jnl`	Path Selection for Transition Path Delay Faults. IEEE Trans. Very Large Scale Integr. Syst. Irith Pomeranz, Sudhakar M. Reddy
2010	A	`conf`	Reducing the storage requirements of a test sequence by using a background vector. DATE Irith Pomeranz, Sudhakar M. Reddy
2010	J	`jnl`	Robust Fault Models Where Undetectable Faults Imply Logic Redundancy. IEEE Trans. Very Large Scale Integr. Syst. Irith Pomeranz, Sudhakar M. Reddy
2010	C	`conf`	Selecting state variables for improved on-line testability through output response comparison of identical circuits. IOLTS Irith Pomeranz, Sudhakar M. Reddy
2010	J	`jnl`	Selection of a Fault Model for Fault Diagnosis Based on Unique Responses. IEEE Trans. Very Large Scale Integr. Syst. Irith Pomeranz, Sudhakar M. Reddy
2010	J	`jnl`	Static test compaction for diagnostic test sets of full-scan circuits. IET Comput. Digit. Tech. Irith Pomeranz, Sudhakar M. Reddy
2010	J	`jnl`	Switching Activity as a Test Compaction Heuristic for Transition Faults. IEEE Trans. Very Large Scale Integr. Syst. Irith Pomeranz, Sudhakar M. Reddy
2010	J	`jnl`	TOV: Sequential Test Generation by Ordering of Test Vectors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
2010	J	`jnl`	Test Sequences with Reduced and Increased Switching Activity. J. Low Power Electron. Irith Pomeranz, Sudhakar M. Reddy
2010	J	`jnl`	Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis. Int. J. Parallel Program. Alejandro Czutro, Ilia Polian, Matthew Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker
2009	A	`conf`	A scalable method for the generation of small test sets. DATE Santiago Remersaro, Janusz Rajski, Sudhakar M. Reddy, Irith Pomeranz
2009	—	`conf`	Definition and application of approximate necessary assignments. ACM Great Lakes Symposium on VLSI Irith Pomeranz, Sudhakar M. Reddy
2009	J	`jnl`	Definition and generation of partially-functional broadside tests. IET Comput. Digit. Tech. Irith Pomeranz, Sudhakar M. Reddy
2009	—	`conf`	Detectability of internal bridging faults in scan chains. ASP-DAC Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz
2009	J	`jnl`	Diagnosis of Multiple-Voltage Design With Bridge Defect. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. S. Saqib Khursheed, Bashir M. Al-Hashimi, Sudhakar M. Reddy, Peter Harrod
2009	J	`jnl`	Double-Single Stuck-at Faults: A Delay Fault Model for Synchronous Sequential Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
2009	—	`conf`	Dynamic Compaction in SAT-Based ATPG. Asian Test Symposium Alejandro Czutro, Ilia Polian, Piet Engelke, Sudhakar M. Reddy, Bernd Becker
2009	—	`conf`	Dynamic test compaction for a random test generation procedure with input cube avoidance. ASP-DAC Irith Pomeranz, Sudhakar M. Reddy
2009	—	`conf`	Fault Diagnosis under Transparent-Scan. Asian Test Symposium Irith Pomeranz, Sudhakar M. Reddy
2009	J	`jnl`	Forward-Looking Reverse Order Fault Simulation for n -Detection Test Sets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
2009	J	`jnl`	Functional Broadside Tests Under an Expanded Definition of Functional Operation Conditions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
2009	—	`conf`	Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Functional Test Sequences. DFT Irith Pomeranz, Sudhakar M. Reddy
2009	A	`conf`	Improving compressed test pattern generation for multiple scan chain failure diagnosis. DATE Xun Tang, Ruifeng Guo, Wu-Tung Cheng, Sudhakar M. Reddy
2009	—	`conf`	Improving the Detectability of Resistive Open Faults in Scan Cells. DFT Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz
2009	B	`conf`	Input Cubes with Lingering Synchronization Effects and their Use in Random Sequential Test Generation. ETS Irith Pomeranz, Sudhakar M. Reddy
2009	—	`conf`	Markov source based test length optimized SCAN-BIST architecture. ISQED Aftab Farooqi, Richard O. Gale, Sudhakar M. Reddy, Brian Nutter, Chris Monico
2009	—	`conf`	N-distinguishing Tests for Enhanced Defect Diagnosis. Asian Test Symposium Gang Chen, Janusz Rajski, Sudhakar M. Reddy, Irith Pomeranz
2009	—	`conf`	On Improving Diagnostic Test Generation for Scan Chain Failures. Asian Test Symposium Xun Tang, Ruifeng Guo, Wu-Tung Cheng, Sudhakar M. Reddy, Yu Huang
2009	—	`conf`	On-chip Generation of the Second Primary Input Vectors of Broadside Tests. DFT Irith Pomeranz, Sudhakar M. Reddy
2009	—	`conf`	Partitioned n-detection test generation. ACM Great Lakes Symposium on VLSI Irith Pomeranz, Sudhakar M. Reddy
2009	J	`jnl`	Process Variation-Aware Test for Resistive Bridges. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Urban Ingelsson, Bashir M. Al-Hashimi, S. Saqib Khursheed, Sudhakar M. Reddy, Peter Harrod
2009	J	`jnl`	Random Test Generation With Input Cube Avoidance. IEEE Trans. Very Large Scale Integr. Syst. Irith Pomeranz, Sudhakar M. Reddy
2009	J	`jnl`	Same/different fault dictionary: an extended pass/fail fault dictionary with improved diagnostic resolution. IET Comput. Digit. Tech. Irith Pomeranz, Sudhakar M. Reddy
2009	A	`conf`	Selection of a fault model for fault diagnosis based on unique responses. DATE Irith Pomeranz, Sudhakar M. Reddy
2009	J	`jnl`	Semiconcurrent Online Testing of Transition Faults through Output Response Comparison of Identical Circuits. IEEE Trans. Dependable Secur. Comput. Irith Pomeranz, Sudhakar M. Reddy
2009	—	`conf`	State persistence: a property for guiding test generation. ACM Great Lakes Symposium on VLSI Irith Pomeranz, Sudhakar M. Reddy
2009	Misc	`conf`	TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis. VLSI Design Alejandro Czutro, Ilia Polian, Matthew Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker
2009	J	`jnl`	Test compaction methods for transition faults under transparent-scan. IET Comput. Digit. Tech. Irith Pomeranz, Sudhakar M. Reddy
2009	J	`jnl`	Test vector chains for increasing the fault coverage and numbers of detections. IET Comput. Digit. Tech. Irith Pomeranz, Sudhakar M. Reddy
2009	Misc	`conf`	The Effect of Filling the Unspecified Values of a Test Set on the Test Set Quality. VLSI Design Irith Pomeranz, Sudhakar M. Reddy
2009	J	`jnl`	Using stuck-at tests to form scan-based tests for transition faults in standard-scan circuits. ACM Trans. Design Autom. Electr. Syst. Irith Pomeranz, Sudhakar M. Reddy
2008	A	`conf`	A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy. DATE Irith Pomeranz, Sudhakar M. Reddy
2008	A	`conf`	A Same/Different Fault Dictionary: An Extended Pass/Fail Fault Dictionary with Improved Diagnostic Resolution. DATE Irith Pomeranz, Sudhakar M. Reddy
2008	—	`conf`	ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume Reduction. DFT Santiago Remersaro, Janusz Rajski, Thomas Rinderknecht, Sudhakar M. Reddy, Irith Pomeranz
2008	C	`conf`	An Enhanced Logic BIST Architecture for Online Testing. IOLTS Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz
2008	B	`conf`	Bridge Defect Diagnosis for Multiple-Voltage Design. ETS S. Saqib Khursheed, Paul M. Rosinger, Bashir M. Al-Hashimi, Sudhakar M. Reddy, Peter Harrod
2008	—	`conf`	Circuit lines for guiding the generation of random test sequences for synchronous sequential circuits. ASP-DAC Irith Pomeranz, Sudhakar M. Reddy
2008	Misc	`conf`	Design-for-Testability for Improved Path Delay Fault Coverage of Critical Paths. VLSI Design Irith Pomeranz, Sudhakar M. Reddy
2008	Misc	`conf`	Design-for-Testability for Synchronous Sequential Circuits that Maintains Functional Switching Activity. VLSI Design Irith Pomeranz, Sudhakar M. Reddy
2008	A	`conf`	Detection of Internal Stuck-open Faults in Scan Chains. ITC Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz
2008	—	`conf`	Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells. DFT Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz
2008	Misc	`conf`	Expanded Definition of Functional Operation Conditions and its Effects on the Computation of Functional Broadside Tests. VTS Irith Pomeranz, Sudhakar M. Reddy
2008	J	`jnl`	Functional Broadside Tests with Minimum and Maximum Switching Activity. J. Low Power Electron. Irith Pomeranz, Sudhakar M. Reddy
2008	—	`conf`	Hyperactive Faults Dictionary to Increase Diagnosis Throughput. ATS Chen Liu, Wu-Tung Cheng, Huaxing Tang, Sudhakar M. Reddy, Wei Zou, Manish Sharma
2008	J	`jnl`	Improving the Transition Fault Coverage of Functional Broadside Tests by Observation Point Insertion. IEEE Trans. Very Large Scale Integr. Syst. Irith Pomeranz, Sudhakar M. Reddy
2008	Misc	`conf`	On Common-Mode Skewed-Load and Broadside Tests. VLSI Design Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu
2008	J	`jnl`	On Complete Functional Broadside Tests for Transition Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy
2008	J	`jnl`	On Detection of Bridge Defects with Stuck-at Tests. IEICE Trans. Inf. Syst. Kohei Miyase, Kenta Terashima, Xiaoqing Wen, Seiji Kajihara, Sudhakar M. Reddy
2008	—	`conf`	On Reducing Circuit Malfunctions Caused by Soft Errors. DFT Ilia Polian, Sudhakar M. Reddy, Irith Pomeranz, Xun Tang, Bernd Becker
2008	A*	`conf`	On tests to detect via opens in digital CMOS circuits. DAC Sudhakar M. Reddy, Irith Pomeranz, Chen Liu
2008	Misc	`conf`	On the Detectability of Scan Chain Internal Faults - An Industrial Case Study. VTS Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz
2008	J	`jnl`	On the Saturation of n-Detection Test Generation by Different Definitions With Increased n. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
2008	J	`jnl`	Primary Input Vectors to Avoid in Random Test Sequences for Synchronous Sequential Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
2008	B	`conf`	Safe Fault Collapsing Based on Dominance Relations. ETS Irith Pomeranz, Sudhakar M. Reddy
2008	—	`conf`	Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors. ISVLSI Ilia Polian, Sudhakar M. Reddy, Bernd Becker
2008	J	`jnl`	Scan-Based Delay Test Types and Their Effect on Power Dissipation During Test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
2008	Misc	`conf`	Synthesis for Broadside Testability of Transition Faults. VTS Irith Pomeranz, Sudhakar M. Reddy
2008	—	`conf`	Test vector chains for increased targeted and untargeted fault coverage. ASP-DAC Irith Pomeranz, Sudhakar M. Reddy
2008	J	`jnl`	Transition Path Delay Faults: A New Path Delay Fault Model for Small and Large Delay Defects. IEEE Trans. Very Large Scale Integr. Syst. Irith Pomeranz, Sudhakar M. Reddy
2008	J	`jnl`	Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
2007	—	`conf`	A-Diagnosis: A Complement to Z-Diagnosis. DFT Irith Pomeranz, Sudhakar M. Reddy
2007	Misc	`conf`	Autoscan-Invert: An Improved Scan Design without External Scan Inputs or Outputs. VTS Irith Pomeranz, Sudhakar M. Reddy
2007	B	`conf`	Diagnostic Test Generation Based on Subsets of Faults. ETS Irith Pomeranz, Sudhakar M. Reddy
2007	—	`conf`	Diagnostic Test Generation Targeting Equivalence Classes. ATS Irith Pomeranz, Sudhakar M. Reddy
2007	J	`jnl`	Effectiveness of scan-based delay fault tests in diagnosis of transition faults. IET Comput. Digit. Tech. Irith Pomeranz, Sudhakar M. Reddy
2007	—	`conf`	Enhanced Broadside Testing for Improved Transition Fault Coverage. ATS Irith Pomeranz, Sudhakar M. Reddy
2007	J	`jnl`	Enhancing delay fault coverage through low-power segmented scan. IET Comput. Digit. Tech. Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Bashir M. Al-Hashimi
2007	Misc	`conf`	Equivalence and Dominance Relations Between Fault Pairs and Their Use in Fault Pair Collapsing for Fault Diagnosis. VLSI Design Irith Pomeranz, Sudhakar M. Reddy
2007	A	`conf`	Faster defect localization in nanometer technology based on defective cell diagnosis. ITC Manish Sharma, Wu-Tung Cheng, Ting-Pu Tai, Y. S. Cheng, Will Hsu, Chen Liu, Sudhakar M. Reddy, Albert Mann
2007	J	`jnl`	Forming N-detection test sets without test generation. ACM Trans. Design Autom. Electr. Syst. Irith Pomeranz, Sudhakar M. Reddy
2007	Misc	`conf`	Functional Broadside Tests with Different Levels of Reachability. VLSI Design Irith Pomeranz, Sudhakar M. Reddy
2007	J	`jnl`	Generation of Broadside Transition-Fault Test Sets That Detect Four-Way Bridging Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
2007	A	`conf`	Interconnect open defect diagnosis with minimal physical information. ITC Chen Liu, Wei Zou, Sudhakar M. Reddy, Wu-Tung Cheng, Manish Sharma, Huaxing Tang
2007	Misc	`conf`	Low Shift and Capture Power Scan Tests. VLSI Design Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski
2007	A	`conf`	On test generation by input cube avoidance. DATE Irith Pomeranz, Sudhakar M. Reddy
2007	A	`conf`	On the saturation of n-detection test sets with increased n. ITC Irith Pomeranz, Sudhakar M. Reddy
2007	—	`conf`	Reducing the Energy Consumption in Fault-Tolerant Distributed Embedded Systems with Time-Constraint. ISQED Yuan Cai, Sudhakar M. Reddy, Bashir M. Al-Hashimi
2007	J	`jnl`	Scan-Based Tests with Low Switching Activity. IEEE Des. Test Comput. Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski
2007	—	`conf`	Semi-Concurrent On-Line Testing of Transition Faults Through Output Response Comparison of Identical Circuits. DFT Irith Pomeranz, Sudhakar M. Reddy
2007	Misc	`conf`	Speeding Up Effect-Cause Defect Diagnosis Using a Small Dictionary. VTS Wei Zou, Wu-Tung Cheng, Sudhakar M. Reddy, Huaxing Tang
2007	J	`jnl`	The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits CoRR Irith Pomeranz, Sudhakar M. Reddy
2007	—	`conf`	Warning: Launch off Shift Tests for Delay Faults May Contribute to Test Escapes. ASP-DAC Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz
2007	J	`jnl`	Workload-ahead-driven online energy minimization techniques for battery-powered embedded systems with time-constraints. ACM Trans. Design Autom. Electr. Syst. Yuan Cai, Marcus T. Schmitz, Bashir M. Al-Hashimi, Sudhakar M. Reddy
2007	J	`jnl`	Worst-Case and Average-Case Analysis of n-Detection Test Sets CoRR Irith Pomeranz, Sudhakar M. Reddy
2007	J	`jnl`	Worst-case and average-case analysis of n-detection test sets and test generation strategies. IET Comput. Digit. Tech. Irith Pomeranz, Sudhakar M. Reddy
2007	J	`jnl`	z-Diagnosis: A Framework for Diagnostic Fault Simulation and Test Generation Utilizing Subsets of Outputs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy, Srikanth Venkataraman
2006	—	`conf`	A Field Programmable Memory BIST Architecture Supporting Algorithms with Multiple Nested Loops. ATS Xiaogang Du, Nilanjan Mukherjee, Chris Hill, Wu-Tung Cheng, Sudhakar M. Reddy
2006	C	`conf`	A Partitioning Technique for Identification of Error-Capturing Scan Cells in Scan-BIST. IOLTS Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz
2006	Misc	`conf`	A Test Generation Procedure for Avoiding the Detection of Functionally Redundant Transition Faults. VTS Hangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy
2006	B	`conf`	A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults. ETS Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz
2006	A	`conf`	A delay fault model for at-speed fault simulation and test generation. ICCAD Irith Pomeranz, Sudhakar M. Reddy
2006	A*	`conf`	A test pattern ordering algorithm for diagnosis with truncated fail data. DAC Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski
2006	—	`conf`	Cache size selection for performance, energy and reliability of time-constrained systems. ASP-DAC Yuan Cai, Marcus T. Schmitz, Alireza Ejlali, Bashir M. Al-Hashimi, Sudhakar M. Reddy
2006	Misc	`conf`	Dominance Based Analysis for Large Volume Production Fail Diagnosis. VTS Bharath Seshadri, Irith Pomeranz, Srikanth Venkataraman, M. Enamul Amyeen, Sudhakar M. Reddy
2006	B	`conf`	Enhancing Delay Fault Coverage through Low Power Segmented Scan. ETS Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Bashir M. Al-Hashimi
2006	B	`conf`	Fault Collapsing for Transition Faults Using Extended Transition Faults. ETS Irith Pomeranz, Sudhakar M. Reddy
2006	A	`conf`	Fault Detection by Output Response Comparison of Identical Circuits Using Half-Frequency Compatible Sequences. ITC Irith Pomeranz, Sudhakar M. Reddy
2006	J	`jnl`	Generation of Functional Broadside Tests for Transition Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
2006	A	`conf`	Generation of broadside transition fault test sets that detect four-way bridging faults. DATE Irith Pomeranz, Sudhakar M. Reddy
2006	J	`jnl`	Improved n-Detection Test Sequences Under Transparent Scan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
2006	—	`conf`	Interconnect Open Defect Diagnosis with Physical Information. ATS Wei Zou, Wu-Tung Cheng, Sudhakar M. Reddy
2006	Misc	`conf`	New Procedures to Identify Redundant Stuck-At Faults and Removal of Redundant Logic. VLSI Design Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski
2006	J	`jnl`	On Generating Tests that Avoid the Detection of Redundant Faults in Synchronous Sequential Circuits with Full Scan. IEEE Trans. Computers Irith Pomeranz, Sudhakar M. Reddy
2006	Misc	`conf`	On Methods to Improve Location Based Logic Diagnosis. VLSI Design Wei Zou, Wu-Tung Cheng, Sudhakar M. Reddy, Huaxing Tang
2006	—	`conf`	On the Replacement of Scan Chain Inputs by Primary Input Vectors. ATS Irith Pomeranz, Sudhakar M. Reddy
2006	—	`conf`	On the Use of Functional Test Generation in Diagnostic Test Generation for Synchronous Sequential Circuits. V&D@FLoC Irith Pomeranz, Sudhakar M. Reddy
2006	A	`conf`	Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs. ITC Santiago Remersaro, Xijiang Lin, Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski
2006	Misc	`conf`	Scan Tests with Multiple Fault Activation Cycles for Delay Faults. VTS Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski
2006	J	`jnl`	Scan-BIST based on transition probabilities for circuits with single and multiple scan chains. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
2006	—	`conf`	Scan-Based Delay Fault Tests for Diagnosis of Transition Faults. DFT Irith Pomeranz, Sudhakar M. Reddy
2006	—	`conf`	Test Generation for Open Defects in CMOS Circuits. DFT Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz
2006	A	`conf`	Test compaction for transition faults under transparent-scan. DATE Irith Pomeranz, Sudhakar M. Reddy
2006	Misc	`conf`	The Cut Delay Fault Model for Guiding the Generation of n-Detection Test Sets for Transition Faults. VLSI Design Irith Pomeranz, Sudhakar M. Reddy
2006	J	`jnl`	Transparent DFT: a design for testability and test generation approach for synchronous sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
2006	J	`jnl`	Using Dummy Bridging Faults to Define Reduced Sets of Target Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
2005	C	`conf`	A Novel Method of Improving Transition Delay Fault Coverage Using Multiple Scan Enable Signals. ICCD Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz
2005	B	`conf`	A unified fault model and test generation procedure for interconnect opens and bridges. ETS Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Piet Engelke, Bernd Becker
2005	J	`jnl`	Autoscan: a scan design without external scan inputs or outputs. IEEE Trans. Very Large Scale Integr. Syst. Irith Pomeranz, Sudhakar M. Reddy
2005	—	`conf`	Battery-aware dynamic voltage scaling in multiprocessor embedded system. ISCAS (1) Yuan Cai, Sudhakar M. Reddy, Irith Pomeranz, Bashir M. Al-Hashimi
2005	—	`conf`	Bridge Defect Diagnosis with Physical Information. Asian Test Symposium Wei Zou, Wu-Tung Cheng, Sudhakar M. Reddy
2005	—	`conf`	Circuit Independent Weighted Pseudo-Random BIST Pattern Generator. Asian Test Symposium Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz
2005	J	`jnl`	Concurrent Online Testing of Identical Circuits Using Nonidentical Input Vectors. IEEE Trans. Dependable Secur. Comput. Irith Pomeranz, Sudhakar M. Reddy
2005	A	`conf`	Defect Aware Test Patterns. DATE Huaxing Tang, Gang Chen, Sudhakar M. Reddy, Chen Wang, Janusz Rajski, Irith Pomeranz
2005	Misc	`conf`	Distance Restricted Scan Chain Reordering to Enhance Delay Fault Coverage. VLSI Design Wei Li, Seongmoon Wang, Srimat T. Chakradhar, Sudhakar M. Reddy
2005	—	`conf`	Dynamic Test Compaction for Bridging Faults. ISQED Irith Pomeranz, Sudhakar M. Reddy
2005	—	`conf`	Fault Diagnosis and Fault Model Aliasing. ISVLSI Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy
2005	J	`jnl`	Finite memory test response compactors for embedded test applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Janusz Rajski, Jerzy Tyszer, Chen Wang, Sudhakar M. Reddy
2005	A	`conf`	Forming N-detection test sets from one-detection test sets without test generation. ITC Irith Pomeranz, Sudhakar M. Reddy
2005	—	`conf`	Full-speed field programmable memory BIST supporting multi-level looping. MTDT Xiaogang Du, Nilanjan Mukherjee, Wu-Tung Cheng, Sudhakar M. Reddy
2005	A	`conf`	Full-speed field-programmable memory BIST architecture. ITC Xiaogang Du, Nilanjan Mukherjee, Wu-Tung Cheng, Sudhakar M. Reddy
2005	—	`conf`	Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch Transitions. Asian Test Symposium Narendra Devta-Prasanna, Sudhakar M. Reddy, Arun Gunda, P. Krishnamurthy, Irith Pomeranz
2005	A	`conf`	Methods for improving transition delay fault coverage using broadside tests. ITC Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz
2005	Misc	`conf`	On Efficient X-Handling Using a Selective Compaction Scheme to Achieve High Test Response Compaction Ratios. VLSI Design Huaxing Tang, Chen Wang, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Irith Pomeranz
2005	—	`conf`	On Generating Pseudo-Functional Delay Fault Tests for Scan Designs. DFT Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz
2005	—	`conf`	On Improving Defect Coverage of Stuck-at Fault Tests. Asian Test Symposium Kohei Miyase, Kenta Terashima, Seiji Kajihara, Xiaoqing Wen, Sudhakar M. Reddy
2005	—	`conf`	On Reducing Peak Current and Power during Test. ISVLSI Wei Li, Sudhakar M. Reddy, Irith Pomeranz
2005	J	`jnl`	On fault equivalence, fault dominance, and incompletely specified test sets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
2005	J	`jnl`	On masking of redundant faults in synchronous sequential circuits with design-for-testability logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
2005	J	`jnl`	On reducing test application time for scan circuits using limited scan operations and transfer sequences. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yonsang Cho, Irith Pomeranz, Sudhakar M. Reddy
2005	B	`conf`	Path-oriented transition fault test generation considering operating conditions. ETS Bharath Seshadri, Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu
2005	—	`conf`	Recovery During Concurrent On-Line Testing of Identical Circuits. DFT Irith Pomeranz, Sudhakar M. Reddy
2005	A	`conf`	The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits. DATE Irith Pomeranz, Sudhakar M. Reddy
2005	Misc	`conf`	Tuple Detection for Path Delay Faults: A Method for Improving Test Set Quality. VLSI Design Irith Pomeranz, Sudhakar M. Reddy
2005	B	`conf`	Using dummy bridging faults to define a reduced set of target faults. ETS Irith Pomeranz, Sudhakar M. Reddy
2005	A	`conf`	Worst-Case and Average-Case Analysis of n-Detection Test Sets. DATE Irith Pomeranz, Sudhakar M. Reddy
2004	J	`jnl`	A Measure of Quality for n-Detection Test Sets. IEEE Trans. Computers Irith Pomeranz, Sudhakar M. Reddy
2004	—	`conf`	A Postprocessing Procedure of Test Enrichment for Path Delay Faults. Asian Test Symposium Irith Pomeranz, Sudhakar M. Reddy
2004	Misc	`conf`	At-Speed Built-in Self-Repair Analyzer for Embedded Word-Oriented Memories. VLSI Design Xiaogang Du, Sudhakar M. Reddy, Wu-Tung Cheng, Joseph Rayhawk, Nilanjan Mukherjee
2004	—	`conf`	Concurrent On-Line Testing of Identical Circuits Through Output Comparison Using Non-Identical Input Vectors. DFT Irith Pomeranz, Sudhakar M. Reddy
2004	Misc	`conf`	Defect Diagnosis Based on Pattern-Dependent Stuck-At Faults. VLSI Design Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy, M. Enamul Amyeen
2004	J	`jnl`	Don't Care Identification and Statistical Encoding for Test Data Compression. IEICE Trans. Inf. Syst. Seiji Kajihara, Kenjiro Taniguchi, Kohei Miyase, Irith Pomeranz, Sudhakar M. Reddy
2004	B	`conf`	Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values. ETS Seiji Kajihara, Kewal K. Saluja, Sudhakar M. Reddy
2004	J	`jnl`	Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations. IEEE Trans. Very Large Scale Integr. Syst. Irith Pomeranz, Sudhakar M. Reddy
2004	A	`conf`	Level of Similarity: A Metric for Fault Collapsing. DATE Irith Pomeranz, Sudhakar M. Reddy
2004	J	`jnl`	Masking of Unknown Output Values during Output Response Compression byUsing Comparison Units. IEEE Trans. Computers Irith Pomeranz, Sandip Kundu, Sudhakar M. Reddy
2004	Misc	`conf`	Memory BIST Using ESP. VTS Xiaogang Du, Sudhakar M. Reddy, Don E. Ross, Wu-Tung Cheng, Joseph Rayhawk
2004	—	`conf`	Multiple Scan Tree Design with Test Vector Modification. Asian Test Symposium Kohei Miyase, Seiji Kajihara, Sudhakar M. Reddy
2004	Misc	`conf`	On Interconnecting Circuits with Multiple Scan Chains for Improved Test Data Compression. VLSI Design Irith Pomeranz, Sudhakar M. Reddy
2004	J	`jnl`	On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential Circuit. IEEE Trans. Computers Irith Pomeranz, Sudhakar M. Reddy
2004	C	`conf`	On Undetectable Faults in Partial Scan Circuits Using Transparent-Scan. ICCD Irith Pomeranz, Sudhakar M. Reddy
2004	A*	`conf`	On test generation for transition faults with minimized peak power dissipation. DAC Wei Li, Sudhakar M. Reddy, Irith Pomeranz
2004	J	`jnl`	On the characterization and efficient computation of hard-to-detect bridging faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu
2004	—	`conf`	Properties of Maximally Dominating Faults. Asian Test Symposium Irith Pomeranz, Sudhakar M. Reddy
2004	—	`conf`	Reducing Fault Latency in Concurrent On-Line Testing by Using Checking Functions over Internal Lines. DFT Irith Pomeranz, Sudhakar M. Reddy
2004	—	`conf`	Scan BIST Targeting Transition Faults Using a Markov Source. ISQED Hangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy
2004	J	`jnl`	Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Nonscan Input Sequences and a Lower Bound on the Number of Tests. IEEE Trans. Computers Irith Pomeranz, Sudhakar M. Reddy
2004	—	`conf`	Test Application Time Reduction for Scan Circuits Using Limited Scan Operations. ISQED Yonsang Cho, Irith Pomeranz, Sudhakar M. Reddy
2004	J	`jnl`	Vector-restoration-based static compaction using random initial omission. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
2004	—	`conf`	Weighted Pseudo-Random BIST for N-Detection of Single Stuck-at Faults. Asian Test Symposium Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz
2004	A	`conf`	Z-DFD: Design-for-Diagnosability Based on the Concept of Z-Detection. ITC Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy
2004	A	`conf`	Z-Sets and Z-Detections: Circuit Characteristics that Simplify Fault Diagnosis. DATE Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy, Bharath Seshadri
2003	—	`conf`	A DFT Approach for Path Delay Faults in Interconnected Circuits. Asian Test Symposium Irith Pomeranz, Sudhakar M. Reddy
2003	J	`jnl`	A Low Power Pseudo-Random BIST Technique. J. Electron. Test. Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz
2003	A	`conf`	A New Approach to Test Generation and Test Compaction for Scan Circuits. DATE Irith Pomeranz, Sudhakar M. Reddy
2003	Misc	`conf`	A Test Interface for Built-In Test of Non-Isolated Scanned Cores. VTS Irith Pomeranz, Sudhakar M. Reddy, Yervant Zorian
2003	A*	`conf`	A scan BIST generation method using a markov source and partial bit-fixing. DAC Wei Li, Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz
2003	C	`conf`	An Improved Markov Source Design for Scan BIST. IOLTS Chaowen Yu, Wei Li, Sudhakar M. Reddy, Irith Pomeranz
2003	Misc	`conf`	Application of Saluja-Karpovsky Compactors to Test Responses with Many Unknowns. VTS Janak H. Patel, Steven S. Lumetta, Sudhakar M. Reddy
2003	A	`conf`	Convolutional Compaction of Test Responses. ITC Janusz Rajski, Jerzy Tyszer, Chen Wang, Sudhakar M. Reddy
2003	A	`conf`	Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST. DATE Ilia Polian, Bernd Becker, Sudhakar M. Reddy
2003	Misc	`conf`	GALLOP: Genetic Algorithm based Low Power FSM Synthesis by Simultaneous Partitioning and State Assignment. VLSI Design Ganesh Venkataraman, Sudhakar M. Reddy, Irith Pomeranz
2003	A	`conf`	On Application of Output Masking to Undetectable Faults in Synchronous Sequential Circuits with Design-for-Testability Logic. ICCAD Irith Pomeranz, Sudhakar M. Reddy
2003	A	`conf`	On Compacting Test Response Data Containing Unknown Values. ICCAD Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Jerzy Tyszer
2003	Misc	`conf`	On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential Circuit. VTS Irith Pomeranz, Sudhakar M. Reddy
2003	A	`conf`	On Reducing Test Data Volume and Test Application Time for Multiple Scan Chain Designs. ITC Huaxing Tang, Sudhakar M. Reddy, Irith Pomeranz
2003	J	`jnl`	On Selecting Testable Paths in Scan Designs. J. Electron. Test. Yun Shao, Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara
2003	—	`conf`	On path selection for delay fault testing considering operating conditions [logic IC testing]. ETW Bharath Seshadri, Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu
2003	A*	`conf`	On test data compression and n-detection test sets. DAC Irith Pomeranz, Sudhakar M. Reddy
2003	J	`jnl`	On test data volume reduction for multiple scan chain designs. ACM Trans. Design Autom. Electr. Syst. Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz
2003	A	`conf`	On the Characterization of Hard-to-Detect Bridging Faults. DATE Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu
2003	A	`conf`	On-chip Compression of Output Responses with Unknown Values Using LFSR Reseeding. ITC Masao Naruse, Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu
2003	—	`conf`	Optimizing SOC Test Resources Using Dual Sequences. VLSI-SoC (Selected Papers) Wei Zou, Chris C. N. Chu, Sudhakar M. Reddy, Irith Pomeranz
2003	C	`conf`	Optimizing SOC Test Resources using Dual Sequences. VLSI-SOC Wei Zou, Chris Chu, Sudhakar M. Reddy, Irith Pomeranz
2003	J	`jnl`	PROPTEST: a property-based test generator for synchronous sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz
2003	C	`conf`	Procedures for Identifying Untestable and Redundant Transition Faults in Synchronous Sequential Circuits. ICCD Gang Chen, Sudhakar M. Reddy, Irith Pomeranz
2003	J	`jnl`	Reverse-order-restoration-based static test compaction for synchronous sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz
2003	Misc	`conf`	SOC Test Scheduling Using Simulated Annealing. VTS Wei Zou, Sudhakar M. Reddy, Irith Pomeranz, Yu Huang
2003	—	`conf`	Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets. ISQED Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Sudhakar M. Reddy
2003	Misc	`conf`	Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Non-Scan Sequential Test Sequences. VLSI Design Irith Pomeranz, Sudhakar M. Reddy
2003	C	`conf`	Static Test Compaction for Multiple Full-Scan Circuits. ICCD Irith Pomeranz, Sudhakar M. Reddy
2003	A	`conf`	Statistical Diagnosis for Intermittent Scan Chain Hold-Time Fault. ITC Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Cheng-Ju Hsieh, Yu-Ting Hung
2003	A	`conf`	Test Data Compression Based on Output Dependence. DATE Irith Pomeranz, Sudhakar M. Reddy
2003	—	`conf`	Test Data Volume Reduction by Test Data Realignment. Asian Test Symposium Irith Pomeranz, Sudhakar M. Reddy
2003	J	`jnl`	Test data compression based on input-output dependence. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
2003	J	`jnl`	Test enrichment for path delay faults using multiple sets of target faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
2003	—	`conf`	Testing Delay Faults in Embedded CAMs. Asian Test Symposium Xiaogang Du, Sudhakar M. Reddy, Joseph Rayhawk, Wu-Tung Cheng
2003	J	`jnl`	Theorems for identifying undetectable faults in partial-scan circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
2003	J	`jnl`	Transparent scan: a new approach to test generation and test compaction for scan circuits that incorporates limited scan operations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
2002	C	`conf`	A Low Power Pseudo-Random BIST Technique. ICCD Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz
2002	—	`conf`	A Low Power Pseudo-Random BIST Technique. IOLTW Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz
2002	—	`conf`	A Method of Static Test Compaction Based on Don't Care Identification. DELTA Kohei Miyase, Seiji Kajihara, Sudhakar M. Reddy
2002	—	`conf`	A Partitioning and Storage Based Built-In Test Pattern Generation Method for Delay Faults in Scan Circuits. Asian Test Symposium Irith Pomeranz, Sudhakar M. Reddy
2002	—	`conf`	A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits. ASP-DAC/VLSI Design Irith Pomeranz, Sudhakar M. Reddy
2002	J	`jnl`	A Storage-Based Built-In Test Pattern Generation Method for Scan Circuits Based on Partitioning and Reduction of a Precomputed Test Set. IEEE Trans. Computers Irith Pomeranz, Sudhakar M. Reddy
2002	J	`jnl`	Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Input Sequences Using Single and Multiple Fault Detection Times. IEEE Trans. Computers Irith Pomeranz, Sudhakar M. Reddy
2002	A	`conf`	Conflict driven techniques for improving deterministic test pattern generation. ICCAD Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski
2002	—	`conf`	Constraint Driven Pin Mapping for Concurrent SOC Testing. ASP-DAC/VLSI Design Yu Huang, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan, Yanping Zhang, Wu-Tung Cheng, Sudhakar M. Reddy
2002	—	`conf`	Core - Clustering Based SOC Test Scheduling Optimization. Asian Test Symposium Yu Huang, Sudhakar M. Reddy, Wu-Tung Cheng
2002	C	`conf`	Don't-Care Identification on Specific Bits of Test Patterns. ICCD Kohei Miyase, Seiji Kajihara, Irith Pomeranz, Sudhakar M. Reddy
2002	J	`jnl`	Enumeration of Test Sequences in Increasing Chronological Order to Improve the Levels of Compaction Achieved by Vector Omission. IEEE Trans. Computers Irith Pomeranz, Sudhakar M. Reddy
2002	A	`conf`	Finding a Common Fault Response for Diagnosis during Silicon Debug. DATE Irith Pomeranz, Janusz Rajski, Sudhakar M. Reddy
2002	—	`conf`	Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST. ASP-DAC/VLSI Design Nadir Z. Basturkmen, Sudhakar M. Reddy, Janusz Rajski
2002	—	`conf`	Improving the Efficiency of Static Compaction Based on Chronological Order Enumeration of Test Sequences. Asian Test Symposium Irith Pomeranz, Sudhakar M. Reddy
2002	J	`jnl`	On Concurrent Test of Core-Based SOC Design. J. Electron. Test. Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy
2002	—	`conf`	On Generating High Quality Tests for Transition Faults. Asian Test Symposium Yun Shao, Irith Pomeranz, Sudhakar M. Reddy
2002	Misc	`conf`	On Test Data Volume Reduction for Multiple Scan Chain Designs. VTS Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz
2002	A	`conf`	On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout. ITC Sudhakar M. Reddy, Irith Pomeranz, Huaxing Tang, Seiji Kajihara, Kozo Kinoshita
2002	A*	`conf`	On output response compression in the presence of unknown output values. DAC Irith Pomeranz, Sandip Kundu, Sudhakar M. Reddy
2002	—	`conf`	On selecting testable paths in scan designs. ETW Yun Shao, Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara
2002	C	`conf`	On the Coverage of Delay Faults in Scan Designs with Multiple Scan Chains. ICCD Irith Pomeranz, Sudhakar M. Reddy
2002	A	`conf`	On undetectable faults in partial scan circuits. ICCAD Irith Pomeranz, Sudhakar M. Reddy
2002	A	`conf`	Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm. ITC Yu Huang, Sudhakar M. Reddy, Wu-Tung Cheng, Paul Reuter, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan
2002	—	`conf`	Path Delay Fault Test Generation for Standard Scan Designs Using State Tuples. ASP-DAC/VLSI Design Yun Shao, Irith Pomeranz, Sudhakar M. Reddy
2002	—	`conf`	Properties of Output Sequences and their Use in Guiding Property-Based Test Generation for Synchronous Sequential Circuits. DELTA Irith Pomeranz, Sudhakar M. Reddy
2002	J	`jnl`	Property-based test generation for scan designs and the effects ofthe test application scheme and scan selection on the number ofdetectable faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
2002	A	`conf`	Pseudo Random Patterns Using Markov Sources for Scan BIST. ITC Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz
2002	J	`jnl`	Synthesis of Scan Chains for Netlist Descriptions at RT-Level. J. Electron. Test. Yu Huang, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Wu-Tung Cheng, Sudhakar M. Reddy
2002	—	`conf`	Test Data Compression Using Don't-Care Identification and Statistical Encoding. DELTA Seiji Kajihara, Kenjiro Taniguchi, Irith Pomeranz, Sudhakar M. Reddy
2002	—	`conf`	Test Data Compression Using Don?t-Care Identification and Statistical Encoding. Asian Test Symposium Seiji Kajihara, Kenjiro Taniguchi, Kohei Miyase, Irith Pomeranz, Sudhakar M. Reddy
2002	A	`conf`	Test Enrichment for Path Delay Faults Using Multiple Sets of Target Faults. DATE Irith Pomeranz, Sudhakar M. Reddy
2002	J	`jnl`	Test compaction for at-speed testing of scan circuits based onnonscan test. sequences and removal of transfer sequences. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
2002	J	`jnl`	n-pass n-detection fault simulation and its applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
2001	C	`conf`	A Partitioning and Storage Based Built-in Test Pattern Generation Method for Synchronous Sequential Circuits. ICCD Irith Pomeranz, Sudhakar M. Reddy
2001	—	`conf`	A Postprocessing Procedure to Reduce the Number of Different Test Lengths in a Test Set for Scan Circuits. Asian Test Symposium Irith Pomeranz, Sudhakar M. Reddy
2001	J	`jnl`	A built-in self-test method for diagnosis of synchronous sequential circuits. IEEE Trans. Very Large Scale Integr. Syst. Irith Pomeranz, Sudhakar M. Reddy
2001	A	`conf`	A method to enhance the fault coverage obtained by output response comparison of identical circuits. ITC Irith Pomeranz, Sudhakar M. Reddy
2001	A*	`conf`	An Approach to Test Compaction for Scan Circuits that Enhances At-Speed Testing. DAC Irith Pomeranz, Sudhakar M. Reddy
2001	—	`conf`	An Efficient Method to Identify Untestable Path Delay Faults. Asian Test Symposium Yun Shao, Sudhakar M. Reddy, Seiji Kajihara, Irith Pomeranz
2001	C	`conf`	COREL: A Dynamic Compaction Procedure for Synchronous Sequential Circuits with Repetition and Local Static Compaction. ICCD Irith Pomeranz, Sudhakar M. Reddy
2001	A	`conf`	Definitions of the numbers of detections of target faults and their effectiveness in guiding test generation for high defect coverage. DATE Irith Pomeranz, Sudhakar M. Reddy
2001	J	`jnl`	Design-for-testability to achieve complete coverage of delay faults in standard full scan circuits. J. Syst. Archit. Irith Pomeranz, Sudhakar M. Reddy
2001	—	`conf`	Effect of RTL coding style on testability. CICC Yu Huang, Chien-Chung Tsai, Nilanjan Mukherhee, Wu-Tung Cheng, Sudhakar M. Reddy
2001	—	`conf`	Estimating the relative single stuck-at fault coverage of test sets for a combinational logic block from its functional description. HLDVT Irith Pomeranz, Sudhakar M. Reddy
2001	—	`conf`	Experimental Results of Forward-Looking Reverse Order Fault Simulation on Industrial Circuits with Scan. Asian Test Symposium Irith Pomeranz, Sudhakar M. Reddy, Xijiang Lin
2001	J	`jnl`	Forward-looking fault simulation for improved static compaction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
2001	—	`conf`	ITEM: an iterative improvement test generation procedure for synchronous sequential circuits. ACM Great Lakes Symposium on VLSI Irith Pomeranz, Sudhakar M. Reddy
2001	Misc	`conf`	On Improving Static Test Compaction for Sequential Circuits. VLSI Design Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy
2001	—	`conf`	On Improving a Fault Simulation Based Test Generator for Synchronous Sequential Circuits. Asian Test Symposium Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz
2001	A	`conf`	On RTL scan design. ITC Yu Huang, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Dan Devries, Wu-Tung Cheng, Sudhakar M. Reddy
2001	J	`jnl`	On diagnosis and diagnostic test generation for pattern-dependenttransition faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
2001	A	`conf`	On improving the stuck-at fault coverage of functional test sequences by using limited-scan operations. ITC Irith Pomeranz, Sudhakar M. Reddy
2001	A	`conf`	On static test compaction and test pattern ordering for scan designs. ITC Xijiang Lin, Janusz Rajski, Irith Pomeranz, Sudhakar M. Reddy
2001	Misc	`conf`	On the Use of Fault Dominance in n-Detection Test Generation. VTS Irith Pomeranz, Sudhakar M. Reddy
2001	A	`conf`	REDI: An Efficient Fault Oriented Procedure to Identify Redundant Faults in Combinational Logic Circuits. ICCAD Chen Wang, Irith Pomeranz, Sudhakar M. Reddy
2001	—	`conf`	Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D. Asian Test Symposium Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy
2001	J	`jnl`	Resynthesis of combinational logic circuits for improved path delay fault testability using comparison units. IEEE Trans. Very Large Scale Integr. Syst. Irith Pomeranz, Sudhakar M. Reddy
2001	A	`conf`	Sequence reordering to improve the levels of compaction achievable by static compaction procedures. DATE Irith Pomeranz, Sudhakar M. Reddy
2001	J	`jnl`	Vector replacement to improve static-test compaction forsynchronous sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
2000	J	`jnl`	A diagnostic test generation procedure based on test elimination byvector omission for synchronous sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
2000	A	`conf`	Built-In Generation of Weighted Test Sequences for Synchronous Sequential Circuits. DATE Irith Pomeranz, Sudhakar M. Reddy
2000	—	`conf`	Enhanced untestable path analysis using edge graphs. Asian Test Symposium Seiji Kajihara, Takashi Shimono, Irith Pomeranz, Sudhakar M. Reddy
2000	C	`conf`	Fault diagnosis based on parameters of output responses. PRDC Irith Pomeranz, Sudhakar M. Reddy
2000	A	`conf`	Functional Test Generation for Full Scan Circuits. DATE Irith Pomeranz, Sudhakar M. Reddy
2000	—	`conf`	High Performance/Delay Testing. Asian Test Symposium Shi-Yu Huang, Sudhakar M. Reddy
2000	A	`conf`	Improving the Proportion of At-Speed Tests in Scan BIST. ICCAD Yu Huang, Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski
2000	J	`jnl`	On Finding a Minimal Functional Description of a Finite-State Machine for Test Generation for Adjacent Machines. IEEE Trans. Computers Irith Pomeranz, Sudhakar M. Reddy
2000	Misc	`conf`	On Synchronizing Sequences and Unspecified Values in Output Responses of Synchronous Sequential Circuits. VLSI Design Irith Pomeranz, Sudhakar M. Reddy
2000	C	`conf`	On Test Application Time and Defect Detection Capabilities of Test Sets for Scan Designs. ICCD Irith Pomeranz, Sudhakar M. Reddy
2000	A*	`conf`	On diagnosis of pattern-dependent delay faults. DAC Irith Pomeranz, Sudhakar M. Reddy
2000	J	`jnl`	On n-detection test sets and variable n-detection test sets fortransition faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
2000	J	`jnl`	On synchronizable circuits and their synchronizing sequences. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
2000	J	`jnl`	On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits. IEEE Trans. Computers Irith Pomeranz, Sudhakar M. Reddy
2000	—	`conf`	On the feasibility of fault simulation using partial circuit descriptions. Asian Test Symposium Irith Pomeranz, Sudhakar M. Reddy
2000	—	`conf`	On the use of multiple fault detection times in a method for built-in test pattern generation for synchronous sequential circuits. ETW Irith Pomeranz, Sudhakar M. Reddy
2000	A	`conf`	On validating data hold times for flip-flops in sequential circuits. ITC Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara, Atsushi Murakami, Sadami Takeoka, Mitsuyasu Ohta
2000	J	`jnl`	Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits. IEEE Trans. Computers Irith Pomeranz, Sudhakar M. Reddy
2000	—	`conf`	Reducing test application time for full scan circuits by the addition of transfer sequences. Asian Test Symposium Irith Pomeranz, Sudhakar M. Reddy
2000	Misc	`conf`	SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration. VTS Xijiang Lin, Wu-Tung Cheng, Irith Pomeranz, Sudhakar M. Reddy
2000	A	`conf`	Selection of potentially testable path delay faults for test generation. ITC Atsushi Murakami, Seiji Kajihara, Tsutomu Sasao, Irith Pomeranz, Sudhakar M. Reddy
2000	C	`conf`	Sensitivity Levels of Test Patterns and Their Usefulness in Simulation-Based Test Generation. ICCD Irith Pomeranz, Sudhakar M. Reddy
2000	A	`conf`	Simulation Based Test Generation for Scan Designs. ICCAD Irith Pomeranz, Sudhakar M. Reddy
2000	J	`jnl`	Static Test Compaction for Scan-Based Designs to Reduce Test Application Time. J. Electron. Test. Irith Pomeranz, Sudhakar M. Reddy
2000	Misc	`conf`	Test Transformation to Improve Compaction by Statistical Encoding. VLSI Design Hideyuki Ichihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy
2000	A	`conf`	Test-Point Insertion to Enhance Test Compaction for Scan Designs. DSN Irith Pomeranz, Sudhakar M. Reddy
1999	J	`jnl`	A Cone-Based Genetic Optimization Procedure for Test Generation and Its Application to n-Detections in Combinational Circuits. IEEE Trans. Computers Irith Pomeranz, Sudhakar M. Reddy
1999	Misc	`conf`	A Fault Simulation Based Test Pattern Generator for Synchronous Sequential Circuits. VTS Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy
1999	Misc	`conf`	A Flexible Path Selection Procedure for Path Delay Fault Testing. VTS Irith Pomeranz, Sudhakar M. Reddy
1999	J	`jnl`	A comment on "Improving a nonenumerative method to estimate path delay fault coverage". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
1999	A	`conf`	An approach for improving the levels of compaction achieved by vector omission. ICCAD Irith Pomeranz, Sudhakar M. Reddy
1999	A	`conf`	Application of Tools Developed at the University of Iowa to ITC Benchmarks. ITC Sudhakar M. Reddy
1999	A*	`conf`	Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Test Subsequences. DAC Irith Pomeranz, Sudhakar M. Reddy
1999	C	`conf`	Fault Simulation Based Test Generation for Combinational Circuits Using Dynamically Selected Sub-Circuits. ICCD Irith Pomeranz, Sudhakar M. Reddy
1999	A	`conf`	Full Scan Fault Coverage With Partial Scan. DATE Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy
1999	A	`conf`	On achieving complete coverage of delay faults in full scan circuits using locally available lines. ITC Irith Pomeranz, Sudhakar M. Reddy
1999	—	`conf`	On avoiding undetectable faults during test generation. ETW Irith Pomeranz, Sudhakar M. Reddy
1999	Misc	`conf`	On n-Detection Test Sets and Variable n-Detection Test Sets for Transition Faults. VTS Irith Pomeranz, Sudhakar M. Reddy
1999	—	`conf`	PASTA: Partial Scan to Enhance Test Compaction. Great Lakes Symposium on VLSI Irith Pomeranz, Sudhakar M. Reddy
1999	—	`conf`	Pattern Sensitivity: A Property to Guide Test Generation for Combinational Circuits. Asian Test Symposium Irith Pomeranz, Sudhakar M. Reddy
1999	Misc	`conf`	Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits. VTS Sudhakar M. Reddy, Irith Pomeranz, Nadir Z. Basturkmen, Xijiang Lin
1999	A*	`conf`	Proptest: A Property Based Test Pattern Generator for Sequential Circuits Using Test Compaction. DAC Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz
1999	J	`jnl`	Static test compaction for synchronous sequential circuits based on vector restoration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy, Ruifeng Guo
1999	A	`conf`	SymSim: symbolic fault simulation of data-flow data-path designs at the Register-Transfer level. ITC Sitaran Yadavalli, Sudhakar M. Reddy
1999	A	`conf`	Techniques for improving the efficiency of sequential circuit test generation. ICCAD Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy
1999	A	`conf`	The effects of test compaction on fault diagnosis. ITC Yun Shao, Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz
1999	J	`jnl`	Universal delay test sets for logic networks. IEEE Trans. Very Large Scale Integr. Syst. Uwe Sparmann, Holger Müller, Sudhakar M. Reddy
1999	Misc	`conf`	VERSE: A Vector Replacement Procedure for Improving Test Compaction in Synchronous Sequential Circuits. VLSI Design Irith Pomeranz, Sudhakar M. Reddy
1999	—	`conf`	Vector-Based Functional Fault Models for Delay Faults. Asian Test Symposium Irith Pomeranz, Sudhakar M. Reddy
1998	—	`conf`	A Generalized Test Generation Procedure for Path Delay Faults. FTCS Irith Pomeranz, Sudhakar M. Reddy
1998	A	`conf`	A Synthesis Procedure for Flexible Logic Functions. DATE Irith Pomeranz, Sudhakar M. Reddy
1998	A	`conf`	A diagnostic test generation procedure for synchronous sequential circuits based on test elimination. ITC Irith Pomeranz, Sudhakar M. Reddy
1998	J	`jnl`	Delay fault models for VLSI circuits1. Integr. Irith Pomeranz, Sudhakar M. Reddy
1998	A	`conf`	Design-for-Testability for Synchronous Sequential Circuits using Locally Available Lines. DATE Irith Pomeranz, Sudhakar M. Reddy
1998	J	`jnl`	Design-for-testability for path delay faults in large combinational circuits using test points. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
1998	J	`jnl`	Functional test generation for delay faults in combinational circuits. ACM Trans. Design Autom. Electr. Syst. Irith Pomeranz, Sudhakar M. Reddy
1998	C	`conf`	Improved built-in test pattern generators based on comparison units for synchronous sequential circuits. ICCD Irith Pomeranz, Sudhakar M. Reddy
1998	J	`jnl`	Location of Stuck-At Faults and Bridging Faults Based on Circuit Partitioning. IEEE Trans. Computers Irith Pomeranz, Sudhakar M. Reddy
1998	J	`jnl`	Low-complexity fault simulation under the multiple observation time and the restricted multiple observation time testing approaches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
1998	Misc	`conf`	MIX: A Test Generation System for Synchronous Sequential Circuits. VLSI Design Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy
1998	Misc	`conf`	On Removing Redundant Faults in Synchronous Sequential Circuits. VTS Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy
1998	—	`conf`	On Speeding-Up Vector Restoration Based Static Compaction of Test Sequences for Sequential Circuits . Asian Test Symposium Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy
1998	Misc	`conf`	On Synchronizing Sequences and Test Sequence Partitioning. VTS Irith Pomeranz, Sudhakar M. Reddy
1998	Misc	`conf`	On Test Compaction Objectives for Combinational and Sequential Circuits. VLSI Design Irith Pomeranz, Sudhakar M. Reddy
1998	C	`conf`	On finding undetectable and redundant faults in synchronous sequential circuits. ICCD Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy
1998	J	`jnl`	On methods to match a test pattern generator to a circuit-under-test. IEEE Trans. Very Large Scale Integr. Syst. Irith Pomeranz, Sudhakar M. Reddy
1998	A	`conf`	Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits Based on Vector Restoration. DATE Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy
1998	—	`conf`	Static Test Compaction for Scan-Based Designs to Reduce Test Application Time. Asian Test Symposium Irith Pomeranz, Sudhakar M. Reddy
1998	Misc	`conf`	Stuck-At Tuple-Detection: A Fault Model Based on Stuck-At Faults for Improved Defect Coverage. VTS Irith Pomeranz, Sudhakar M. Reddy
1998	J	`jnl`	Techniques for minimizing power dissipation in scan and combinational circuits during test application. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vinay Dabholkar, Sreejit Chakravarty, Irith Pomeranz, Sudhakar M. Reddy
1998	—	`conf`	Test Compaction for Synchronous Sequential Circuits by Test Sequence Recycling. Great Lakes Symposium on VLSI Irith Pomeranz, Sudhakar M. Reddy
1998	—	`conf`	Test Generation for Synchronous Sequential Circuits to Reduce Storage Requirements. Asian Test Symposium Irith Pomeranz, Sudhakar M. Reddy
1998	J	`jnl`	Test sequences to achieve high defect coverage for synchronous sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
1998	J	`jnl`	Vertex Splitting in Dags and Applications to Partial Scan Designs and Lossy Circuits. Int. J. Found. Comput. Sci. Doowon Paik, Sudhakar M. Reddy, Sartaj Sahni
1997	Misc	`conf`	(Quasi-) Linear Path Delay Fault Tests for Adders. VLSI Design Bernd Becker, Rolf Drechsler, Sudhakar M. Reddy
1997	Misc	`conf`	A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths. VLSI Design Seiji Kajihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy
1997	—	`conf`	ACTIV-LOCSTEP: A Test Generation Procedure Based on Logic Simulation and Fault Activation. FTCS Irith Pomeranz, Sudhakar M. Reddy
1997	A	`conf`	Built-in test generation for synchronous sequential circuits. ICCAD Irith Pomeranz, Sudhakar M. Reddy
1997	J	`jnl`	Compact test sets for high defect coverage. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara
1997	Misc	`conf`	EXTEST: a method to extend test sequences of synchronous sequential circuits to increase the fault coverage. VTS Irith Pomeranz, Sudhakar M. Reddy
1997	A*	`conf`	Fault Simulation under the Multiple Observation Time Approach using Backward Implications. DAC Irith Pomeranz, Sudhakar M. Reddy
1997	J	`jnl`	LOCSTEP: a logic-simulation-based test generation procedure. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
1997	J	`jnl`	On Dictionary-Based Fault Location in Digital Logic Circuits. IEEE Trans. Computers Irith Pomeranz, Sudhakar M. Reddy
1997	Misc	`conf`	On Full Reset as a Design-For-Testability Technique. VLSI Design Irith Pomeranz, Sudhakar M. Reddy
1997	—	`conf`	On Generating Test Sets that Remain Valid in the Presence of Undetected Faults. Great Lakes Symposium on VLSI Irith Pomeranz, Sudhakar M. Reddy
1997	J	`jnl`	On error correction in macro-based circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
1997	—	`conf`	On improving genetic optimization based test generation. ED&TC Irith Pomeranz, Sudhakar M. Reddy
1997	Misc	`conf`	On n-detection test sequences for synchronous sequential circuits343. VTS Irith Pomeranz, Sudhakar M. Reddy
1997	—	`conf`	On the Compaction of Test Sets Produced by Genetic Optimization. Asian Test Symposium Irith Pomeranz, Sudhakar M. Reddy
1997	Misc	`conf`	On the Detection of Reset Faults in Synchronous Sequential Circuits. VLSI Design Irith Pomeranz, Sudhakar M. Reddy
1997	J	`jnl`	On the fault coverage of gate delay fault detecting tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ankan K. Pramanick, Sudhakar M. Reddy
1997	—	`conf`	On the use of reset to increase the testability of interconnected finite-state machines. ED&TC Irith Pomeranz, Sudhakar M. Reddy
1997	J	`jnl`	Perspectives on high performance network computing. Future Gener. Comput. Syst. Volker Strumpen, Balkrishna Ramkumar, Thomas L. Casavant, Sudhakar M. Reddy
1997	—	`conf`	TEMPLATES: A Test Generation Procedure for Synchronous Sequential Circuits. Asian Test Symposium Irith Pomeranz, Sudhakar M. Reddy
1997	J	`jnl`	Test Generation for Multiple State-Table Faults in Finite-State Machines. IEEE Trans. Computers Irith Pomeranz, Sudhakar M. Reddy
1997	C	`conf`	Vector Restoration Based Static Compaction of Test Sequences for Synchronous Sequential Circuits. ICCD Irith Pomeranz, Sudhakar M. Reddy
1996	—	`conf`	"Challenges in Testing". Asian Test Symposium Sudhakar M. Reddy
1996	—	`conf`	A Fast Optimal Robust Path Delay Fault Testable Adder. ED&TC Bernd Becker, Rolf Drechsler, Rolf Krieger, Sudhakar M. Reddy
1996	J	`jnl`	A novel framework for logic verification in a synthesis environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wolfgang Kunz, Dhiraj K. Pradhan, Sudhakar M. Reddy
1996	Misc	`conf`	Delay Fault Testing: How Robust are Our Models? VTS Sandeep K. Gupta, Slawomir Pilarski, Sudhakar M. Reddy, Jacob Savir, Prab Varma
1996	—	`conf`	Dynamic Test Compaction for Synchronous Sequential Circuits using Static Compaction Techniques. FTCS Irith Pomeranz, Sudhakar M. Reddy
1996	C	`conf`	Fault Location Based on Circuit Partitioning. ICCD Irith Pomeranz, Sudhakar M. Reddy
1996	A	`conf`	Local Transformations and Robust Dependent Path Delay. ITC Harry Hengster, Uwe Sparmann, Bernd Becker, Sudhakar M. Reddy
1996	—	`conf`	Low-Complexity Fault Diagnosis Under the Multiple Observation Time Testing Approach. Asian Test Symposium Irith Pomeranz, Sudhakar M. Reddy
1996	—	`conf`	Minimal Delay Test Sets for Unate Gate Networks. Asian Test Symposium Uwe Sparmann, Holger Müller, Sudhakar M. Reddy
1996	A	`conf`	On Cancelling the Effects of Logic Sharing for Improved Path Delay Fault Testability. ITC Irith Pomeranz, Sudhakar M. Reddy
1996	—	`conf`	On Double Transition Faults as a Delay Fault Model. Great Lakes Symposium on VLSI Irith Pomeranz, Sudhakar M. Reddy, Janak H. Patel
1996	Misc	`conf`	On Finding Functionally Identical and Functionally Opposite Lines in Combinational Logic Circuits. VLSI Design Irith Pomeranz, Sudhakar M. Reddy
1996	J	`jnl`	On Removing Redundancies from Synchronous Sequential Circuits with Synchronizing Sequences. IEEE Trans. Computers Irith Pomeranz, Sudhakar M. Reddy
1996	A*	`conf`	On Static Compaction of Test Sequences for Synchronous Sequential Circuits. DAC Irith Pomeranz, Sudhakar M. Reddy
1996	—	`conf`	On Test Generation for Interconnected Finite-State Machines - The Output Sequence Justification Problem. ED&TC Irith Pomeranz, Sudhakar M. Reddy
1996	—	`conf`	On Test Generation for Interconnected Finite-State Machines: The Input Sequence Propagation Problem. Asian Test Symposium Irith Pomeranz, Sudhakar M. Reddy
1996	J	`jnl`	On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits. IEEE Trans. Computers Irith Pomeranz, Sudhakar M. Reddy
1996	J	`jnl`	On the effectiveness of residue code checking for parallel two's complement multipliers. IEEE Trans. Very Large Scale Integr. Syst. Uwe Sparmann, Sudhakar M. Reddy
1996	Misc	`conf`	On the effects of test compaction on defect coverage. VTS Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara
1996	—	`conf`	Perspectives for High Performance Computing in Workstation Networks. HPCN Europe Volker Strumpen, Balkrishna Ramkumar, Thomas L. Casavant, Sudhakar M. Reddy
1995	J	`jnl`	Aliasing Computation Using Fault Simulation with Fault Dropping. IEEE Trans. Computers Irith Pomeranz, Sudhakar M. Reddy
1995	Misc	`conf`	Compact test generation for bridging faults under I VTS Remata S. Reddy, Irith Pomeranz, Sudhakar M. Reddy, Seiji Kajihara
1995	—	`conf`	Correcting Unidirectional Errors with Nonpositive Hopfield Networks. ICNN Soura Dasgupta, Yash Shrivastava, Sudhakar M. Reddy
1995	J	`jnl`	Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy
1995	J	`jnl`	Efficient multiple path propagating tests for delay faults. J. Electron. Test. Ankan K. Pramanick, Sudhakar M. Reddy
1995	A*	`conf`	Fast Identification of Robust Dependent Path Delay Faults. DAC Uwe Sparmann, D. Luxenburger, Kwang-Ting Cheng, Sudhakar M. Reddy
1995	A	`conf`	Functional test generation for delay faults in combinational circuits. ICCAD Irith Pomeranz, Sudhakar M. Reddy
1995	J	`jnl`	INCREDYBLE: A New Search Strategy for Design Automation Problems with Applications to Testing. IEEE Trans. Computers Irith Pomeranz, Sudhakar M. Reddy
1995	—	`conf`	LOCSTEP: A Logic Simulation Based Test Generation Procedure. FTCS Irith Pomeranz, Sudhakar M. Reddy
1995	A	`conf`	Low-Complexity Fault Simulation under the Multiplie Observation Time Testing Approach. ITC Irith Pomeranz, Sudhakar M. Reddy
1995	Misc	`conf`	MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level. VLSI Design Sitaran Yadavalli, Irith Pomeranz, Sudhakar M. Reddy
1995	J	`jnl`	NEST: a nonenumerative test generation method for path delay faults in combinational circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy, Prasanti Uppaluri
1995	J	`jnl`	On Fault Simulation for Synchronous Sequential Circuits. IEEE Trans. Computers Irith Pomeranz, Sudhakar M. Reddy
1995	A*	`conf`	On Synthesis-for-Testability of Combinational Logic Circuits. DAC Irith Pomeranz, Sudhakar M. Reddy
1995	J	`jnl`	On correction of multiple design errors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
1995	—	`conf`	On generating compact test sequences for synchronous sequential circuits. EURO-DAC Irith Pomeranz, Sudhakar M. Reddy
1995	—	`conf`	Static compaction for two-pattern test sets. Asian Test Symposium Irith Pomeranz, Sudhakar M. Reddy
1995	C	`conf`	Test generation for multiple state-table faults in finite-state machines. ICCD Irith Pomeranz, Sudhakar M. Reddy
1995	C	`conf`	Testing-what's missing? An incomplete list of challenges. ICCD Sudhakar M. Reddy
1994	A	`conf`	A Hierarchical Environment for Interactive Test Engineering. ITC Thomas Burch, Joachim Hartmann, Günter Hotz, M. Krallmann, U. Nikolaus, Sudhakar M. Reddy, Uwe Sparmann
1994	J	`jnl`	An efficient nonenumerative method to estimate the path delay fault coverage in combinational circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
1994	J	`jnl`	Application of Homing Sequences to Synchronous Sequential Circuit Testing. IEEE Trans. Computers Irith Pomeranz, Sudhakar M. Reddy
1994	J	`jnl`	Deleting Vertices to Bound Path Length. IEEE Trans. Computers Doowon Paik, Sudhakar M. Reddy, Sartaj Sahni
1994	A*	`conf`	Design-for-Testability for Path Delay Faults in Large Combinatorial Circuits Using Test-Points. DAC Irith Pomeranz, Sudhakar M. Reddy
1994	A	`conf`	On Achieving Complete Testability of Synchronous Sequential Circuits with Synchronizing Sequences. ITC Irith Pomeranz, Sudhakar M. Reddy
1994	—	`conf`	On Codeword Testing of Two-Rail and Parity TSC Checkers. FTCS Sudhakar M. Reddy, Irith Pomeranz, Rahul Jain
1994	Misc	`conf`	On Determining Symmetries in Inputs of Logic Circuits. VLSI Design Irith Pomeranz, Sudhakar M. Reddy
1994	A*	`conf`	On Improving Fault Diagnosis for Synchronous Sequential Circuits. DAC Irith Pomeranz, Sudhakar M. Reddy
1994	J	`jnl`	On achieving complete fault coverage for sequential machines. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
1994	Misc	`conf`	On compacting test sets by addition and removal of test vectors. VTS Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy
1994	J	`jnl`	On determining symmetries in inputs of logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
1994	A	`conf`	On error correction in macro-based circuits. ICCAD Irith Pomeranz, Sudhakar M. Reddy
1994	Misc	`conf`	On identifying undetectable and redundant faults in synchronous sequential circuits. VTS Irith Pomeranz, Sudhakar M. Reddy
1994	A	`conf`	On testing delay faults in macro-based combinational circuits. ICCAD Irith Pomeranz, Sudhakar M. Reddy
1994	—	`conf`	On the Effectiveness of Residue Code Checking for Parallel Two's Complement Multipliers. FTCS Uwe Sparmann, Sudhakar M. Reddy
1994	J	`jnl`	On the Role of Hardware Reset in Synchronous Sequential Circuit Test Generation. IEEE Trans. Computers Irith Pomeranz, Sudhakar M. Reddy
1994	J	`jnl`	SPADES-ACE: a simulator for path delay faults in sequential circuits with extensions to arbitrary clocking schemes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
1994	—	`conf`	Test Pattern Generation for Path Delay Faults in Synchronous Sequential Circuits Using Multiple Fast Clocks and Multiple Observations Times. FTCS Prasanti Uppaluri, Irith Pomeranz, Sudhakar M. Reddy
1993	J	`jnl`	3-weight pseudo-random test generation based on a deterministic test set for combinational and sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy
1993	A	`conf`	A Learning-Based Method to Match a Test Pattern Generator to a Circuit-Under-Test. ITC Irith Pomeranz, Sudhakar M. Reddy
1993	—	`conf`	A method for diagnosing implementation errors in synchronous sequential circuits and its implications on synthesis. EURO-DAC Irith Pomeranz, Sudhakar M. Reddy
1993	Misc	`conf`	Aliasing computation using fault simulation with fault dropping. VTS Irith Pomeranz, Sudhakar M. Reddy
1993	J	`jnl`	COMPACTEST: a method to generate compact test sets for combinational circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Lakshmi N. Reddy, Sudhakar M. Reddy
1993	J	`jnl`	Classification of Faults in Synchronous Sequential Circuits. IEEE Trans. Computers Irith Pomeranz, Sudhakar M. Reddy
1993	A*	`conf`	Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits. DAC Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy
1993	—	`conf`	Design and Synthesis for Testability of Synchronous Sequential Circuits Based on Strong-Connectivity. FTCS Irith Pomeranz, Sudhakar M. Reddy
1993	—	`conf`	EXOP (Extended Operation): A New Logical Fault Model for Digital Circuits. FTCS Irith Pomeranz, Sudhakar M. Reddy
1993	Misc	`conf`	Genetic Beam Search for Gate Matrix Layout. VLSI Design Khushro Shahookar, W. Khamisani, Pinaki Mazumder, Sudhakar M. Reddy
1993	Misc	`conf`	Heuristics for the Placement of Flip-Flops in Partial Scan Designs and the Placement of Signal Boosters in Lossy Circuits. VLSI Design Doowon Paik, Sudhakar M. Reddy, Sartaj Sahni
1993	A*	`conf`	NEST: A Non-Enumerative Test Generation Method for Path Delay Faults in Combinational Circuits. DAC Irith Pomeranz, Sudhakar M. Reddy, Prasanti Uppaluri
1993	Misc	`conf`	On Unified Delay Fault Testing. VLSI Design Ankan K. Pramanick, Sudhakar M. Reddy
1993	A	`conf`	On diagnosis and correction of design errors. ICCAD Irith Pomeranz, Sudhakar M. Reddy
1993	Misc	`conf`	On the Generation of Weights for Weighted Pseudo Random Testing. VLSI Design Irith Pomeranz, Sudhakar M. Reddy
1993	A	`conf`	Test generation for path delay faults based on learning. ICCAD Irith Pomeranz, Sudhakar M. Reddy
1993	J	`jnl`	Testing of Fault-Tolerant Hardware Through Partial Control of Inputs. IEEE Trans. Computers Irith Pomeranz, Sudhakar M. Reddy
1993	—	`conf`	Theory and Practice of Sequential Machine Testing and Testability. FTCS Irith Pomeranz, Sudhakar M. Reddy, Janak H. Patel
1992	Misc	`conf`	3-Weight Pseudo-Random Test Generation Based on a Deterministic Test Set. VLSI Design Irith Pomeranz, Sudhakar M. Reddy
1992	—	`conf`	A Divide-And-Conquer Approach to Test Generation for Large Synchronous Sequential Circuits. FTCS Irith Pomeranz, Sudhakar M. Reddy
1992	A	`conf`	An efficient non-enumerative method to estimate path delay fault coverage. ICCAD Irith Pomeranz, Sudhakar M. Reddy
1992	A*	`conf`	At-Speed Delay Testing of Synchronous Sequential Circuits. DAC Irith Pomeranz, Sudhakar M. Reddy
1992	A	`conf`	COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuits. ICCAD Lakshmi N. Reddy, Irith Pomeranz, Sudhakar M. Reddy
1992	Misc	`conf`	Generalization of independent faults for transition faults. VTS Irith Pomeranz, Sudhakar M. Reddy
1992	J	`jnl`	Guaranteed convergence in a class of Hopfield networks. IEEE Trans. Neural Networks Yash Shrivastava, Soura Dasgupta, Sudhakar M. Reddy
1992	A*	`conf`	On Efficient Concurrent Fault Simulation for Synchronous Sequential Circuits. DAC Dong-Ho Lee, Sudhakar M. Reddy
1992	J	`jnl`	On the design of random pattern testable PLA based on weighted random pattern testing. J. Electron. Test. Dong Sam Ha, Sudhakar M. Reddy
1992	A	`conf`	On the generation of small dictionaries for fault location. ICCAD Irith Pomeranz, Sudhakar M. Reddy
1992	—	`conf`	SPADES: a simulator for path delay faults in sequential circuits. EURO-DAC Irith Pomeranz, Lakshmi N. Reddy, Sudhakar M. Reddy
1992	—	`conf`	Synthesis of Multi-Level Combinational Circuits for Complete Robust Path Delay Fault Testability. FTCS Niraj K. Jha, Irith Pomeranz, Sudhakar M. Reddy, Robert J. Miller
1992	J	`jnl`	The Multiple Observation Time Test Strategy. IEEE Trans. Computers Irith Pomeranz, Sudhakar M. Reddy
1991	A	`conf`	A New Test Generation Method for Sequential Circuits. ICCAD Dong-Ho Lee, Sudhakar M. Reddy
1991	A	`conf`	Achieving Complete Delay Fault Testability by Extra Inputs. ITC Irith Pomeranz, Sudhakar M. Reddy
1991	A	`conf`	COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits. ITC Irith Pomeranz, Lakshmi N. Reddy, Sudhakar M. Reddy
1991	J	`jnl`	Design of robustly testable combinational logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sandip Kundu, Sudhakar M. Reddy, Niraj K. Jha
1991	A	`conf`	Increasing Fault Coverage for Synchronous Sequential Circuits by the Multiple Observation Time Test Strategy. ICCAD Irith Pomeranz, Sudhakar M. Reddy, Lakshmi N. Reddy
1991	A*	`conf`	On Achieving a Complete Fault Coverage for Sequential Machines Using the Transition Fault Model. DAC Irith Pomeranz, Sudhakar M. Reddy
1991	A	`conf`	On Multiple Path Propagating Tests for Path Delay Faults. ITC Ankan K. Pramanick, Sudhakar M. Reddy
1991	A	`conf`	Test Generation for Synchronous Sequential Circuits Based on Fault Extraction. ICCAD Irith Pomeranz, Sudhakar M. Reddy
1991	—	`conf`	Test Generation for Synchronous Sequential Circuits Using Multiple Observation Times. FTCS Irith Pomeranz, Sudhakar M. Reddy
1991	—	`conf`	Testing of Fault-Tolerant Hardware. Fault-Tolerant Computing Systems Irith Pomeranz, Sudhakar M. Reddy
1990	J	`jnl`	Embedded Totally Self-Checking Checkers: A Practical Design. IEEE Des. Test Comput. Sandip Kundu, Sudhakar M. Reddy
1990	J	`jnl`	Long and short covering edges in combination logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wing Ning Li, Sudhakar M. Reddy, Sartaj Sahni
1990	A	`conf`	On Determining Scan Flip-Flops in Partial-Scan Designs. ICCAD Dong-Ho Lee, Sudhakar M. Reddy
1990	J	`jnl`	On Symmetric Error Correcting and All Unidirectional Error Detecting Codes. IEEE Trans. Computers Sandip Kundu, Sudhakar M. Reddy
1990	—	`conf`	On the design of path delay fault testable combinational circuits. FTCS Ankan K. Pramanick, Sudhakar M. Reddy
1990	—	`conf`	On the fault coverage of delay fault detecting tests. EURO-DAC Ankan K. Pramanick, Sudhakar M. Reddy
1990	J	`jnl`	Robust tests for parity trees. J. Electron. Test. Sandip Kundu, Sudhakar M. Reddy
1990	—	`conf`	Zero aliasing compression. FTCS Sandeep K. Gupta, Dhiraj K. Pradhan, Sudhakar M. Reddy
1989	C	`conf`	A test generation system for path delay faults. ICCD Srinivas Patil, Sudhakar M. Reddy
1989	C	`conf`	Design of TSC checkers for implementation in CMOS technology. ICCD Sandip Kundu, Sudhakar M. Reddy
1989	J	`jnl`	On path selection in combinational logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wing Ning Li, Sudhakar M. Reddy, Sartaj K. Sahni
1989	J	`jnl`	On the Design of Fault-Tolerant Two-Dimensional Systolic Arrays for Yield Enhancement. IEEE Trans. Computers Jung Hwan Kim, Sudhakar M. Reddy
1989	A*	`conf`	On the Repair of Redundant RAMs. DAC V. G. Hemmady, Sudhakar M. Reddy
1989	A	`conf`	On the computation of the ranges of detected delay fault sizes. ICCAD Ankan K. Pramanick, Sudhakar M. Reddy
1988	J	`jnl`	A Data Compression Technique for Built-In Self-Test. IEEE Trans. Computers Sudhakar M. Reddy, Kewal K. Saluja, Mark G. Karpovsky
1988	A*	`conf`	On Path Selection in Combinational Logic Circuits. DAC Wing Ning Li, Sudhakar M. Reddy, Sartaj Sahni
1988	J	`jnl`	On Self-Fault Diagnosis of the Distributed Systems. IEEE Trans. Computers Seyed H. Hosseini, Jon G. Kuhl, Sudhakar M. Reddy
1988	J	`jnl`	On the Design of Pseudoexhaustive Testable PLA's. IEEE Trans. Computers Dong Sam Ha, Sudhakar M. Reddy
1988	A	`conf`	On the Detection of Delay Faults. ITC Ankan K. Pramanick, Sudhakar M. Reddy
1988	A	`conf`	On the design of robust multiple fault testable CMOS combinational logic circuits. ICCAD Sandip Kundu, Sudhakar M. Reddy, Niraj K. Jha
1988	—	`conf`	On the design of robust testable CMOS combinational logic circuits. FTCS Sandip Kundu, Sudhakar M. Reddy
1988	A	`conf`	Robust Tests for Parity Trees. ITC Sandip Kundu, Sudhakar M. Reddy
1987	J	`jnl`	A New Approach to the Design of Testable PLA's. IEEE Trans. Computers Sudhakar M. Reddy, Dong Sam Ha
1987	A*	`conf`	A Parallel PLA Minimization Program. DAC R. Galivanche, Sudhakar M. Reddy
1987	J	`jnl`	Augmented Shuffle-Exchange Multistage Interconnection Networks. Computer Vijay P. Kumar, Sudhakar M. Reddy
1987	J	`jnl`	Distributed Fault-Tolerance of Tree Structures. IEEE Trans. Computers Seyed H. Hosseini, Jon G. Kuhl, Sudhakar M. Reddy
1987	J	`jnl`	On Delay Fault Testing in Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chin Jen Lin, Sudhakar M. Reddy
1987	J	`jnl`	Scan Design Using Standard Flip-Flops. IEEE Des. Test Sudhakar M. Reddy, Ramaswami Dandapani
1986	J	`jnl`	Detecting FET Stuck-Open Faults in CMOS Latches and Flip-Flops. IEEE Des. Test Madhukar K. Reddy, Sudhakar M. Reddy
1986	J	`jnl`	Fault-Tolerance Considerations in Large Multiple-Processor Systems. Computer Jon G. Kuhl, Sudhakar M. Reddy
1986	A	`conf`	On the Design of Random Pattern Testable PLAs. ITC Dong Sam Ha, Sudhakar M. Reddy
1986	J	`jnl`	Testable Realizations for FET Stuck-Open Faults CMOS Combinational Logic Circuits. IEEE Trans. Computers Sudhakar M. Reddy, Madhukar K. Reddy
1985	A*	`conf`	Design and Analysis of Fault-Tolerant Multistage Interconnection Networks With Low Link Complexity. ISCA Vijay P. Kumar, Sudhakar M. Reddy
1985	A	`conf`	On Multipath Multistage Interconnection Networks. ICDCS Sudhakar M. Reddy, Vijay P. Kumar
1985	A	`conf`	On the Design of Testable Domino PLAs. ITC Dong Sam Ha, Sudhakar M. Reddy
1985	A*	`conf`	Transistor level test generation for MOS circuits. DAC Madhukar K. Reddy, Sudhakar M. Reddy, Prathima Agrawal
1984	A	`conf`	A Class of Graphs for Fault-Tolerant Processor Interconnections. ICDCS Vijay P. Kumar, Sudhakar M. Reddy
1984	J	`jnl`	A Diagnosis Algorithm for Distributed Computing Systems with Dynamic Failure and Repair. IEEE Trans. Computers Seyed H. Hosseini, Jon G. Kuhl, Sudhakar M. Reddy
1984	A*	`conf`	A gate level model for CMOS combinational logic circuits with application to fault detection. DAC Sudhakar M. Reddy, Vishwani D. Agrawal, Sunil K. Jain
1984	A	`conf`	On CMOS Totally Self-Checking Circuits. ITC Sridhar R. Manthani, Sudhakar M. Reddy
1983	B	`conf`	A Class of Graphs for Processor Interconnection. ICPP Jon G. Kuhl, Sudhakar M. Reddy, P. Raghavan
1983	A	`conf`	On Testable Design for CMOS Logic Circuits. ITC Jon G. Kuhl, Sudhakar M. Reddy
1982	J	`jnl`	A Fault-Tolerant Communication Architecture for Distributed Systems. IEEE Trans. Computers Dhiraj K. Pradhan, Sudhakar M. Reddy
1982	A	`conf`	Design of Easily Testable Microprocessors : A Case Study. ITC Sunil Nanda, Sudhakar M. Reddy
1981	J	`jnl`	A March Test for Functional Faults in Semiconductor Random Access Memories. IEEE Trans. Computers Dong S. Suk, Sudhakar M. Reddy
1981	J	`jnl`	A Testable Design of Iterative Logic Arrays. IEEE Trans. Computers R. Parthasarathy, Sudhakar M. Reddy
1980	A*	`conf`	Distributed Fault-Tolerance For Large Multiprocessor Systems. ISCA Jon G. Kuhl, Sudhakar M. Reddy
1980	J	`jnl`	Test Procedures for a Class of Pattern-Sensitive Faults in Semiconductor Random-Access Memories. IEEE Trans. Computers Dong S. Suk, Sudhakar M. Reddy
1978	J	`jnl`	A Class of Linear Codes for Error Control in Byte-per-Card Organized Digital Systems. IEEE Trans. Computers Sudhakar M. Reddy
1978	J	`jnl`	A Multicode Single Transition-Time State Assignment for Asynchronous Sequential Machines. IEEE Trans. Computers Jon G. Kuhl, Sudhakar M. Reddy
1978	J	`jnl`	On the Detection of Terminal Stuck-Faults. IEEE Trans. Computers Jon G. Kuhl, Sudhakar M. Reddy
1977	J	`jnl`	A Note on Testing Logic Circuits by Transition Counting. IEEE Trans. Computers Sudhakar M. Reddy
1977	J	`jnl`	Comments on "Minimal Fault Tests for Combinational Networks". IEEE Trans. Computers Sudhakar M. Reddy
1977	J	`jnl`	On Totally Self-Checking Checkers for Separable Codes. IEEE Trans. Computers Mohammad Javad Ashjaee, Sudhakar M. Reddy
1976	J	`jnl`	Techniques to Construct (2, 1) Separating Systems from Linear Error-Correcting Codes. IEEE Trans. Computers Dhiraj K. Pradhan, Sudhakar M. Reddy
1975	J	`jnl`	A Routing Algorithm for Computer Communication Networks. IEEE Trans. Commun. Dong H. Chyung, Sudhakar M. Reddy
1975	J	`jnl`	Fault Detecting Test Sets for Reed-Muller Canonic Networks. IEEE Trans. Computers Kewal K. Saluja, Sudhakar M. Reddy
1974	J	`jnl`	Authors' Reply. IEEE Trans. Computers James W. Gault, John P. Robinson, Sudhakar M. Reddy
1974	J	`jnl`	Design of Two-Level Fault-Tolerant Networks. IEEE Trans. Computers Dhiraj K. Pradhan, Sudhakar M. Reddy
1974	J	`jnl`	Easily Testable Cellular Realizations for the (Exactly P)-out-of n and (p or More)-out-of n Logic Functions. IEEE Trans. Computers Sudhakar M. Reddy, James R. Wilson
1974	J	`jnl`	Easily Testable Two-Dimensional Cellular Logic Arrays. IEEE Trans. Computers Kewal K. Saluja, Sudhakar M. Reddy
1974	J	`jnl`	Further results on decoders for Q -ary output channels (Corresp.). IEEE Trans. Inf. Theory Sudhakar M. Reddy
1974	J	`jnl`	Note on Self-Checking Checkers. IEEE Trans. Computers Sudhakar M. Reddy
1974	J	`jnl`	On Minimally Testable Logic Networks. IEEE Trans. Computers Kewal K. Saluja, Sudhakar M. Reddy
1974	J	`jnl`	On the Design of Logic Networks with Redundancy and Testability Considerations. IEEE Trans. Computers Ramaswami Dandapani, Sudhakar M. Reddy
1973	J	`jnl`	A (48, 31, 8) linear code (Corresp.). IEEE Trans. Inf. Theory V. V. Rao, Sudhakar M. Reddy
1973	J	`jnl`	Complete Test Sets for Logic Functions. IEEE Trans. Computers Sudhakar M. Reddy
1973	J	`jnl`	Fault-Tolerant Asynchronous Networks. IEEE Trans. Computers Dhiraj K. Pradhan, Sudhakar M. Reddy
1972	J	`jnl`	A Design Procedure for Fault-Locatable Switching Circuits. IEEE Trans. Computers Sudhakar M. Reddy
1972	J	`jnl`	Easily Testable Realizations ror Logic Functions. IEEE Trans. Computers Sudhakar M. Reddy
1972	J	`jnl`	Error-Control Techniques for Logic Processors. IEEE Trans. Computers Dhiraj K. Pradhan, Sudhakar M. Reddy
1972	J	`jnl`	Forward-Error Correction with Decision Feedback Inf. Control. George I. Davida, Sudhakar M. Reddy
1972	J	`jnl`	Hybrid block- self-orthogonal convolutional codes. IEEE Trans. Inf. Theory Sudhakar M. Reddy, John P. Robinson
1972	J	`jnl`	Multiple Fault Detection in Combinational Networks. IEEE Trans. Computers James W. Gault, John P. Robinson, Sudhakar M. Reddy
1972	—	`conf`	Multiple Faults in Reed-Muller Canonic Networks SWAT Kewal K. Saluja, Sudhakar M. Reddy
1972	J	`jnl`	New binary codes. IEEE Trans. Inf. Theory Neil J. A. Sloane, Sudhakar M. Reddy, Chin-Long Chen
1972	J	`jnl`	On block codes with specified maximum distance (Corresp.). IEEE Trans. Inf. Theory Sudhakar M. Reddy
1972	J	`jnl`	Random error and burst correction by iterated codes. IEEE Trans. Inf. Theory Sudhakar M. Reddy, John P. Robinson
1971	J	`jnl`	Linear Convolutional Codes for Compound Channels Inf. Control. Sudhakar M. Reddy
1970	J	`jnl`	A Class of High-Rate Double-Error-Correcting Convolutional Codes Inf. Control. Sudhakar M. Reddy, George I. Davida, John P. Robinson
1970	J	`jnl`	Circulant bases for cyclic codes (Corresp.). IEEE Trans. Inf. Theory Charles W. Hoffner II, Sudhakar M. Reddy
1970	J	`jnl`	On decoding iterated codes. IEEE Trans. Inf. Theory Sudhakar M. Reddy
1969	J	`jnl`	A feedback decoding scheme for linear convolutional codes (Corresp.). IEEE Trans. Inf. Theory Sudhakar M. Reddy
1969	J	`jnl`	A note on decoding of block codes (Corresp.). IEEE Trans. Inf. Theory Sudhakar M. Reddy
1968	J	`jnl`	A Construction for Convolutional Codes Using Block Codes Inf. Control. Sudhakar M. Reddy, John P. Robinson
1968	J	`jnl`	A Decoding Algorithm for Some Convolutional Codes Constructed from Block Codes Inf. Control. Sudhakar M. Reddy, John P. Robinson
1968	J	`jnl`	Further Results on Convolutional Codes Derived from Block Codes Inf. Control. Sudhakar M. Reddy