Sudeb Dasgupta

93 papers C 6Misc 10Journal 36Unranked 38

Year	Rank	Type	Title / Venue / Authors
2026	Misc	`conf`	A 146 GOPS and 7.2 TOPS/W 6T SRAM-Based Analog CIM Macro Using Bit-Splitting for 8-Bit MAC Operations. VLSID Cheena Singhal, Abhishek Goel, Sparsh Mittal, Sudeb Dasgupta
2026	J	`jnl`	Energy Efficient Single Phase Adiabatic Logic and Its Application in Ripple Carry Adder Design. Circuits Syst. Signal Process. Jitendra Kanungo, Jitendra Raghuwanshi, Deepak Sharma, Sudeb Dasgupta
2025	C	`conf`	A 1.91 POPS/W Energy-Efficient SRAM Based Signed Multi-Bit Time Domain CIM Architecture. ISCAS Subhradip Chakraborty, Dinesh Kushwaha, Himanshu Ranjan, Sudeb Dasgupta
2025	J	`jnl`	A Methodology for Datapath Energy Prediction and Optimization in Near Threshold Voltage Regime. IEEE Trans. Very Large Scale Integr. Syst. Mahipal Dargupally, Lomash Chandra Acharya, Arvind K. Sharma, Sudeb Dasgupta, Anand Bulusu
2025	—	`conf`	A Robust 4T1C eDRAM Compute-in-Memory Architecture for Inference Applications. NewCAS Aditya Kumar Singh, Dinesh Kushwaha, Sudeb Dasgupta
2025	—	`conf`	A Robust Fully Differential MAC Scheme Using Dummy Rows to Enhance the Signal Margin of Analog Compute-in-Memory Architecture. NewCAS Dinesh Kushwaha, Sudeb Dasgupta, Anand Bulusu
2025	—	`conf`	Aging Model Development for ASAP 7 nm Predictive PDK: Application in Aging-Aware Performance Prediction of Digital Logic and ADCs in Data Acquisition System. ISVLSI Neha Gupta, Lomash Chandra Acharya, Mahipal Dargupally, Khoirom Johnson Singh, Amit Kumar Behera, Johan Euphrosine, Sudeb Dasgupta, Anand Bulusu
2025	—	`conf`	Characterization of Inter-Chip Interconnects Using Piecewise Effective Capacitance. SMACD Nilotpal Sarma, Ashutosh Yadav, Sudeb Dasgupta, Anand Bulusu
2025	J	`jnl`	Robust and Reliable Energy-Efficient Level Shifter. IEEE Trans. Circuits Syst. II Express Briefs Mahipal Dargupally, Lomash Chandra Acharya, Neha Gupta, Ahrron Kongala, Arvind K. Sharma, Sudeb Dasgupta, Anand Bulusu
2024	—	`conf`	An Area and Energy-Efficient SRAM Based Time - Domain Compute-In-Memory Architecture For BNN. AICAS Subhradip Chakraborty, Dinesh Kushwaha, Anand Bulusu, Sudeb Dasgupta
2024	—	`conf`	An Energy-Efficient High Signal Margin Analog Compute-In-Memory Architecture. LASCAS Dinesh Kushwaha, Rajat Kohli, Jwalant Mishra, Jainendra Singh, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
2024	—	`conf`	An Energy-Efficient SRAM-Based Charge Domain Compute In-Memory Architecture. NewCAS Anmol Singla, Dinesh Kushwaha, Gulyawar Aman, Shubhradin Chakraborty, Abhishek Goel, Anand Bulusu, Sudeb Dasgupta
2024	—	`conf`	An Energy-Efficient Time Domain Based Compute In-Memory Architecture for Binary Neural Network. ISQED Subhradip Chakraborty, Dinesh Kushwaha, Abhishek Goel, Anmol Singla, Anand Bulusu, Sudeb Dasgupta
2024	C	`conf`	Interface Trap Analysis in Multi-Fin FinFET Technology: a Crucial Reliability Issue in Digital Application. ISCAS Jyoti Patel, Sankalp Rai, Vivek Kumar, Sudeb Dasgupta
2024	J	`jnl`	Multi-Bit Compute-In Memory Architecture Using a C-2C Ladder Network. IEEE Trans. Circuits Syst. II Express Briefs Dinesh Kushwaha, Jaya Kumar Abotula, Rajat Kohli, Jwalant Mishra, Sudeb Dasgupta, Anand Bulusu
2024	—	`conf`	SRAM-Based Analog Compute-In-Memory Architecture Using C-2C Ladder And Signal Margin Assisted Design Methodology. ISQED Dinesh Kushwaha, Ashish Joshi, Abhishek Goel, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
2024	C	`conf`	SRAM-Based Hybrid Analog Compute-In-memory Architecture to Enhance the Signal Margin. ISCAS Dinesh Kushwaha, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
2024	J	`jnl`	Switching Activity Factor-Based ECSM Characterization (SAFE): A Novel Technique for Aging-Aware Static Timing Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lomash Chandra Acharya, Arvind K. Sharma, Neeraj Mishra, Khoirom Johnson Singh, Mahipal Dargupally, Neha Gupta, Nayakanti Sai Shabarish, Ajoy Mandal, Venkatraman Ramakrishnan, Sudeb Dasgupta, Anand Bulusu
2024	—	`conf`	TG-in-DRAM: A Transmission Gate based Full Adder using Multi-row Activation for enhanced Throughput in CIM Architectures. APCCAS Sambhav Sharma, Garima Choudhary, Neha Gupta, Sunil Rathore, Anand Bulusu, Sudeb Dasgupta
2024	—	`conf`	Time-Domain-Based Non-volatile In-Memory Computing Architecture Using FeFETs for Binary Neural Network. ISQED Aditya Sharma, Vatsal Dixit, Dinesh Kushwaha, Nitanshu Chauhan, Vishal Kumar Saxena, Sudeb Dasgupta, Anand Bulusu
2024	—	`conf`	Variation-Aware Design Methodology for SRAM-Based Multi-Bit Analog Compute-in-Memory Architecture. NewCAS Dinesh Kushwaha, Rajiv V. Joshi, Anand Bulusu, Sudeb Dasgupta
2023	—	`conf`	A Fully Differential 4-Bit Analog Compute-In-Memory Architecture for Inference Application. AICAS Dinesh Kushwaha, Rajat Kohli, Jwalant Mishra, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
2023	—	`conf`	ABB Assisted Area Efficient Vernier Delay Line Time-to-Digital Converter for Low Voltage Applications. APCCAS Ravi, Lomash Chandra Acharya, Mahipal Dargupally, Neha Gupta, Neeraj Mishra, Lalit Mohan Dani, Nilotpal Sarma, Devesh Dwivedi, Sudeb Dasgupta, Anand Bulusu
2023	J	`jnl`	Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lomash Chandra Acharya, Arvind Kumar Sharma, Neeraj Mishra, Khoirom Johnson Singh, Mahipal Dargupally, Nayakanti Sai Shabarish, Ajoy Mandal, Venkatraman Ramakrishnan, Sudeb Dasgupta, Anand Bulusu
2023	—	`conf`	An Efficient Standard Cell Design Methodology by Exploiting Body Biasing and Poly Biasing in FDSOI for NTV Regime. APCCAS Mahipal Dargupally, Lomash Chandra Acharya, Khoirom Johnson Singh, Neha Gupta, Arvind K. Sharma, Sudeb Dasgupta, Anand Bulusu
2023	Misc	`conf`	An Energy-Efficient Multi-bit Current-based Analog Compute-In-Memory Architecture and design Methodology. VLSID Dinesh Kushwaha, Ashish Joshi, Neha Gupta, Aditya Sharma, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
2023	—	`conf`	Beyond SPICE Simulation: A Novel Variability-Aware STA Methodology for Digital Timing Closure. SMACD Lomash Chandra Acharya, Anubhav Kumar, Khoirom Johnson Singh, Neha Gupta, Nayakanti Sai Shabarish, Neeraj Mishra, Mahipal Dargupally, Arvind Kumar Sharma, Venkatraman Ramakrishnan, Ajoy Mandal, Sudeb Dasgupta, Anand Bulusu
2023	Misc	`conf`	FEM modeling of gate resistance for 5 nm SGC/DGC Stacked Nanosheet Transistor. VLSID Vivek Kumar, Jyoti Patel, Arnab Datta, Sudeb Dasgupta
2023	J	`jnl`	Negative capacitance gate stack and Landau FET-based voltage amplifiers and circuits: Impact of ferroelectric thickness and domain variations. Microelectron. J. Khoirom Johnson Singh, Lomash Chandra Acharya, Anand Bulusu, Sudeb Dasgupta
2023	—	`conf`	Power Efficient Hardware Fingerprint: Exploiting Process-Variations in A Quasi-Planar 14nm FinFET. APCCAS Jyoti Patel, Govind Sharma, Chitraja Rajan, Vivek Kumar, Sudeb Dasgupta
2023	Misc	`conf`	Radiation Hardened CMOS Programmable Bias Generator for Space Applications at 180nm. VLSID Ashutosh Yadav, Anand Bulusu, Surinder Singh, Sudeb Dasgupta
2022	C	`conf`	A 65nm Compute-In-Memory 7T SRAM Macro Supporting 4-bit Multiply and Accumulate Operation by Employing Charge Sharing. ISCAS Dinesh Kushwaha, Aditya Sharma, Neha Gupta, Ritik Raj, Ashish Joshi, Jwalant Mishra, Rajat Kohli, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
2022	—	`conf`	A Multibit MAC Scheme using Switched Capacitor based 3C Multiplier for Analog Compute In-Memory Architecture. ICECS 2022 Neha Gupta, Ashish Joshi, Dinesh Kushwaha, Vinod Menezes, Rashmi Sachan, Sudeb Dasgupta, Anand Bulusu
2022	J	`jnl`	An Energy-Efficient High CSNR XNOR and Accumulation Scheme for BNN. IEEE Trans. Circuits Syst. II Express Briefs Dinesh Kushwaha, Ashish Joshi, Chaudhry Indra Kumar, Neha Gupta, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
2022	Misc	`conf`	Design optimization Using Symmetric/Asymmetric Spacer for 14 nm Multi-Fin Tri-gate Fin-FET for Mid-Band 5G Applications. VLSID Jyoti Patel, Shashank Banchhor, Surila Guglani, Avirup Dasgupta, Sourajeet Roy, Anand Bulusu, Sudeb Dasgupta
2022	—	`conf`	FEM Modeling of Thermal Aspect of Dielectric Inserted Under Source & Drain of 5 nm Nanosheet. VDAT Vivek Kumar, Jyoti Patel, Arnab Datta, Sudeb Dasgupta
2022	—	`conf`	Impact of Random Spatial Fluctuation in Non-Uniform Crystalline Phases on Multidomain MFIM Capacitor and Negative Capacitance FDSOI. IRPS Nitanshu Chauhan, Chirag Garg, Kai Ni, Amit Kumar Behera, Sarita Yadav, Shashank Banchhor, Navjeet Bagga, Avirup Dasgupta, Arnab Datta, Sudeb Dasgupta, Anand Bulusu
2022	J	`jnl`	Phase Noise Analysis of Separately Driven Ring Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. Neeraj Mishra, Anchit Proch, Lomash Chandra Acharya, Jeffrey Prinzie, Sudipto Chakraborty, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
2022	C	`conf`	Significance of Organic Ferroelectric in Harnessing Transient Negative Capacitance Effect at Low Voltage Over Oxide Ferroelectric. ISCAS Khoirom Johnson Singh, Lomash Chandra Acharya, Anand Bulusu, Sudeb Dasgupta
2022	—	`conf`	Unveiling the Impact of Interface Traps Induced on Negative Capacitance Nanosheet FET: A Reliability Perspective. VDAT Aniket Gupta, Govind Bajpai, Navjeet Bagga, Shashank Banchhor, Sudeb Dasgupta, Anand Bulusu, Nitanshu Chauhan
2022	—	`ed.`	VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers VDAT Ambika Prasad Shah, Sudeb Dasgupta, Anand D. Darji, Jaynarayan T. Tudu
2021	—	`conf`	Design and Fabrication of Rad-hard Low Power CMOS Temperature Sensor for Space Applications at 180nm. ICM Ashutosh Yadav, Anand Bulusu, Sudeb Dasgupta, Surinder Singh
2021	C	`conf`	Harnessing Maximum Negative Capacitance Signature Voltage Window in P(VDF-TrFE) Gate Stack. ISCAS Khoirom Johnson Singh, Anand Bulusu, Sudeb Dasgupta
2021	—	`conf`	Variation Aware Timing Model of CMOS Inverter for an Efficient ECSM Characterization. ISQED Lomash Chandra Acharya, Arvind Kumar Sharma, Venkatraman Ramakrishnan, Ajoy Mandal, Sudeb Dasgupta, Anand Bulusu
2020	J	`jnl`	Design and Realization of High-Speed Low-Noise Multi-Loop Skew-Based ROs Optimized for Even/Odd Multi-Phase Signals. IEEE Trans. Circuits Syst. Neeraj Mishra, Lalit Dani, Kunal Sanvaniya, Sudeb Dasgupta, Sudipto Chakraborty, Anand Bulusu
2019	—	`ed.`	VLSI Design and Test - 23rd International Symposium, VDAT 2019, Indore, India, July 4-6, 2019, Revised Selected Papers VDAT Anirban Sengupta, Sudeb Dasgupta, Virendra Singh, Rohit Sharma, Santosh Kumar Vishvakarma
2018	J	`jnl`	Selected Articles from VDAT 2017 Conference. J. Low Power Electron. Sudip Roy, Brajesh Kumar Kaushik, Sudeb Dasgupta
2017	—	`ed.`	VLSI Design and Test - 21st International Symposium, VDAT 2017, Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers VDAT Brajesh Kumar Kaushik, Sudeb Dasgupta, Virendra Singh
2016	Misc	`conf`	FinFET Device Circuit Co-design Issues: Impact of Circuit Parameters on Delay. VLSID Archana Pandey, Harsh Kumar, Praanshu Goyal, Sudeb Dasgupta, S. K. Manhas, Anand Bulusu
2016	Misc	`conf`	Metal Carbon Nanotube Schottky Barrier Diode with Detection of Polar Non-polar Gases. VLSID Sarvesh Agarwal, S. K. Manhas, Sudeb Dasgupta, Neeraj Jain
2016	J	`jnl`	Oxide thickness and S/D junction depth based variation aware OTA design using underlap FinFET. Microelectron. J. Ashutosh Nandi, Ashok K. Saxena, Sudeb Dasgupta
2015	J	`jnl`	An 8 bit, 100 kS/s, switch-capacitor DAC SAR ADC for RFID applications. Microelectron. J. Ashish Joshi, S. K. Manhas, Satinder K. Sharma, Sudeb Dasgupta
2015	—	`conf`	Efficient static D-latch standard cell characterization using a novel setup time model. ISQED Arvind Kumar Sharma, Yogendra Sharma, Sudeb Dasgupta, Bulusu Anand
2015	J	`jnl`	Low power SRAM design for 14 nm GAA Si-nanowire technology. Microelectron. J. Gaurav Kaushal, H. Jeong, Satish Maheshwaram, S. K. Manhas, Sudeb Dasgupta, Seong-Ook Jung
2015	—	`conf`	Pre-layout estimation of performance and design of basic analog circuits in stress enabled technologies. VDAT Arvind Kumar Sharma, Neeraj Mishra, Naushad Alam, Sudeb Dasgupta, Anand Bulusu
2015	Misc	`conf`	Tutorial T6: FinFET Device Circuit Co-design: Issues and Challenges. VLSID Sudeb Dasgupta, Bulusu Anand
2014	J	`jnl`	An Analytical Delay Model for Mechanical Stress Induced Systematic Variability Analysis in Nanoscale Circuit Design. IEEE Trans. Circuits Syst. I Regul. Pap. Naushad Alam, Bulusu Anand, Sudeb Dasgupta
2014	Misc	`conf`	Analytical Modeling of Sub-onset Current of Tunnel Field Effect Transistor. VLSID Parmanand Singh, Vivek Asthana, Radhakrishnan Sithanandam, Anand Bulusu, Sudeb Dasgupta
2013	—	`conf`	A Modified Gate Replacement Algorithm for Leakage Reduction Using Dual-T VDAT Surabhi Singh, Brajesh Kumar Kaushik, Sudeb Dasgupta
2013	—	`conf`	Analysis of Crosstalk Deviation for Bundled MWCNT with Process Induced Height and Width Variations. VDAT Jainender Kumar, Manoj Kumar Majumder, Brajesh Kumar Kaushik, Sudeb Dasgupta
2013	—	`conf`	Optimization of Underlap FinFETs and Its SRAM Performance Projections Using High- VDAT Pankaj Kumar Pal, Brajesh Kumar Kaushik, Sudeb Dasgupta
2013	J	`jnl`	The impact of process-induced mechanical stress in narrow width devices and variable-taper CMOS buffer design. Microelectron. Reliab. Naushad Alam, Bulusu Anand, Sudeb Dasgupta
2013	J	`jnl`	The impact of process-induced mechanical stress on CMOS buffer design using multi-fingered devices. Microelectron. Reliab. Naushad Alam, Bulusu Anand, Sudeb Dasgupta
2013	J	`jnl`	Two dimensional analytical modeling for asymmetric 3T and 4T double gate tunnel FET in sub-threshold region: Potential and electric field. Microelectron. J. Menka Yadav, Anand Bulusu, Sudeb Dasgupta
2012	—	`conf`	An accurate current source model for CMOS based combinational logic cell. ISQED Baljit Kaur, Sandeep Vundavalli, S. K. Manhas, Sudeb Dasgupta, Bulusu Anand
2012	—	`conf`	Analog Performance Analysis of Dual-k Spacer Based Underlap FinFET. VDAT Ashutosh Nandi, Ashok K. Saxena, Sudeb Dasgupta
2012	J	`jnl`	Analysis of double-gate FinFET-based address decoder for radiation-induced single-event-transients. IET Circuits Devices Syst. Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta
2012	J	`jnl`	Dg-FinFET-Based SRAM Configurations for Increased SEU Immunity. J. Circuits Syst. Comput. Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta
2012	—	`conf`	Impact of Dummy Poly on the Process-Induced Mechanical Stress Enhanced Circuit Performance. VDAT Naushad Alam, Bulusu Anand, Sudeb Dasgupta
2012	J	`jnl`	Impact of dual-k spacer on analog performance of underlap FinFET. Microelectron. J. Ashutosh Nandi, Ashok K. Saxena, Sudeb Dasgupta
2012	—	`conf`	Process induced mechanical stress aware poly-pitch optimization for enhanced circuit performance. ISQED Naushad Alam, Bulusu Anand, Sudeb Dasgupta
2012	—	`conf`	The Impact of Process-Induced Mechanical Stress in Narrow Width Devices and Circuit Design Issues. ISED Naushad Alam, Bulusu Anand, Sudeb Dasgupta
2011	—	`conf`	A Proposed Output Buffer at 90 nm Technology with Minimum Signal Switching Noise at 83.3MHz. ISVLSI Arnab Kumar Biswas, Anand Bulusu, Sudeb Dasgupta
2011	J	`jnl`	A low-noise, process-variation-tolerant double-gate FinFET based sense amplifier. Microelectron. Reliab. Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta
2011	J	`jnl`	Alpha-particle-induced effects in partially depleted silicon on insulator device: With and without body contact. IET Circuits Devices Syst. Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta
2011	J	`jnl`	Analytical modeling of subthreshold current and subthreshold swing of an underlap DGMOSFET with tied-independent gate and symmetric-asymmetric options. Microelectron. J. Ramesh Vaddi, R. P. Agarwal, Sudeb Dasgupta
2011	—	`conf`	Effect of Gate-S/D Underlap, Asymmetric and Independent Gate Features in the Minimization of Short Channel Effects in Nanoscale DGMOSFET. ISVLSI Ramesh Vaddi, Sudeb Dasgupta, R. P. Agarwal
2011	J	`jnl`	Electrical performance study of 25 nm Omega-FinFET under the influence of gamma radiation: A 3D simulation. Microelectron. J. Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta
2011	J	`jnl`	Modeling and estimation of edge direct tunneling current for nanoscale metal gate (Hf/AlN Microelectron. J. Santosh Kumar Vishvakarma, V. Komal Kumar, Ashok K. Saxena, Sudeb Dasgupta
2011	J	`jnl`	Process Variation Tolerant FinFET Based Robust Low Power SRAM Cell Design at 32 nm Technology. J. Low Power Electron. Balwinder Raj, Jatin Mitra, Deepak Kumar Bihani, V. Rangharajan, Ashok K. Saxena, Sudeb Dasgupta
2011	—	`conf`	Quantum Mechanical Analytical Drain Current Modeling and Simulation for Double Gate FinFET Device Using Quasi Fermi Potential Approach. SocProS (2) Balwinder Raj, Ashok K. Saxena, Sudeb Dasgupta
2010	J	`jnl`	A proposed DG-FinFET based SRAM cell design with RadHard capabilities. Microelectron. Reliab. Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta
2010	J	`jnl`	Comparison of nano-scale complementary metal-oxide semiconductor and 3T-4T double gate fin-shaped field-effect transistors for robust and energy-efficient subthreshold logic. IET Circuits Devices Syst. Ramesh Vaddi, Sudeb Dasgupta, R. P. Agarwal
2010	—	`conf`	Quantum Inversion Charge and Drain Current Analysis for Double Gate FinFET Device: Analytical Modeling and TCAD Simulation Approach. EMS Balwinder Raj, Ashok K. Saxena, Sudeb Dasgupta
2010	J	`jnl`	Robust Double Gate FinFET Based Sense Amplifier Design Using Independent Gate Control. J. Low Power Electron. Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta
2010	J	`jnl`	Robust and Ultra Low Power Subthreshold Logic Circuits with Symmetric, Asymmetric, 3T, 4T DGFinFETs. J. Low Power Electron. Ramesh Vaddi, Sudeb Dasgupta, R. P. Agarwal
2010	J	`jnl`	Robustness comparison of DG FinFETs with symmetric, asymmetric, tied and independent gate options with circuit co-design for ultra low power subthreshold logic. Microelectron. J. Ramesh Vaddi, Sudeb Dasgupta, R. P. Agarwal
2009	—	`conf`	A 1.2 volt, 90nm, 16-bit three way segmented digital to analog converter (DAC) for low power applications. ISQED Maruthi Chandrasekhar Bh, Sudeb Dasgupta
2009	J	`jnl`	Design of Low Power Adiabatic SRAM Using DTGAL, CPAL and ACPL: A Comparative Study. J. Low Power Electron. Y. K. Sudharshan, D. Sreenu, Ashok K. Saxena, Sudeb Dasgupta
2009	J	`jnl`	Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultralow-Power Applications. VLSI Design Ramesh Vaddi, Sudeb Dasgupta, R. P. Agarwal
2008	J	`jnl`	Modeling of Leakage Current Mechanisms in Nanoscale DG MOSFET and its Application to Low Power SRAM Design. J. Comput. Deblina Sarkar, Deepanjan Datta, Sudeb Dasgupta
2007	Misc	`conf`	Modeling of Leakages in Nano-Scale DG MOSFET to Implement Low Power SRAM: A Device/Circuit Co-Design. VLSI Design Deblina Sarkar, Samiran Ganguly, Deepanjan Datta, A. Ananda Prasad Sarab, Sudeb Dasgupta
2006	J	`jnl`	Two-dimensional numerical modeling of lightly doped nano-scale double-gate MOSFET. Microelectron. J. Deepanjan Datta, A. Ananda Prasad Sarab, Sudeb Dasgupta