Sudarshan K. Srinivasan

54 papers A* 1A 6B 1C 9Journal 25Unranked 10
YearRankTypeTitle / Venue / Authors
2026 J jnl
Formally Verifying Quantum Phase Estimation Circuits with 1,000+ Qubits.
CoRR
Arun Govindankutty, Sudarshan K. Srinivasan
2025 J jnl
Superposition-Based Abstractions for Quantum Data Encoding Verification.
IET Quantum Commun.
Arun Govindankutty, Sudarshan K. Srinivasan
2024 C conf
Formal Verification For Cyclic Quantum Walk Circuits.
ISCAS
Benedicto James Sitou Campbell, Sudarshan K. Srinivasan
2023 — conf
Hardware Mitigation and Verification For Rogue In-Flight Data Load Attacks.
ICECS
Nimish Mathure, Sudarshan K. Srinivasan, Kushal K. Ponugoti, Arun Govindankutty
2023 J jnl
Rotational Abstractions for Verification of Quantum Fourier Transform Circuits.
CoRR
Arun Govindankutty, Sudarshan K. Srinivasan, Nimish Mathure
2023 J jnl
Rotational abstractions for verification of quantum Fourier transform circuits.
IET Quantum Commun.
Arun Govindankutty, Sudarshan K. Srinivasan, Nimish Mathure
2023 J jnl
Verification of serialising instructions for security against transient execution attacks.
IET Comput. Digit. Tech.
Kushal K. Ponugoti, Sudarshan K. Srinivasan, Nimish Mathure
2022 J jnl
A Refinement-Based Approach to Spectre Invulnerability Verification.
IEEE Access
Nimish Mathure, Sudarshan K. Srinivasan, Kushal K. Ponugoti
2022 J jnl
Illegal Trojan design and detection in asynchronous NULL Convention Logic and Sleep Convention Logic circuits.
IET Comput. Digit. Tech.
Kushal K. Ponugoti, Sudarshan K. Srinivasan, Scott C. Smith, Nimish Mathure
2021 — conf
Formal Verification Approach to Detect Always-On Denial of Service Trojans in Pipelined Circuits.
ICECS
Kushal K. Ponugoti, Sudarshan K. Srinivasan, Nimish Mathure
2020 — conf
A Formal Verification Approach for Detecting Opcode Trojans.
ICECS
Nimish Mathure, Sudarshan K. Srinivasan, Kushal K. Ponugoti, Akansha Malik, Samuel Quanbeck
2020 — conf
Exploiting Dual-Rail Register Invariants for Equivalence Verification of NCL Circuits.
MWSCAS
Son N. Le, Sudarshan K. Srinivasan, Scott C. Smith
2020 — conf
Formal Verification of Completion-Completeness for NCL Circuits.
MWSCAS
Son N. Le, Sudarshan K. Srinivasan, Scott C. Smith
2020 — conf
Hardware Trojan Design and Detection in Asynchronous NCL Circuits.
ICECS
Kushal K. Ponugoti, Sudarshan K. Srinivasan, Scott C. Smith
2020 J jnl
Improved Efficiency of Object Code Verification Using Statically Abstracted Object Code.
Sci. Program.
N. Shaukat, Sana Shuja, Sudarshan K. Srinivasan, Shaista Jabeen
2019 J jnl
A Reliable IoT-Based Embedded Health Care System for Diabetic Patients.
CoRR
Zeyad A. Al-Odat, Sudarshan K. Srinivasan, Eman M. Al-Qtiemat, Sana Shuja
2019 C conf
An Equivalence Verification Methodology for Asynchronous Sleep Convention Logic Circuits.
ISCAS
Mousam Hossain, Ashiq A. Sakib, Sudarshan K. Srinivasan, Scott C. Smith
2019 J jnl
Formal Modeling and Verification of PCHB Asynchronous Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Ashiq A. Sakib, Scott C. Smith, Sudarshan K. Srinivasan
2018 — conf
An Equivalence Verification Methodology for Combinational Asynchronous PCHB Circuits.
MWSCAS
Ashiq A. Sakib, Scott C. Smith, Sudarshan K. Srinivasan
2018 J jnl
IoT-Based Secure Embedded Scheme for Insulin Pump Data Acquisition and Monitoring.
CoRR
Zeyad A. Al-Odat, Sudarshan K. Srinivasan, Eman Al-qtiemat, Mohana Asha Latha Dubasi, Sana Shuja
2017 — conf
Formal modeling and verification for pre-charge half buffer gates and circuits.
MWSCAS
Ashiq A. Sakib, Scott C. Smith, Sudarshan K. Srinivasan
2017 J jnl
Formal verification methodology for real-time Field Programmable Gate Array.
IET Comput. Digit. Tech.
Shaista Jabeen, Sudarshan K. Srinivasan, Sana Shuja
2015 J jnl
A Formal Verification Methodology for DDD Mode Pacemaker Control Programs.
J. Electr. Comput. Eng.
Sana Shuja, Sudarshan K. Srinivasan, Shaista Jabeen, Dharmakeerthi Nawarathna
2015 J jnl
A Formal Verification Methodology for FPGA-Based Stepper Motor Control.
IEEE Embed. Syst. Lett.
Shaista Jabeen, Sudarshan K. Srinivasan, Sana Shuja, Mohana Asha Latha Dubasi
2014 C conf
Equivalence verification for NULL Convention Logic (NCL) circuits.
ICCD
Vidura Wijayasekara, Sudarshan K. Srinivasan, Scott C. Smith
2014 — conf
Timed Refinement for Verification of Real-Time Object Code Programs.
VSTTE
Mohana Asha Latha Dubasi, Sudarshan K. Srinivasan, Vidura Wijayasekara
2013 C conf
Equivalence checking for synchronous elastic circuits.
MEMOCODE
Vidura Wijaysekara, Sudarshan K. Srinivasan
2013 J jnl
Modeling and Analysis of State-of-the-art VM-based Cloud Management Platforms.
IEEE Trans. Cloud Comput.
Saif Ur Rehman Malik, Samee U. Khan, Sudarshan K. Srinivasan
2012 J jnl
Refinement-based verification of elastic pipelined systems.
IET Comput. Digit. Tech.
Sudarshan K. Srinivasan, Y. Cai, Koushik Sarker
2011 B conf
Desynchronization: design for verification.
FMCAD
Sudarshan K. Srinivasan, Raj S. Katti
2011 J jnl
On the Security of Randomized Arithmetic Codes Against Ciphertext-Only Attacks.
IEEE Trans. Inf. Forensics Secur.
Raj S. Katti, Sudarshan K. Srinivasan, Aida Vosoughi
2010 J jnl
Automatic Refinement Checking of Pipelines with Out-of-Order Execution.
IEEE Trans. Computers
Sudarshan K. Srinivasan
2010 C conf
Joint optimal placement of PMU and conventional measurements in power systems.
ISCAS
Rajesh Kavasseri, Sudarshan K. Srinivasan
2010 J jnl
Optimization Techniques for Verification of Out-of-Order Execution Machines.
J. Electr. Comput. Eng.
Sudarshan K. Srinivasan
2010 — ch.
Verifying Pipelines with BAT.
Design and Verification of Microprocessor Systems for High-Assurance Applications
Panagiotis Manolios, Sudarshan K. Srinivasan
2009 C conf
Efficient Hardware Implementation of a New Pseudo-random Bit Sequence Generator.
ISCAS
Raj S. Katti, Sudarshan K. Srinivasan
2009 J jnl
Token-Aware Completion Functions for Elastic Processor Verification.
J. Electr. Comput. Eng.
Sudarshan K. Srinivasan, Koushik Sarker, Rajendra S. Katti
2009 C conf
Verification of Desynchronized Circuits.
ISCAS
Sudarshan K. Srinivasan, Raj S. Katti
2009 J jnl
Verification of Synchronous Elastic Processors.
IEEE Embed. Syst. Lett.
Sudarshan K. Srinivasan, Koushik Sarker, Rajendra S. Katti
2008 J jnl
A Refinement-Based Compositional Reasoning Framework for Pipelined Machine Verification.
IEEE Trans. Very Large Scale Integr. Syst.
Panagiotis Manolios, Sudarshan K. Srinivasan
2008 J jnl
Automatic verification of safety and liveness for pipelined machines using WEB refinement.
ACM Trans. Design Autom. Electr. Syst.
Panagiotis Manolios, Sudarshan K. Srinivasan
2007 A* conf
BAT: The Bit-Level Analysis Tool.
CAV
Panagiotis Manolios, Sudarshan K. Srinivasan, Daron Vroon
2007 — —
Efficient Verification of Bit-Level Pipelined Machines Using Refinement.
Sudarshan K. Srinivasan
2006 J jnl
A Framework for Verifying Bit-Level Pipelined Machines Based on Automated Deduction and Decision Procedures.
J. Autom. Reason.
Panagiotis Manolios, Sudarshan K. Srinivasan
2006 A conf
Automatic memory reductions for RTL model verification.
ICCAD
Panagiotis Manolios, Sudarshan K. Srinivasan, Daron Vroon
2006 A conf
Monolithic verification of deep pipelines with collapsed flushing.
DATE
Roma Kane, Panagiotis Manolios, Sudarshan K. Srinivasan
2005 — conf
A Parameterized Benchmark Suite of Hard Pipelined-Machine-Verification Problems.
CHARME
Panagiotis Manolios, Sudarshan K. Srinivasan
2005 A conf
A complete compositional reasoning framework for the efficient verification of pipelined machines.
ICCAD
Panagiotis Manolios, Sudarshan K. Srinivasan
2005 C conf
A computationally ef~cient method based on commitment re~nement maps for verifying pipelined machines.
MEMOCODE
Panagiotis Manolios, Sudarshan K. Srinivasan
2005 A conf
Refinement Maps for Efficient Verification of Processor Models.
DATE
Panagiotis Manolios, Sudarshan K. Srinivasan
2005 A conf
Verification of executable pipelined machines with bit-level interfaces.
ICCAD
Panagiotis Manolios, Sudarshan K. Srinivasan
2004 A conf
Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements.
DATE
Panagiotis Manolios, Sudarshan K. Srinivasan
2003 J jnl
Combining data remapping and voltage/frequency scaling of second level memory for energy reduction in embedded systems.
Microelectron. J.
Jun-Cheol Park, Vincent John Mooney III, Sudarshan K. Srinivasan
2003 C conf
Formal Verification of an Intel XScale Processor Model with Scoreboarding, Specialized Execution Pipelines, and Impress Data-Memory Exceptions.
MEMOCODE
Sudarshan K. Srinivasan, Miroslav N. Velev