Sudarshan Banerjee

20 papers A* 2A 1B 1C 1Misc 4Journal 8Unranked 3
YearRankTypeTitle / Venue / Authors
2010 J jnl
Bandwidth Management in Application Mapping for Dynamically Reconfigurable Architectures.
ACM Trans. Reconfigurable Technol. Syst.
Sudarshan Banerjee, Elaheh Bozorgzadeh, Juanjo Noguera, Nikil D. Dutt
2009 J jnl
Exploiting Application Data-Parallelism on Dynamically Reconfigurable Architectures: Placement and Architectural Considerations.
IEEE Trans. Very Large Scale Integr. Syst.
Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt
2009 J jnl
Strip packing with precedence constraints and strip packing with release times.
Theor. Comput. Sci.
John Augustine, Sudarshan Banerjee, Sandy Irani
2008 J jnl
Energy-aware cosynthesis of real-time multimedia applications on MPSoCs using heterogeneous scheduling policies.
ACM Trans. Embed. Comput. Syst.
Minyoung Kim, Sudarshan Banerjee, Nikil D. Dutt, Nalini Venkatasubramanian
2007 C conf
Energy-aware co-processor selection for embedded processors on FPGAs.
ICCD
Amir Hossein Gholamipour, Elaheh Bozorgzadeh, Sudarshan Banerjee
2007 J jnl
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement
CoRR
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne
2007 A* conf
Selective Band width and Resource Management in Scheduling for Dynamically Reconfigurable Architectures.
DAC
Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt, Juanjo Noguera
2006 Misc conf
Design space exploration of real-time multi-media MPSoCs with heterogeneous scheduling policies.
CODES+ISSS
Minyoung Kim, Sudarshan Banerjee, Nikil D. Dutt, Nalini Venkatasubramanian
2006 J jnl
ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors.
IEEE Trans. Very Large Scale Integr. Syst.
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne
2006 J jnl
Integrating Physical Constraints in HW-SW Partitioning for Architectures With Partial Dynamic Reconfiguration.
IEEE Trans. Very Large Scale Integr. Syst.
Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt
2006 — conf
Minimizing peak power for application chains on architectures with partial dynamic reconfiguration.
FPT
Sudarshan Banerjee, Elaheh Bozorgzadeh, Juanjo Noguera, Nikil D. Dutt
2006 — conf
PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures.
ASP-DAC
Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt
2006 Misc conf
Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core.
VLSI Design
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Paolo Ienne, Laura Pozzi
2006 B conf
Strip packing with precedence constraints and strip packing with release times.
SPAA
John Augustine, Sudarshan Banerjee, Sandy Irani
2005 Misc conf
Considering Run-Time Reconfiguration Overhead in Task Graph Transformations for Dynamically Reconfigurable Architectures.
FCCM
Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt
2005 A conf
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement.
DATE
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne
2005 A* conf
Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration.
DAC
Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt
2004 Misc conf
Efficient search space exploration for HW-SW partitioning.
CODES+ISSS
Sudarshan Banerjee, Nikil D. Dutt
2004 — conf
FIFO power optimization for on-chip networks.
ACM Great Lakes Symposium on VLSI
Sudarshan Banerjee, Nikil D. Dutt
1997 J jnl
Parallel Algorithms for Finding the Most Vital Edge in Weighted Graphs.
J. Parallel Distributed Comput.
Sudarshan Banerjee, Sanjeev Saxena