Sudarshan Bahukudumbi

13 papers A 2Misc 3Journal 5Unranked 2
YearRankTypeTitle / Venue / Authors
2009 J jnl
Power Management Using Test-Pattern Ordering for Wafer-Level Test During Burn-In.
IEEE Trans. Very Large Scale Integr. Syst.
Sudarshan Bahukudumbi, Krishnendu Chakrabarty
2009 J jnl
Test-Length and TAM Optimization for Wafer-Level Reduced Pin-Count Testing of Core-Based SoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sudarshan Bahukudumbi, Krishnendu Chakrabarty
2009 J jnl
Wafer-Level Defect Screening for "Big-D/Small-A" Mixed-Signal SoCs.
IEEE Trans. Very Large Scale Integr. Syst.
Sudarshan Bahukudumbi, Sule Ozev, Krishnendu Chakrabarty, Vikram Iyengar
2008 — conf
Power Management for Wafer-Level Test During Burn-In.
ATS
Sudarshan Bahukudumbi, Krishnendu Chakrabarty
2008 J jnl
Power-aware SoC test planning for effective utilization of port-scalable testers.
ACM Trans. Design Autom. Electr. Syst.
Anuja Sehgal, Sudarshan Bahukudumbi, Krishnendu Chakrabarty
2008 A conf
Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs.
DATE
Sudarshan Bahukudumbi, Krishnendu Chakrabarty, Richard Kacprowicz
2008 Misc conf
Test-Pattern Ordering for Wafer-Level Test-During-Burn-In.
VTS
Sudarshan Bahukudumbi, Krishnendu Chakrabarty
2008 — —
Wafer-Level Testing and Test Planning for Integrated Circuits.
Sudarshan Bahukudumbi
2007 — conf
AWafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for "Big-D/Small-A" Mixed-Signal SoCs.
ASP-DAC
Sudarshan Bahukudumbi, Sule Ozev, Krishnendu Chakrabarty, Vikram Iyengar
2007 Misc conf
Test-Length Selection and TAM Optimization for Wafer-Level, Reduced Pin-Count Testing of Core-Based Digital SoCs.
VLSI Design
Sudarshan Bahukudumbi, Krishnendu Chakrabarty
2007 J jnl
Wafer-Level Modular Testing of Core-Based SoCs.
IEEE Trans. Very Large Scale Integr. Syst.
Sudarshan Bahukudumbi, Krishnendu Chakrabarty
2006 A conf
Defect-Oriented and Time-Constrained Wafer-Level Test-Length Selection for Core-Based Digital SoCs.
ITC
Sudarshan Bahukudumbi, Krishnendu Chakrabarty
2005 Misc conf
A Low Overhead High Speed Histogram Based Test Methodology for Analog Circuits and IP Cores.
VLSI Design
Sudarshan Bahukudumbi, Krishna Bharath