Suchita Pati

19 papers B 4Journal 11Unranked 4
YearRankTypeTitle / Venue / Authors
2025 B conf
ConCCL: Optimizing ML Concurrent Computation and Communication with GPU DMA Engines.
ISPASS
Anirudha Agrawal, Shaizeen Aga, Suchita Pati, Mahzabeen Islam
2025 J jnl
DMA Collectives for Efficient ML Communication Offloads.
CoRR
Suchita Pati, Mahzabeen Islam, Shaizeen Aga, Mohamed Assem Ibrahim
2025 J jnl
Design Space Exploration of DMA based Finer-Grain Compute Communication Overlap.
CoRR
Shagnik Pal, Shaizeen Aga, Suchita Pati, Mahzabeen Islam, Lizy K. John
2025 J jnl
GOLDYLOC: Global Optimizations & Lightweight Dynamic Logic for Concurrency.
ACM Trans. Archit. Code Optim.
Suchita Pati, Shaizeen Aga, Nuwan Jayasena, Matthew D. Sinclair
2024 J jnl
Global Optimizations & Lightweight Dynamic Logic for Concurrency.
CoRR
Suchita Pati, Shaizeen Aga, Nuwan Jayasena, Matthew D. Sinclair
2024 — conf
JIT-Q: Just-in-time Quantization with Processing-In-Memory for Efficient ML Training.
MLSys
Mohamed Assem Ibrahim, Shaizeen Aga, Ada Li, Suchita Pati, Mahzabeen Islam
2024 J jnl
Optimizing ML Concurrent Computation and Communication with GPU DMA Engines.
CoRR
Anirudha Agrawal, Shaizeen Aga, Suchita Pati, Mahzabeen Islam
2024 — conf
T3: Transparent Tracking & Triggering for Fine-grained Overlap of Compute & Collectives.
ASPLOS (2)
Suchita Pati, Shaizeen Aga, Mahzabeen Islam, Nuwan Jayasena, Matthew D. Sinclair
2024 J jnl
T3: Transparent Tracking & Triggering for Fine-grained Overlap of Compute & Collectives.
CoRR
Suchita Pati, Shaizeen Aga, Mahzabeen Islam, Nuwan Jayasena, Matthew D. Sinclair
2023 J jnl
Computation vs. Communication Scaling for Future Transformers on Future Hardware.
CoRR
Suchita Pati, Shaizeen Aga, Mahzabeen Islam, Nuwan Jayasena, Matthew D. Sinclair
2023 J jnl
Just-in-time Quantization with Processing-In-Memory for Efficient ML Training.
CoRR
Mohamed Assem Ibrahim, Shaizeen Aga, Ada Li, Suchita Pati, Mahzabeen Islam
2023 — conf
Tale of Two Cs: Computation vs. Communication Scaling for Future Transformers on Future Hardware.
IISWC
Suchita Pati, Shaizeen Aga, Mahzabeen Islam, Nuwan Jayasena, Matthew D. Sinclair
2022 — conf
Demystifying BERT: System Design Implications.
IISWC
Suchita Pati, Shaizeen Aga, Nuwan Jayasena, Matthew D. Sinclair
2021 J jnl
Demystifying BERT: Implications for Accelerator Design.
CoRR
Suchita Pati, Shaizeen Aga, Nuwan Jayasena, Matthew D. Sinclair
2020 B conf
SeqPoint: Identifying Representative Iterations of Sequence-Based Neural Networks.
ISPASS
Suchita Pati, Shaizeen Aga, Matthew D. Sinclair, Nuwan Jayasena
2020 J jnl
SeqPoint: Identifying Representative Iterations of Sequence-based Neural Networks.
CoRR
Suchita Pati, Shaizeen Aga, Matthew D. Sinclair, Nuwan Jayasena
2019 B conf
Analyzing Machine Learning Workloads Using a Detailed GPU Simulator.
ISPASS
Jonathan S. Lew, Deval A. Shah, Suchita Pati, Shaylin Cattell, Mengchi Zhang, Amruth Sandhupatla, Christopher Ng, Negar Goli, Matthew D. Sinclair, Timothy G. Rogers, Tor M. Aamodt
2018 J jnl
Analyzing Machine Learning Workloads Using a Detailed GPU Simulator.
CoRR
Jonathan S. Lew, Deval Shah, Suchita Pati, Shaylin Cattell, Mengchi Zhang, Amruth Sandhupatla, Christopher Ng, Negar Goli, Matthew D. Sinclair, Timothy G. Rogers, Tor M. Aamodt
2017 B conf
DARTS: Performance-counter driven sampling using binary translators.
ISPASS
Rajesh Kumar, Suchita Pati, Kanishka Lahiri