Suchismita Roy

41 papers A 1C 1Misc 3Journal 27Unranked 9

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	Identification of Hardware Trojan in Gate-Level Netlist. J. Circuits Syst. Comput. Anindan Mondal, Archisman Ghosh, Shubrojyoti Karmakar, Mahabub Hasan Mahalat, Suchismita Roy, Bibhash Sen
2024	—	`conf`	Zero Area Overhead Based Scan-Chain Watermarking. ISED Ashwin CS, Suchismita Roy
2023	J	`jnl`	Hardware Trojan Detection using Transition Probability with Minimal Test Vectors. ACM Trans. Embed. Comput. Syst. Anindan Mondal, Shubrojyoti Karmakar, Mahabub Hasan Mahalat, Suchismita Roy, Bibhash Sen, Anupam Chattopadhyay
2023	J	`jnl`	Non-invasive anaemia detection by examining palm pallor: A smartphone-based approach. Biomed. Signal Process. Control. Abhishek Kesarwani, Sunanda Das, Mamata Dalui, Dakshina Ranjan Kisku, Bibhash Sen, Suchismita Roy, Anupam Basu
2023	J	`jnl`	Smartphone-based non-invasive haemoglobin level estimation by analyzing nail pallor. Biomed. Signal Process. Control. Sunanda Das, Abhishek Kesarwani, Mamata Dalui, Dakshina Ranjan Kisku, Bibhash Sen, Suchismita Roy, Anupam Basu
2023	J	`jnl`	Toward the Generation of Test Vectors for the Detection of Hardware Trojan Targeting Effective Switching Activity. ACM J. Emerg. Technol. Comput. Syst. Anindan Mondal, Debasish Kalita, Archisman Ghosh, Suchismita Roy, Bibhash Sen
2022	J	`jnl`	Congestion-Aware Rectilinear Steiner Tree Construction Using PB-SAT. J. Circuits Syst. Comput. Sudeshna Kundu, Suchismita Roy, Shyamapada Mukherjee
2022	J	`jnl`	Power aware floorplanning in multiple supply voltage domain. Int. J. Circuit Theory Appl. Suchandra Banerjee, Suchismita Roy
2021	J	`jnl`	Hardware Trojan Free Netlist Identification: A Clustering Approach. J. Electron. Test. Anindan Mondal, Rajesh Kumar Biswal, Mahabub Hasan Mahalat, Suchismita Roy, Bibhash Sen
2021	C	`conf`	PUF based Lightweight Authentication and Key Exchange Protocol for IoT. SECRYPT Sourav Roy, Dipnarayan Das, Anindan Mondal, Mahabub Hasan Mahalat, Suchismita Roy, Bibhash Sen
2021	J	`jnl`	Thermal-Driven Floorplanning for Fixed Outline Layouts. J. Circuits Syst. Comput. Suchandra Banerjee, Suchismita Roy
2020	J	`jnl`	Corrigendum to: "Linear time algorithm to cover and hit a set of line segments optimally by two axis-parallel squares" [Theor. Comput. Sci. 769 (2019) 63-74]. Theor. Comput. Sci. Sanjib Sadhu, Xiaozhou He, Sasanka Roy, Subhas C. Nandy, Suchismita Roy
2020	J	`jnl`	Efficient Algorithm for Computing the Triangle Maximizing the Length of Its Smallest Side Inside a Convex Polygon. Int. J. Found. Comput. Sci. Sanjib Sadhu, Sasanka Roy, Soumen Nandi, Subhas C. Nandy, Suchismita Roy
2020	J	`jnl`	Rectilinear Steiner Tree Construction Techniques Using PB-SAT-Based Methodology. J. Circuits Syst. Comput. Sudeshna Kundu, Suchismita Roy, Shyamapada Mukherjee
2019	—	`conf`	A Novel Test Vector Generation Method for Hardware Trojan Detection. SoCC Anindan Mondal, Mahabub Hasan Mahalat, Suraj Mandal, Suchismita Roy, Bibhash Sen
2019	J	`jnl`	A SAT-Based Methodology for Effective Clock Gating for Power Minimization. J. Circuits Syst. Comput. Khushbu Chandrakar, Suchismita Roy
2019	J	`jnl`	An Integrated Framework for Application Independent Testing of FPGA Interconnect. J. Electron. Test. Shukla Banik, Suchismita Roy, Bibhash Sen
2019	J	`jnl`	Application-Dependent Testing of FPGA Interconnect Network. IEEE Trans. Very Large Scale Integr. Syst. Shukla Banik, Suchismita Roy, Bibhash Sen
2019	J	`jnl`	Corrigendum to: "Linear time algorithm to cover and hit a set of line segments optimally by two axis-parallel squares", Theoretical Computer Science 769 (2019) 63-74. CoRR Sanjib Sadhu, Xiaozhou He, Sasanka Roy, Subhas C. Nandy, Suchismita Roy
2019	J	`jnl`	Linear time algorithm to cover and hit a set of line segments optimally by two axis-parallel squares. Theor. Comput. Sci. Sanjib Sadhu, Sasanka Roy, Subhas C. Nandy, Suchismita Roy
2019	Misc	`conf`	Test Configuration Generation for Different FPGA Architectures for Application Independent Testing. VLSID Shukla Banik, Suchismita Roy, Bibhash Sen
2018	J	`jnl`	Power Optimization Techniques for High-Level Designs Using Multiple Voltage Components for Low Power Consumption. J. Low Power Electron. Khushbu Chandrakar, Sudeshna Kundu, Suchismita Roy
2018	—	`conf`	XOR based Methodology to Detect Hardware Trojan utilizing the Transition Probability. ISED Anindan Mondal, Mahabub Hasan Mahalat, Anudeep Reddy Medapati, Suchismita Roy, Bibhash Sen
2017	J	`jnl`	A linear time algorithm to cover and hit a set of line segments optimally by two axis-parallel squares. CoRR Sanjib Sadhu, Sasanka Roy, Subhas C. Nandy, Suchismita Roy
2017	—	`conf`	Computing the Triangle Maximizing the Length of Its Smallest Side Inside a Convex Polygon. ICCSA (2) Sanjib Sadhu, Sasanka Roy, Soumen Nandi, Subhas C. Nandy, Suchismita Roy
2017	—	`conf`	K-nearest neighbour (KNN) approach using SAT based technique for rectilinear steiner tree construction. ISED Sudeshna Kundu, Suchismita Roy, Shyamapada Mukherjee
2017	Misc	`conf`	Optimal Covering and Hitting of Line Segments by Two Axis-Parallel Squares. COCOON Sanjib Sadhu, Sasanka Roy, Subhas C. Nandy, Suchismita Roy
2017	J	`jnl`	Satisfiability Modulo Theory based Methodology for Floorplanning in VLSI Circuits. CoRR Suchandra Banerjee, Anand Ratna, Suchismita Roy
2017	J	`jnl`	Via-Aware Dogleg Routing Using Boolean Satisfiability. J. Circuits Syst. Comput. Shyamapada Mukherjee, Suchismita Roy
2016	J	`jnl`	Nearly-2-SAT Solutions for Segmented-Channel Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shyamapada Mukherjee, Suchismita Roy
2016	—	`conf`	Satisfiability modulo theory based methodology for floorplanning in VLSI circuits. ISED Suchandra Banerjee, Anand Ratna, Suchismita Roy
2015	—	`conf`	Multi terminal net routing for island style FPGAs using nearly-2-SAT computation. VDAT Shyamapada Mukherjee, Suchismita Roy
2015	J	`jnl`	SAT based solutions for detailed routing of island style FPGA architectures. Microelectron. J. Shyamapada Mukherjee, Suchismita Roy
2013	—	`conf`	Congestion Balancing Global Router. VDAT Shyamapada Mukherjee, Jibesh Patra, Suchismita Roy
2013	—	`conf`	SAT based low power binding to reduce switching activity. IC3 Khushbu Chandrakar, Suchismita Roy
2012	J	`jnl`	SAT based timing analysis for fixed and rise/fall gate delay models. Integr. Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta
2010	J	`jnl`	Bounded delay timing analysis and power estimation using SAT. Microelectron. J. Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta
2008	J	`jnl`	Satisfiability Models for Maximum Transition Power. IEEE Trans. Very Large Scale Integr. Syst. Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta
2007	Misc	`conf`	Bounded Delay Timing Analysis Using Boolean Satisfiability. VLSI Design Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta
2007	J	`jnl`	Event propagation for accurate circuit delay calculation using SAT. ACM Trans. Design Autom. Electr. Syst. Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta
2005	A	`conf`	SAT based solutions for consistency problems in formal property specifications for open systems. ICCAD Suchismita Roy, Sayantan Das, Prasenjit Basu, Pallab Dasgupta, Partha Pratim Chakrabarti