Subramanian S. Iyer

50 papers A* 4A 1Journal 22Unranked 23

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	MXFormer: A Microscaling Floating-Point Charge-Trap Transistor Compute-in-Memory Transformer Accelerator. CoRR George Karfakis, Samyak Chakrabarty, Vinod Kurian Jacob, Siyun Qiao, Subramanian S. Iyer, Sudhakar Pamarti, Puneet Gupta
2023	J	`jnl`	A 16-nm 784-Core Digital Signal Processor Array, Assembled as a 2 × 2 Dielet With 10-μm Pitch Interdielet I/O for Runtime Multiprogram Reconfiguration. IEEE J. Solid State Circuits Sumeet Singh Nagi, Uneeb Rathore, Krutikesh Sahoo, Tim Ling, Subramanian S. Iyer, Dejan Markovic
2023	—	`conf`	An 8T eNVSRAM Macro in 22nm FDSOI Standard Logic with Simultaneous Full-Array Data Restore for Secure IoT Devices. ISSCC Sepideh Nouri, Subramanian S. Iyer
2023	A*	`conf`	Hybrid Obfuscation of Chiplet-Based Systems. DAC Yousef Safari, Pooya Aghanoury, Subramanian S. Iyer, Nader Sehatbakhsh, Boris Vaisband
2022	—	`conf`	A 16nm 785GMACs/J 784-Core Digital Signal Processor Array With a Multilayer Switch Box Interconnect, Assembled as a 2×2 Dielet with 10μm-Pitch Inter-Dielet I/O for Runtime Multi-Program Reconfiguration. ISSCC Uneeb Rathore, Sumeet Singh Nagi, Subramanian S. Iyer, Dejan Markovic
2022	J	`jnl`	Accuracy and Resiliency of Analog Compute-in-Memory Inference Engines. ACM J. Emerg. Technol. Comput. Syst. Zhe Wan, Tianyi Wang, Yiming Zhou, Subramanian S. Iyer, Vwani P. Roychowdhury
2021	A*	`conf`	Designing a 2048-Chiplet, 14336-Core Waferscale Processor. DAC Saptadeep Pal, Jingyang Liu, Irina Alam, Nicholas Cebry, Haris Suhail, Shi Bu, Subramanian S. Iyer, Sudhakar Pamarti, Rakesh Kumar, Puneet Gupta
2021	—	`conf`	Large-Scale Quantum System Design on Nb-based Superconducting Silicon Interconnect Fabric. ISQED Yu-Tao Yang, Subramanian S. Iyer
2020	J	`jnl`	A Novel Hierarchical Circuit LUT Model for SOI Technology for Rapid Prototyping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sitansusekhar Roymohapatra, Ganesh R. Gore, Akanksha Yadav, Mahesh B. Patil, Krishnan S. Rengarajan, Subramanian S. Iyer, Maryam Shojaei Baghini
2020	J	`jnl`	Accuracy and Resiliency of Analog Compute-in-Memory Inference Engines. CoRR Zhe Wan, Tianyi Wang, Yiming Zhou, Subramanian S. Iyer, Vwani P. Roychowdhury
2019	J	`jnl`	An Analog Neural Network Computing Engine Using CMOS-Compatible Charge-Trap-Transistor (CTT). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yuan Du, Li Du, Xuefeng Gu, Jieqiong Du, X. Shawn Wang, Boyu Hu, Mingzhe Jiang, Xiaoliang Chen, Subramanian S. Iyer, Mau-Chung Frank Chang
2019	A*	`conf`	Architecting Waferscale Processors - A GPU Case Study. HPCA Saptadeep Pal, Daniel Petrisko, Matthew Tomei, Puneet Gupta, Subramanian S. Iyer, Rakesh Kumar
2019	—	`conf`	Bilayer Passivation Film for Cu Interconnects on Si Interconnect Fabric. IRPS Niloofar Shakoorzadeh, Amir Hanna, Subramanian S. Iyer
2019	—	`conf`	Communication Considerations for Silicon Interconnect Fabric. SLIP Boris Vaisband, Subramanian S. Iyer
2019	—	`conf`	Global and semi-global communication on Si-IF. NOCS Boris Vaisband, Subramanian S. Iyer
2019	—	`conf`	Reliability Evaluation of Silicon Interconnect Fabric Technology. IRPS Kannan K. Thankappan, Adeel Ahmad Bajwa, Boris Vaisband, SivaChandra Jangam, Subramanian S. Iyer
2019	J	`jnl`	Silicon interconnect fabric: A versatile heterogeneous integration platform for AI systems. IBM J. Res. Dev. Subramanian S. Iyer, SivaChandra Jangam, Boris Vaisband
2018	J	`jnl`	80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity. IEEE J. Solid State Circuits Balaji Jayaraman, Derek Leu, Janakiraman Viraraghavan, Alberto Cestero, Ming Yin, John Golz, Rajesh Reddy Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata, Subramanian S. Iyer
2018	A*	`conf`	A Case for Packageless Processors. HPCA Saptadeep Pal, Daniel Petrisko, Adeel Ahmad Bajwa, Puneet Gupta, Subramanian S. Iyer, Rakesh Kumar
2018	—	`conf`	A deep learning approach to spine segmentation using a feed-forward chain of pixel-wise convolutional networks. ISBI William Whitehead, Steven Moran, Bilwaj Gaonkar, Luke Macyszyn, Subramanian S. Iyer
2018	—	`conf`	Network on interconnect fabric. ISQED Boris Vaisband, Adeel Ahmad Bajwa, Subramanian S. Iyer
2018	—	`conf`	Reliability challenges in advance packaging. IRPS Subramanian S. Iyer, Adeel Ahmad Bajwa
2017	—	`conf`	Advanced Packaging and Heterogeneous Integration to Reboot Computing. ICRC Saptadeep Pal, Subramanian S. Iyer, Puneet Gupta
2017	J	`jnl`	Assessing Benefits of a Buried Interconnect Layer in Digital Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Liheng Zhu, Yasmine Badr, Shaodi Wang, Subramanian S. Iyer, Puneet Gupta
2017	—	`conf`	Heterogeneous SoCs. VLSI-DAT Subramanian S. Iyer
2017	—	`conf`	Integrated neural interfaces. MWSCAS Ross M. Walker, Loren Rieth, Subramanian S. Iyer, Adeel Ahmad Bajwa, Jason Silver, Taufiq Ahmed, Naila Tasneem, Mohit Sharma, A. Tye Gardner
2017	J	`jnl`	Toward Human-Scale Brain Computing Using 3D Wafer Scale Integration. ACM J. Emerg. Technol. Comput. Syst. Arvind Kumar, Zhe Wan, Winfried W. Wilcke, Subramanian S. Iyer
2016	—	`conf`	80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity. VLSI Circuits Janakiraman Viraraghavan, Derek Leu, Balaji Jayaraman, Alberto Cestero, Robert Kilker, Ming Yin, John Golz, Rajesh Reddy Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata, Subramanian S. Iyer
2016	J	`jnl`	A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access. IEEE J. Solid State Circuits Gregory Fredeman, Donald W. Plass, Abraham Mathews, Janakiraman Viraraghavan, Kenneth Reyer, Thomas J. Knips, Thomas Miller, Elizabeth L. Gerhard, Dinesh Kannambadi, Chris Paone, Dongho Lee, Daniel Rainey, Michael A. Sperling, Michael Whalen, Steven Burns, Rajesh Reddy Tummuru, Herbert Ho, Alberto Cestero, Norbert Arnold, Babar A. Khan, Toshiaki Kirihata, Subramanian S. Iyer
2016	J	`jnl`	Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias. IEEE J. Emerg. Sel. Topics Circuits Syst. Toshiaki Kirihata, John Golz, Matthew R. Wordeman, Pooja Batra, Gary W. Maier, Norman Robson, Troy L. Graves-abe, Daniel Berger, Subramanian S. Iyer
2015	—	`conf`	Impact of 3D copper TSV integration on 32SOI FEOL and BEOL reliability. IRPS Mukta G. Farooq, Giuseppe La Rosa, Fen Chen, Prakash Periasamy, Troy L. Graves-abe, Chandrasekharan Kothandaraman, C. Collins, W. Landers, J. Oakley, J. Liu, John Safran, S. Ghosh, S. Mittl, D. Ioannou, Carole Graas, Daniel Berger, Subramanian S. Iyer
2015	—	`conf`	Invited talk: Some challenges in scaling 3D ICs to a broader application set. 3DIC Subramanian S. Iyer
2015	—	`conf`	Oxygen vacancy traps in Hi-K/Metal gate technologies and their potential for embedded memory applications. IRPS Chandrasekharan Kothandaraman, X. Chen, Dan Moy, Dallas Lea, Sami Rosenblatt, Faraz Khan, Derek Leu, Toshiaki Kirihata, D. Ioannou, Giuseppe La Rosa, Jeffrey B. Johnson, Norman Robson, Subramanian S. Iyer
2014	J	`jnl`	Silicon stress: technical perspective. Commun. ACM Subramanian S. Iyer
2013	J	`jnl`	A Self-Authenticating Chip Architecture Using an Intrinsic Fingerprint of Embedded DRAM. IEEE J. Solid State Circuits Sami Rosenblatt, Srivatsan Chellappa, Alberto Cestero, Norman Robson, Toshiaki Kirihata, Subramanian S. Iyer
2013	J	`jnl`	Field Tolerant Dynamic Intrinsic Chip ID Using 32 nm High-K/Metal Gate SOI Embedded DRAM. IEEE J. Solid State Circuits Sami Rosenblatt, Daniel Fainstein, Alberto Cestero, John Safran, Norman Robson, Toshiaki Kirihata, Subramanian S. Iyer
2012	—	`conf`	Dynamic intrinsic chip ID using 32nm high-K/metal gate SOI embedded DRAM. VLSIC Daniel Fainstein, Sami Rosenblatt, Alberto Cestero, Norman Robson, Toshiaki Kirihata, Subramanian S. Iyer
2012	—	`conf`	Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond. ICICDT Balaji Jayaraman, Sneha Gupta, Yanli Zhang, Puneet Goyal, Herbert Ho, Rishikesh Krishnan, Sunfei Fang, Sungjae Lee, Douglas Daley, Kevin McStay, Bernhard Wunder, John Barth, Sadanand Deshpande, Paul C. Parries, Rajeev Malik, Paul D. Agnello, Scott R. Stiffler, Subramanian S. Iyer
2011	J	`jnl`	3D integration review. Sci. China Inf. Sci. Mukta G. Farooq, Subramanian S. Iyer
2011	J	`jnl`	45-nm silicon-on-insulator CMOS technology integrating embedded DRAM for high-performance server and ASIC applications. IBM J. Res. Dev. Subramanian S. Iyer, Greg G. Freeman, Colin Brodsky, Anthony I. Chou, Dan Corliss, Sameer H. Jain, Naftali E. Lustig, Vincent McGahay, Shreesh Narasimha, James P. Norum, Karen A. Nummy, Paul C. Parries, Sujatha Sankaran, Chris D. Sheraw, Pushkara Rao Varanasi, Geng Wang, Mary E. Weybright, Xiaojun Yu, Emmanuel Crabbe, Paul D. Agnello
2011	—	`conf`	Three Dimensional integration - Considerations for memory applications. CICC Subramanian S. Iyer, Toshiaki Kirihata, John E. Barth Jr.
2009	J	`jnl`	A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS. IEEE J. Solid State Circuits Peter J. Klim, John Barth, William R. Reohr, David Dick, Gregory Fredeman, Gary Koch, Hien M. Le, Aditya Khargonekar, Pamela Wilcox, John Golz, Jente B. Kuang, Abraham Mathews, Jethro C. Law, Trong Luong, Hung C. Ngo, Ryan Freese, Hillery C. Hunter, Erik Nelson, Paul C. Parries, Toshiaki Kirihata, Subramanian S. Iyer
2008	J	`jnl`	A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier. IEEE J. Solid State Circuits John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer
2008	—	`conf`	A Commercial Field-Programmable Dense eFUSE Array Memory with 99.999% Sense Yield for 45nm SOI CMOS. ISSCC Gregory Uhlmann, Tony Aipperspach, Toshiaki Kirihata, K. Chandrasekharan, Yan Zun Li, Chris Paone, Brian Reed, Norman Robson, John Safran, David Schmitt, Subramanian S. Iyer
2008	A	`conf`	Analysis of Retention Time Distribution of Embedded DRAM - A New Method to Characterize Across-Chip Threshold Voltage Variation. ITC Wei Kong, Paul C. Parries, G. Wang, Subramanian S. Iyer
2007	—	`conf`	A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier. ISSCC John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer
2007	—	`conf`	Electrically Programmable Fuse (eFUSE): From Memory Redundancy to Autonomic Chips. CICC Norman Robson, John Safran, Chandrasekharan Kothandaraman, Alberto Cestero, Xiang Chen, Raj Rajeevakumar, Alan Leslie, Dan Moy, Toshiaki Kirihata, Subramanian S. Iyer
2005	J	`jnl`	An 800-MHz embedded DRAM with a concurrent refresh mode. IEEE J. Solid State Circuits Toshiaki Kirihata, Paul C. Parries, David R. Hanson, Hoki Kim, John Golz, Gregory Fredeman, Raj Rajeevakumar, John Griesemer, Norman Robson, Alberto Cestero, Babar A. Khan, Geng Wang, Matt Wordeman, Subramanian S. Iyer
2005	J	`jnl`	Embedded DRAM: Technology platform for the Blue Gene/L chip. IBM J. Res. Dev. Subramanian S. Iyer, John E. Barth Jr., Paul C. Parries, James P. Norum, James P. Rice, Lyndon R. Logan, Dennis Hoyniak
2000	J	`jnl`	1-GHz fully pipelined 3.7-ns address access time 8 k×1024 embedded synchronous DRAM macro. IEEE J. Solid State Circuits Osamu Takahashi, Sang H. Dhong, Manabu Ohkubo, Shohji Onishi, Robert H. Dennard, Robert Hannon, Scott Crowder, Subramanian S. Iyer, Matthew R. Wordeman, Bijan Davari, William B. Weinberger, Naoaki Aoki