Subodh Wairya

17 papers Journal 15Unranked 2
YearRankTypeTitle / Venue / Authors
2026 J jnl
Low-Power, Sensing Small Differential Input Signal of High Speed Dynamic Comparator with Transconductance-Improved Latching Stage.
J. Circuits Syst. Comput.
Anurag Yadav, Subodh Wairya
2025 J jnl
Charge shared based low power and high-speed dynamic comparator for high frequency analog signal processing architecture.
Integr.
Anurag Yadav, Subodh Wairya
2024 J jnl
Design and Analysis of Low Power and High-Speed Dynamic Comparator with Transconductance Enhanced in Latching Stage for ADC Application.
J. Circuits Syst. Comput.
Anurag Yadav, Subodh Wairya
2023 J jnl
A 6.7 GHz, 89.33 μW Power and 81.26% Tuning Range Dual Input Ring VCO with PMOS Varactor.
J. Circuits Syst. Comput.
Mohd Saqib, Subodh Wairya, Anurag Yadav
2023 J jnl
Carry look-ahead and ripple carry method based 4-bit carry generator circuit for implementing wide-word length adder.
Microelectron. J.
Anum Khan, Arindom Chakraborty, Upal Barua Joy, Subodh Wairya, Mehedi Hasan
2023 — conf
Design Analysis of an Energy-Efficient Low-Power Dynamic Comparator Using NMOS Based Preamplifier.
ICCCNT
Abhinav Saxena, Anurag Yadav, Subodh Wairya
2021 J jnl
Hybrid deep neural network with adaptive galactic swarm optimization for text extraction from scene images.
Soft Comput.
Digvijay Pandey, Binay Kumar Pandey, Subodh Wairya
2021 J jnl
Prediction of Breast Cancer Using Extremely Randomized Clustering Forests (ERCF) Technique: Prediction of Breast Cancer.
Int. J. Distributed Syst. Technol.
Akhil Gupta, Rohit Anand, Digvijay Pandey, Nidhi Sindhwani, Subodh Wairya, Binay Kumar Pandey, Manvinder Sharma
2019 J jnl
Novel Lossless Grounded and Floating Inductance Simulators Employing a Grounded Capacitor Based on CC-CFA.
J. Circuits Syst. Comput.
Amrita Singh, Manoj Kumar Jain, Subodh Wairya
2017 J jnl
Novel conservative reversible error control circuits based on molecular QCA.
Int. J. Comput. Appl. Technol.
Neeraj Kumar Misra, Bibhash Sen, Subodh Wairya
2017 J jnl
Testable Novel Parity-Preserving Reversible Gate and Low-Cost Quantum Decoder Design in 1D Molecular-QCA.
J. Circuits Syst. Comput.
Neeraj Kumar Misra, Bibhash Sen, Subodh Wairya, Bandan Kumar Bhoi
2015 J jnl
Cost Efficient Design of Reversible Adder Circuits for Low Power Applications.
CoRR
Neeraj Kumar Misra, Mukesh Kumar Kushwaha, Subodh Wairya, Amit Kumar
2015 J jnl
Evolution of structure of some binary group based n bit comparator, n-to-2n decoder by reversible technique.
CoRR
Neeraj Kumar Misra, Subodh Wairya, Vinod Kumar Singh
2015 J jnl
Feasible methodology for optimization of a novel reversible binary compressor.
CoRR
Neeraj Kumar Misra, Mukesh Kumar Kushwaha, Subodh Wairya, Amit Kumar
2015 — conf
Optimized Approach for Reversible Code Converters Using Quantum Dot Cellular Automata.
FICTA
Neeraj Kumar Misra, Subodh Wairya, Vinod Kumar Singh
2012 J jnl
Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design.
VLSI Design
Subodh Wairya, Rajendra Kumar Nagaria, Sudarshan Tiwari
2010 J jnl
On the New Design of sinusoid voltage Controlled oscillators Using Multiplier in CFA-Based Double Integrator Loop.
J. Circuits Syst. Comput.
Rajendra Kumar Nagaria, Rakesh Kumar Singh, Subodh Wairya