Subhendu Roy - RankMe

22 papers A* 2A 2C 1Misc 1Journal 11Unranked 5

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	SMART-GPO: Gate-Level Sensitivity Measurement with Accurate Estimation for Glitch Power Optimization. ASP-DAC Yikang Ouyang, Yuchao Wu, Dongsheng Zuo, Subhendu Roy, Tinghuan Chen, Zhiyao Xie, Yuzhe Ma
2022	J	`jnl`	High-Speed Adder Design Space Exploration via Graph Neural Processes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hao Geng, Yuzhe Ma, Qi Xu, Jin Miao, Subhendu Roy, Bei Yu
2021	J	`jnl`	Machine Learning for Statistical Modeling: The Case of Perpendicular Spin-Transfer-Torque Random Access Memory. ACM Trans. Design Autom. Electr. Syst. Urmimala Roy, Tanmoy Pramanik, Subhendu Roy, Avhishek Chatterjee, Leonard F. Register, Sanjay Kumar Banerjee
2019	J	`jnl`	Cross-Layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yuzhe Ma, Subhendu Roy, Jin Miao, Jiamin Chen, Bei Yu
2018	J	`jnl`	Cross-layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach. CoRR Yuzhe Ma, Subhendu Roy, Jin Miao, Jiamin Chen, Bei Yu
2018	J	`jnl`	SD-PUF: Spliced Digital Physical Unclonable Function. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jin Miao, Meng Li, Subhendu Roy, Yuzhe Ma, Bei Yu
2017	A	`conf`	A learning bridge from architectural synthesis to physical design for exploring power efficient high-performance adders. ISLPED Subhendu Roy, Yuzhe Ma, Jin Miao, Bei Yu
2016	J	`jnl`	Design for manufacturability and reliability in extreme-scaling VLSI. Sci. China Inf. Sci. Bei Yu, Xiaoqing Xu, Subhendu Roy, Yibo Lin, Jiaojiao Ou, David Z. Pan
2016	A	`conf`	LRR-DPUF: learning resilient and reliable digital physical unclonable function. ICCAD Jin Miao, Meng Li, Subhendu Roy, Bei Yu
2016	J	`jnl`	OSFA: A New Paradigm of Aging Aware Gate-Sizing for Power/Performance Optimizations Under Multiple Operating Conditions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Subhendu Roy, Derong Liu, Jagmohan Singh, Junhyung Um, David Z. Pan
2016	J	`jnl`	Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan
2015	C	`conf`	CSL: Coordinated and scalable logic synthesis techniques for effective NBTI reduction. ICCD Chen-Hsuan Lin, Subhendu Roy, Chun-Yao Wang, David Z. Pan, Deming Chen
2015	J	`jnl`	Clock Tree Resynthesis for Multi-Corner Multi-Mode Timing Closure. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Subhendu Roy, Pavlos M. Mattheakis, Laurent Masse-Navette, David Z. Pan
2015	A*	`conf`	OSFA: a new paradigm of gate-sizing for power/performance optimizations under multiple operating conditions. DAC Subhendu Roy, Derong Liu, Junhyung Um, David Z. Pan
2015	—	`conf`	Polynomial time algorithm for area and power efficient adder synthesis in high-performance designs. ASP-DAC Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan
2015	—	`conf`	Skew Bounded Buffer Tree Resynthesis For Clock Power Optimization. ACM Great Lakes Symposium on VLSI Subhendu Roy, David Z. Pan, Pavlos M. Mattheakis, Peter S. Colyer, Laurent Masse-Navette, Pierre-Olivier Ribet
2014	—	`conf`	Clock tree resynthesis for multi-corner multi-mode timing closure. ISPD Subhendu Roy, Pavlos M. Mattheakis, Laurent Masse-Navette, David Z. Pan
2014	Misc	`conf`	Reliability Aware Gate Sizing Combating NBTI and Oxide Breakdown. VLSID Subhendu Roy, David Z. Pan
2014	J	`jnl`	Towards Optimal Performance-Area Trade-Off in Adders by Synthesis of Parallel Prefix Structures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan
2014	J	`jnl`	Triple Patterning Lithography (TPL) Layout Decomposition using End-Cutting (JM3 Special Session). CoRR Bei Yu, Subhendu Roy, Jhih-Rong Gao, David Z. Pan
2013	A*	`conf`	Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures. DAC Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan
2010	—	`conf`	Large Scale VLSI Circuit Simulation Using Point Relaxation. CSC Subhendu Roy, Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar