Subhankar Pal

34 papers A* 6A 2B 3C 1Misc 1Journal 15Unranked 5
YearRankTypeTitle / Venue / Authors
2025 J jnl
A remedy to mitigate tensile instability in SPH for simulating large deformation and failure of geomaterials.
Adv. Eng. Softw.
Tapan Jana, Subhankar Pal, Amit Shaw, L. S. Ramachandra
2025 A* conf
ARTEMIS: Agile Discovery of Efficient Real-Time Systems-on-Chips in the Heterogeneous Era.
HPCA
Subhankar Pal, Aporva Amarnath, Behzad Boroujerdian, Augusto Vega, Alper Buyuktosunoglu, John-David Wellman, Vijay Janapa Reddi, Pradip Bose
2025 A* conf
FHENDI: A Near-DRAM Accelerator for Compiler-Generated Fully Homomorphic Encryption Applications.
HPCA
Yongmo Park, Aporva Amarnath, Subhankar Pal, Karthik Swaminathan, Alper Buyuktosunoglu, Hayim Shaul, Ehud Aharoni, Nir Drucker, Wei D. Lu, Omri Soceanu, Pradip Bose
2025 J jnl
Opportunities and Challenges of Native Sensing in 6G: A Survey on Research and Standardization.
IEEE Internet Things J.
Mohammad Nabati, Toktam Mahmoodi, Subhankar Pal, Sandip Sarkar
2024 J jnl
A remedy to mitigate tensile instability in SPH for simulating large deformation and failure of geomaterials.
CoRR
Tapan Jana, Subhankar Pal, Amit Shaw, L. S. Ramachandra
2024 J jnl
Dramaton: A Near-DRAM Accelerator for Large Number Theoretic Transforms.
IEEE Comput. Archit. Lett.
Yongmo Park, Subhankar Pal, Aporva Amarnath, Karthik Swaminathan, Wei D. Lu, Alper Buyuktosunoglu, Pradip Bose
2023 J jnl
Accelerating Graph Analytics on a Reconfigurable Architecture with a Data-Indirect Prefetcher.
CoRR
Yichen Yang, Jingtao Li, Nishil Talati, Subhankar Pal, Siying Feng, Chaitali Chakrabarti, Trevor N. Mudge, Ronald G. Dreslinski
2023 — conf
Efficient Pruning for Machine Learning Under Homomorphic Encryption.
ESORICS (4)
Ehud Aharoni, Moran Baruch, Pradip Bose, Alper Buyuktosunoglu, Nir Drucker, Subhankar Pal, Tomer Pelleg, Kanthi K. Sarpatwar, Hayim Shaul, Omri Soceanu, Roman Vaculín
2023 J jnl
xURLCC in 6g with meshed RAN.
CoRR
Mohammad Ali Khoshkholghi, Toktam Mahmoodi, Subhankar Pal, Subhash Chopra, Mayuri Tendulkar, Sandip Sarkar
2022 J jnl
A Holistic Solution for Reliability of 3D Parallel Systems.
ACM J. Emerg. Technol. Comput. Syst.
Javad Bagherzadeh, Aporva Amarnath, Jielun Tan, Subhankar Pal, Ronald G. Dreslinski
2022 J jnl
HE-PEx: Efficient Machine Learning under Homomorphic Encryption using Pruning, Permutation and Expansion.
CoRR
Ehud Aharoni, Moran Baruch, Pradip Bose, Alper Buyuktosunoglu, Nir Drucker, Subhankar Pal, Tomer Pelleg, Kanthi K. Sarpatwar, Hayim Shaul, Omri Soceanu, Roman Vaculín
2022 J jnl
HetSched: Quality-of-Mission Aware Scheduling for Autonomous Vehicle SoCs.
CoRR
Aporva Amarnath, Subhankar Pal, Hiwot Kassa, Augusto Vega, Alper Buyuktosunoglu, Hubertus Franke, John-David Wellman, Ronald G. Dreslinski, Pradip Bose
2022 J jnl
OnSRAM: Efficient Inter-Node On-Chip Scratchpad Management in Deep Learning Accelerators.
ACM Trans. Embed. Comput. Syst.
Subhankar Pal, Swagath Venkataramani, Viji Srinivasan, Kailash Gopalakrishnan
2022 J jnl
Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory.
IEEE J. Solid State Circuits
Sung Kim, Morteza Fayazi, Alhad Daftardar, Kuan-Yu Chen, Jielun Tan, Subhankar Pal, Tutu Ajayi, Yan Xiong, Trevor N. Mudge, Chaitali Chakrabarti, David T. Blaauw, Ronald G. Dreslinski, Hun-Seok Kim
2021 A* conf
CoSPARSE: A Software and Hardware Reconfigurable SpMV Framework for Graph Analytics.
DAC
Siying Feng, Jiawen Sun, Subhankar Pal, Xin He, Kuba Kaszyk, Dong-Hyeon Park, John Magnus Morton, Trevor N. Mudge, Murray Cole, Michael F. P. O'Boyle, Chaitali Chakrabarti, Ronald G. Dreslinski
2021 B conf
Efficient Management of Scratch-Pad Memories in Deep Learning Accelerators.
ISPASS
Subhankar Pal, Swagath Venkataramani, Viji Srinivasan, Kailash Gopalakrishnan
2021 J jnl
Heterogeneity-Aware Scheduling on SoCs for Autonomous Vehicles.
IEEE Comput. Archit. Lett.
Aporva Amarnath, Subhankar Pal, Hiwot Tadese Kassa, Augusto Vega, Alper Buyuktosunoglu, Hubertus Franke, John-David Wellman, Ronald Dreslinski Jr., Pradip Bose
2021 A* conf
SparseAdapt: Runtime Control for Sparse Linear Algebra on a Reconfigurable Accelerator.
MICRO
Subhankar Pal, Aporva Amarnath, Siying Feng, Michael F. P. O'Boyle, Ronald G. Dreslinski, Christophe Dubach
2021 — —
Towards Closing the Programmability-Efficiency Gap using Software-Defined Hardware.
Subhankar Pal
2021 — conf
Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm.
VLSI Circuits
Sung Kim, Morteza Fayazi, Alhad Daftardar, Kuan-Yu Chen, Jielun Tan, Subhankar Pal, Tutu Ajayi, Yan Xiong, Trevor N. Mudge, Chaitali Chakrabarti, David T. Blaauw, Ronald G. Dreslinski, Hun-Seok Kim
2021 J jnl
Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm.
CoRR
Sung Kim, Morteza Fayazi, Alhad Daftardar, Kuan-Yu Chen, Jielun Tan, Subhankar Pal, Tutu Ajayi, Yan Xiong, Trevor N. Mudge, Chaitali Chakrabarti, David T. Blaauw, Ronald G. Dreslinski, Hun-Seok Kim
2020 J jnl
A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator.
IEEE J. Solid State Circuits
Dong-Hyeon Park, Subhankar Pal, Siying Feng, Paul Gao, Jielun Tan, Austin Rovinski, Shaolin Xie, Chun Zhao, Aporva Amarnath, Timothy Wesley, Jonathan Beaumont, Kuan-Yu Chen, Chaitali Chakrabarti, Michael Bedford Taylor, Trevor N. Mudge, David T. Blaauw, Hun-Seok Kim, Ronald G. Dreslinski
2020 C conf
Accelerating Deep Neural Network Computation on a Low Power Reconfigurable Architecture.
ISCAS
Yan Xiong, Jian Zhou, Subhankar Pal, David T. Blaauw, Hun-Seok Kim, Trevor N. Mudge, Ronald G. Dreslinski, Chaitali Chakrabarti
2020 Misc conf
Accelerating Linear Algebra Kernels on a Massively Parallel Reconfigurable Architecture.
ICASSP
A. Soorishetty, Jian Zhou, Subhankar Pal, David T. Blaauw, H. Kim, Trevor N. Mudge, Ronald G. Dreslinski, Chaitali Chakrabarti
2020 — conf
HETSIM: Simulating Large-Scale Heterogeneous Systems using a Trace-driven, Synchronization and Dependency-Aware Framework.
IISWC
Subhankar Pal, Kuba Kaszyk, Siying Feng, Björn Franke, Murray Cole, Michael F. P. O'Boyle, Trevor N. Mudge, Ronald G. Dreslinski
2020 A* conf
R2D3: A Reliability Engine for 3D Parallel Systems.
DAC
Javad Bagherzadeh, Aporva Amarnath, Jielun Tan, Subhankar Pal, Ronald G. Dreslinski
2020 J jnl
STOMP: A Tool for Evaluation of Scheduling Policies in Heterogeneous Multi-Processors.
CoRR
Augusto Vega, Aporva Amarnath, John-David Wellman, Hiwot Kassa, Subhankar Pal, Hubertus Franke, Alper Buyuktosunoglu, Ronald G. Dreslinski, Pradip Bose
2020 A conf
Sparse-TPU: adapting systolic arrays for sparse matrices.
ICS
Xin He, Subhankar Pal, Aporva Amarnath, Siying Feng, Dong-Hyeon Park, Austin Rovinski, Haojie Ye, Kuan-Yu Chen, Ronald G. Dreslinski, Trevor N. Mudge
2020 B conf
Transmuter: Bridging the Efficiency Gap using Memory and Dataflow Reconfiguration.
PACT
Subhankar Pal, Siying Feng, Dong-Hyeon Park, Sung Kim, Aporva Amarnath, Chi-Sheng Yang, Xin He, Jonathan Beaumont, Kyle May, Yan Xiong, Kuba Kaszyk, John Magnus Morton, Jiawen Sun, Michael F. P. O'Boyle, Murray Cole, Chaitali Chakrabarti, David T. Blaauw, Hun-Seok Kim, Trevor N. Mudge, Ronald G. Dreslinski
2019 — conf
A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm.
VLSI Circuits
Subhankar Pal, Dong-Hyeon Park, Siying Feng, Paul Gao, Jielun Tan, Austin Rovinski, Shaolin Xie, Chun Zhao, Aporva Amarnath, Timothy Wesley, Jonathan Beaumont, Kuan-Yu Chen, Chaitali Chakrabarti, Michael B. Taylor, Trevor N. Mudge, David T. Blaauw, Hun-Seok Kim, Ronald G. Dreslinski
2019 B conf
Parallelism Analysis of Prominent Desktop Applications: An 18- Year Perspective.
ISPASS
Siying Feng, Subhankar Pal, Yichen Yang, Ronald G. Dreslinski
2018 A* conf
OuterSPACE: An Outer Product Based Sparse Matrix Multiplication Accelerator.
HPCA
Subhankar Pal, Jonathan Beaumont, Dong-Hyeon Park, Aporva Amarnath, Siying Feng, Chaitali Chakrabarti, Hun-Seok Kim, David T. Blaauw, Trevor N. Mudge, Ronald G. Dreslinski
2017 A conf
A carbon nanotube transistor based RISC-V processor using pass transistor logic.
ISLPED
Aporva Amarnath, Siying Feng, Subhankar Pal, Tutu Ajayi, Austin Rovinski, Ronald G. Dreslinski
2014 — conf
A New Design of an N-Bit Reversible Arithmetic Logic Unit.
ISED
Subhankar Pal, Chetan Kumar Vudadha, P. Sai Phaneendra, Sreehari Veeramachaneni, Srinivas B. Mandalika