Stéphane Badel

17 papers A* 1A 3B 2C 4Journal 2Unranked 4
YearRankTypeTitle / Venue / Authors
2011 A* conf
Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library.
DAC
Alessandro Cevrero, Francesco Regazzoni, Micheal Schwander, Stéphane Badel, Paolo Ienne, Yusuf Leblebici
2010 A conf
ARMADILLO: A Multi-purpose Cryptographic Primitive Dedicated to Hardware.
CHES
Stéphane Badel, Nilay Dagtekin, Jorge Nakahara Jr., Khaled Ouafi, Nicolas Reffé, Pouyan Sepehrdad, Petr Susil, Serge Vaudenay
2010 J jnl
Optimization of the wire grid size for differential routing: Analysis and impact on the power-delay-area tradeoff.
Microelectron. J.
Massimo Alioto, Stéphane Badel, Yusuf Leblebici
2009 A conf
A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions.
CHES
Francesco Regazzoni, Alessandro Cevrero, François-Xavier Standaert, Stéphane Badel, Theo Kluter, Philip Brisk, Yusuf Leblebici, Paolo Ienne
2009 C conf
Optimization of Wire Grid Size for Differential Routing and Impact on the Power-delay-area Tradeoff.
ISCAS
Massimo Alioto, Stéphane Badel, Yusuf Leblebici
2008 A conf
A Generic Standard Cell Design Methodology for Differential Circuit Styles.
DATE
Stéphane Badel, Erdem Guleyupoglu, Ozgur Inac, Anna Pena Martinez, Paolo Vietti, Frank K. Gürkaynak, Yusuf Leblebici
2008 J jnl
CMOS realization of two-dimensional mixed analog-digital Hamming distance discriminator circuits for real-time imaging applications.
Microelectron. J.
Stéphane Badel, Alexandre Schmid, Yusuf Leblebici
2008 — —
MOS current-mode logic standard cells for high-speed low-noise applications.
Stéphane Badel
2007 — conf
A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies.
ICSAMOS
Francesco Regazzoni, Stéphane Badel, Thomas Eisenbarth, Johann Großschädl, Axel Poschmann, Zeynep Toprak Deniz, Marco Macchetti, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne
2007 C conf
Breaking the Power-Delay Tradeoff: Design of Low-Power High-Speed MOS Current-Mode Logic Circuits Operating with Reduced Supply Voltage.
ISCAS
Stéphane Badel, Yusuf Leblebici
2007 — conf
Early wire characterization for predictable network-on-chip global interconnects.
SLIP
Ilhan Hatirnaz, Stéphane Badel, Nuria Pazos, Yusuf Leblebici, Srinivasan Murali, David Atienza, Giovanni De Micheli
2007 — conf
Predictable system interconnects through accurate early wire characterization.
SoCC
I. Hatyrnaz, Stéphane Badel, Nuria Pazos, Yusuf Leblebici
2006 C conf
Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells.
VLSI-SoC
Stéphane Badel, Ilhan Hatirnaz, Yusuf Leblebici, Elizabeth J. Brauer
2006 C conf
Via-programmable expanded universal logic gate in MCML for structured ASIC applications: circuit design.
ISCAS
Elizabeth J. Brauer, Ilhan Hatirnaz, Stéphane Badel, Yusuf Leblebici
2004 — conf
Mixed analog-digital image processing circuit based on Hamming artificial neural network architecture.
ISCAS (5)
Stéphane Badel, Alexandre Schmid, Yusuf Leblebici
2003 B conf
A VLSI Hamming artificial neural network with k-winner-take-all and k-loser-take-all capability.
IJCNN
Stéphane Badel, Alexandre Schmid, Yusuf Leblebici
2003 B conf
VLSI Realization of a Two-Dimensional Hamming Distance Comparator ANN for Image Processing Applications.
ESANN
Stéphane Badel, Alexandre Schmid, Yusuf Leblebici