Stéphan Jourdan

16 papers A* 9Journal 4Unranked 3
YearRankTypeTitle / Venue / Authors
2025 J jnl
Optimized Memory Tagging on AmpereOne Processors.
CoRR
Shiv Kaushik, Mahesh Madhav, Nagi Aboulenein, Jason Bessette, Sandeep Brahmadathan, Ben Chaffin, Matthew Erler, Stéphan Jourdan, Thomas Maciukenas, Ramya Masti, Jon Perry, Massimo Sutera, Scott Tetrick, Bret Toll, David Turley, Carl Worth, Atiq Bajwa
2014 J jnl
Haswell: The Fourth-Generation Intel Core Processor.
IEEE Micro
Per Hammarlund, Alberto J. Martinez, Atiq A. Bajwa, David L. Hill, Erik G. Hallnor, Hong Jiang, Martin G. Dixon, Michael Derr, Mikal Hunsaker, Rajesh Kumar, Randy B. Osborne, Ravi Rajwar, Ronak Singhal, Reynold D'Sa, Robert Chappell, Shiv Kaushik, Srinivas Chennupaty, Stéphan Jourdan, Steve Gunther, Thomas Piazza, Ted Burton
2009 — conf
Transitioning the Intel® next generation microarchitectures (nehalem and westmere) into the mainstream.
Hot Chips Symposium
Lily Pao Looi, Stéphan Jourdan
2002 A* conf
A stateless, content-directed data prefetching mechanism.
ASPLOS
Robert Cooksey, Stéphan Jourdan, Dirk Grunwald
2001 J jnl
An Exploration of Instruction Fetch Requirement in Out-of-Order Superscalar Processors.
Int. J. Parallel Program.
Pierre Michaud, André Seznec, Stéphan Jourdan
2000 A* conf
Early load address resolution via register tracking.
ISCA
Michael Bekerman, Adi Yoaz, Freddy Gabbay, Stéphan Jourdan, Maxim Kalaev, Ronny Ronen
2000 A* conf
eXtended Block Cache.
HPCA
Stéphan Jourdan, Lihu Rappoport, Yoav Almog, Mattan Erez, Adi Yoaz, Ronny Ronen
1999 A* conf
Correlated Load-Address Predictors.
ISCA
Michael Bekerman, Stéphan Jourdan, Ronny Ronen, Gilad Kirshenboim, Lihu Rappoport, Adi Yoaz, Uri C. Weiser
1999 — conf
Exploring Instruction-Fetch Bandwidth Requirement in Wide-Issue Superscalar Processors.
IEEE PACT
Pierre Michaud, André Seznec, Stéphan Jourdan
1999 A* conf
Speculation Techniques for Improving Load Related Instruction Scheduling.
ISCA
Adi Yoaz, Mattan Erez, Ronny Ronen, Stéphan Jourdan
1998 A* conf
A Novel Renaming Scheme to Exploit Value Temporal Locality Through Physical Register Reuse and Unification.
MICRO
Stéphan Jourdan, Ronny Ronen, Michael Bekerman, Bishara Shomar, Adi Yoaz
1997 J jnl
Recovery requirements of branch prediction storage structures in the presence of mispredicted-path execution.
Int. J. Parallel Program.
Stéphan Jourdan, Jared Stark, Tse-Hao Hsing, Yale N. Patt
1996 A* conf
Multiple-Block Ahead Branch Predictors.
ASPLOS
André Seznec, Stéphan Jourdan, Pascal Sainrat, Pierre Michaud
1996 — conf
The effects of mispredicted-path execution on branch prediction structures.
IEEE PACT
Stéphan Jourdan, Tse-Hao Hsing, Jared Stark, Yale N. Patt
1995 A* conf
An investigation of the performance of various instruction-issue buffer topologies.
MICRO
Stéphan Jourdan, Pascal Sainrat, Daniel Litaize
1995 A* conf
Exploring Configurations of Functional Units in an Out-of-Order Superscalar Processor.
ISCA
Stéphan Jourdan, Pascal Sainrat, Daniel Litaize