Stijn Eyerman - RankMe

70 papers A* 13A 3B 16Journal 32Unranked 6

Year	Rank	Type	Title / Venue / Authors
2025	A*	`conf`	DECA: A Near-Core LLM Decompression Accelerator Grounded on a 3D Roofline Model. MICRO Gerasimos Gerogiannis, Stijn Eyerman, Evangelos Georganas, Wim Heirman, Josep Torrellas
2025	J	`jnl`	DECA: A Near-Core LLM Decompression Accelerator Supporting Out-of-Order Invocation. CoRR Gerasimos Gerogiannis, Stijn Eyerman, Evangelos Georganas, Wim Heirman, Josep Torrellas
2025	B	`conf`	Multi-Core Aware Evaluation of Prefetchers. ISPASS Martí Torrents, Paul Caheny, Stijn Eyerman, Wim Heirman
2024	J	`jnl`	Accurate and Scalable Many-Node Simulation. CoRR Stijn Eyerman, Wim Heirman, Kristof Du Bois, Ibrahim Hur
2024	B	`conf`	Message from the Program Chairs; ISPASS 2024. ISPASS Wim Heirman, Stijn Eyerman
2023	B	`conf`	Simulating Wrong-Path Instructions in Decoupled Functional-First Simulation. ISPASS Stijn Eyerman, Sam Van den Steen, Wim Heirman, Ibrahim Hur
2023	J	`jnl`	The Intel Programmable and Integrated Unified Memory Architecture Graph Analytics Processor. IEEE Micro Sriram Aananthakrishnan, Shamsul Abedin, Vincent Cavé, Fabio Checconi, Kristof Du Bois, Stijn Eyerman, Joshua B. Fryman, Wim Heirman, Jason Howard, Ibrahim Hur, Samkit Jain, Marek M. Landowski, Kevin Ma, Jarrod A. Nelson, Robert Pawlowski, Fabrizio Petrini, Sebastian Szkoda, Sanjaya Tayal, Jesmin Jahan Tithi, Yves Vandriessche
2022	B	`conf`	DRAM Bandwidth and Latency Stacks: Visualizing DRAM Bottlenecks. ISPASS Stijn Eyerman, Wim Heirman, Ibrahim Hur
2022	J	`jnl`	Efficient Asynchronous RPC Calls for Microservices: DeathStarBench Study. CoRR Stijn Eyerman, Ibrahim Hur
2022	J	`jnl`	Execution Time Estimation of Multithreaded Programs With Critical Sections. IEEE Trans. Parallel Distributed Syst. Dimitri Kagaris, Sourav Dutta, Stijn Eyerman
2022	B	`conf`	Scale-Model Architectural Simulation. ISPASS Wenjie Liu, Wim Heirman, Stijn Eyerman, Shoaib Akram, Lieven Eeckhout
2021	J	`jnl`	Automatic Sublining for Efficient Sparse Memory Accesses. ACM Trans. Archit. Code Optim. Wim Heirman, Stijn Eyerman, Kristof Du Bois, Ibrahim Hur
2021	A*	`conf`	Enabling Branch-Mispredict Level Parallelism by Selectively Flushing Instructions. MICRO Stijn Eyerman, Wim Heirman, Sam Van den Steen, Ibrahim Hur
2021	J	`jnl`	Modeling DRAM Timing in Parallel Simulators With Immediate-Response Memory Model. IEEE Comput. Archit. Lett. Stijn Eyerman, Wim Heirman, Ibrahim Hur
2021	J	`jnl`	RIO: ROB-Centric In-Order Modeling of Out-of-Order Processors. IEEE Comput. Archit. Lett. Wim Heirman, Stijn Eyerman, Kristof Du Bois, Ibrahim Hur
2021	J	`jnl`	Scale-Model Simulation. IEEE Comput. Archit. Lett. Wenjie Liu, Wim Heirman, Stijn Eyerman, Shoaib Akram, Lieven Eeckhout
2020	J	`jnl`	Breaking In-Order Branch Miss Recovery. IEEE Comput. Archit. Lett. Stijn Eyerman, Wim Heirman, Sam Van den Steen, Ibrahim Hur
2020	J	`jnl`	PIUMA: Programmable Integrated Unified Memory Architecture. CoRR Sriram Aananthakrishnan, Nesreen K. Ahmed, Vincent Cavé, Marcelo Cintra, Yigit Demir, Kristof Du Bois, Stijn Eyerman, Joshua B. Fryman, Ivan Ganev, Wim Heirman, Hans-Christian Hoppe, Jason Howard, Ibrahim Hur, Midhunchandra Kodiyath, Samkit Jain, Daniel S. Klowden, Marek M. Landowski, Laurent Montigny, Ankit More, Przemyslaw Ossowski, Robert Pawlowski, Nick Pepperling, Fabrizio Petrini, Mariusz Sikora, Balasubramanian Seshasayee, Shaden Smith, Sebastian Szkoda, Sanjaya Tayal, Jesmin Jahan Tithi, Yves Vandriessche, Izajasz P. Wrosz
2020	—	`conf`	Projecting Performance for PIUMA using Down-Scaled Simulation. HPEC Stijn Eyerman, Wim Heirman, Yigit Demir, Kristof Du Bois, Ibrahim Hur
2018	B	`conf`	Extending the Performance Analysis Tool Box: Multi-stage CPI Stacks and FLOPS Stacks. ISPASS Stijn Eyerman, Wim Heirman, Kristof Du Bois, Ibrahim Hur
2018	A	`conf`	Many-core graph workload analysis. SC Stijn Eyerman, Wim Heirman, Kristof Du Bois, Joshua B. Fryman, Ibrahim Hur
2018	J	`jnl`	Multi-Stage CPI Stacks. IEEE Comput. Archit. Lett. Stijn Eyerman, Wim Heirman, Kristof Du Bois, Ibrahim Hur
2018	B	`conf`	Near-side prefetch throttling: adaptive prefetching for high-performance many-core processors. PACT Wim Heirman, Kristof Du Bois, Yves Vandriessche, Stijn Eyerman, Ibrahim Hur
2018	J	`jnl`	Optimizing Soft Error Reliability Through Scheduling on Heterogeneous Multicore Processors. IEEE Trans. Computers Ajeya Naithani, Stijn Eyerman, Lieven Eeckhout
2017	B	`conf`	Analyzing the scalability of managed language applications with speedup stacks. ISPASS Jennifer B. Sartor, Kristof Du Bois, Stijn Eyerman, Lieven Eeckhout
2017	—	`conf`	Exploring optimizations on shared-memory platforms for parallel triangle counting algorithms. HPEC Ancy Sarah Tom, Narayanan Sundaram, Nesreen K. Ahmed, Shaden Smith, Stijn Eyerman, Midhunchandra Kodiyath, Ibrahim Hur, Fabrizio Petrini, George Karypis
2017	J	`jnl`	Improving IBM POWER8 Performance Through Symbiotic Job Scheduling. IEEE Trans. Parallel Distributed Syst. Josué Feliu, Stijn Eyerman, Julio Sahuquillo, Salvador Petit, Lieven Eeckhout
2017	J	`jnl`	Linear Branch Entropy: Characterizing and Optimizing Branch Behavior in a Micro-Architecture Independent Way. IEEE Trans. Computers Sander De Pestel, Stijn Eyerman, Lieven Eeckhout
2017	J	`jnl`	Mind The Power Holes: Sifting Operating Points in Power-Limited Heterogeneous Multicores. IEEE Comput. Archit. Lett. Almutaz Adileh, Stijn Eyerman, Aamer Jaleel, Lieven Eeckhout
2017	A*	`conf`	Reliability-Aware Scheduling on Heterogeneous Multicore Processors. HPCA Ajeya Naithani, Stijn Eyerman, Lieven Eeckhout
2016	J	`jnl`	Analytical Processor Performance and Power Modeling Using Micro-Architecture Independent Characteristics. IEEE Trans. Computers Sam Van den Steen, Stijn Eyerman, Sander De Pestel, Moncef Mechri, Trevor E. Carlson, David Black-Schaffer, Erik Hagersten, Lieven Eeckhout
2016	J	`jnl`	Maximizing Heterogeneous Processor Performance Under Power Constraints. ACM Trans. Archit. Code Optim. Almutaz Adileh, Stijn Eyerman, Aamer Jaleel, Lieven Eeckhout
2016	A*	`conf`	Symbiotic job scheduling on the IBM POWER8. HPCA Josué Feliu, Stijn Eyerman, Julio Sahuquillo, Salvador Petit
2015	J	`jnl`	Mechanistic Modeling of Architectural Vulnerability Factor. ACM Trans. Comput. Syst. Arun Arvind Nair, Stijn Eyerman, Jian Chen, Lizy Kurian John, Lieven Eeckhout
2015	B	`conf`	Micro-architecture independent analytical processor performance and power modeling. ISPASS Sam Van den Steen, Sander De Pestel, Moncef Mechri, Stijn Eyerman, Trevor E. Carlson, David Black-Schaffer, Erik Hagersten, Lieven Eeckhout
2015	B	`conf`	Micro-architecture independent branch behavior characterization. ISPASS Sander De Pestel, Stijn Eyerman, Lieven Eeckhout
2015	B	`conf`	Revisiting symbiotic job scheduling. ISPASS Stijn Eyerman, Pierre Michaud, Wouter Rogiest
2014	J	`jnl`	An Evaluation of High-Level Mechanistic Core Models. ACM Trans. Archit. Code Optim. Trevor E. Carlson, Wim Heirman, Stijn Eyerman, Ibrahim Hur, Lieven Eeckhout
2014	J	`jnl`	Mechanistic Analytical Modeling of Superscalar In-Order Processor Performance. ACM Trans. Archit. Code Optim. Maximilien Breughe, Stijn Eyerman, Lieven Eeckhout
2014	J	`jnl`	Multiprogram Throughput Metrics: A Systematic Approach. ACM Trans. Archit. Code Optim. Stijn Eyerman, Pierre Michaud, Wouter Rogiest
2014	J	`jnl`	Restating the Case for Weighted-IPC Metrics to Evaluate Multiprogram Workload Performance. IEEE Comput. Archit. Lett. Stijn Eyerman, Lieven Eeckhout
2014	A*	`conf`	The benefit of SMT in the multi-core era: flexibility towards degrees of thread-level parallelism. ASPLOS Stijn Eyerman, Lieven Eeckhout
2013	A	`conf`	Bottle graphs: visualizing scalability bottlenecks in multi-threaded applications. OOPSLA Kristof Du Bois, Jennifer B. Sartor, Stijn Eyerman, Lieven Eeckhout
2013	A*	`conf`	Criticality stacks: identifying critical threads in parallel programs using synchronization behavior. ISCA Kristof Du Bois, Stijn Eyerman, Jennifer B. Sartor, Lieven Eeckhout
2013	J	`jnl`	Per-thread cycle accounting in multicore processors. ACM Trans. Archit. Code Optim. Kristof Du Bois, Stijn Eyerman, Lieven Eeckhout
2012	A*	`conf`	A first-order mechanistic model for architectural vulnerability factor. ISCA Arun A. Nair, Stijn Eyerman, Lieven Eeckhout, Lizy Kurian John
2012	B	`conf`	A mechanistic performance model for superscalar in-order processors. ISPASS Maximilien Breughe, Stijn Eyerman, Lieven Eeckhout
2012	—	`conf`	An efficient CPI stack counter architecture for superscalar processors. ACM Great Lakes Symposium on VLSI Osman Allam, Stijn Eyerman, Lieven Eeckhout
2012	J	`jnl`	Probabilistic modeling for job symbiosis scheduling on SMT processors. ACM Trans. Archit. Code Optim. Stijn Eyerman, Lieven Eeckhout
2012	B	`conf`	Speedup stacks: Identifying scaling bottlenecks in multi-threaded applications. ISPASS Stijn Eyerman, Kristof Du Bois, Lieven Eeckhout
2011	J	`jnl`	Fine-grained DVFS using on-chip regulators. ACM Trans. Archit. Code Optim. Stijn Eyerman, Lieven Eeckhout
2011	—	`conf`	How sensitive is processor customization to the workload's input datasets? SASP Maximilien Breughe, Zheng Li, Yang Chen, Stijn Eyerman, Olivier Temam, Chengyong Wu, Lieven Eeckhout
2011	B	`conf`	Mechanistic-empirical processor performance modeling for constructing CPI stacks on real hardware. ISPASS Stijn Eyerman, Kenneth Hoste, Lieven Eeckhout
2010	J	`jnl`	A Counter Architecture for Online DVFS Profitability Estimation. IEEE Trans. Computers Stijn Eyerman, Lieven Eeckhout
2010	A*	`conf`	Interval simulation: Raising the level of abstraction in architectural simulation. HPCA Davy Genbrugge, Stijn Eyerman, Lieven Eeckhout
2010	A*	`conf`	Modeling critical sections in Amdahl's law and its implications for multicore design. ISCA Stijn Eyerman, Lieven Eeckhout
2010	J	`jnl`	Per-Thread Cycle Accounting. IEEE Micro Stijn Eyerman, Lieven Eeckhout
2010	A*	`conf`	Probabilistic job symbiosis modeling for SMT processor scheduling. ASPLOS Stijn Eyerman, Lieven Eeckhout
2009	J	`jnl`	A mechanistic performance model for superscalar out-of-order processors. ACM Trans. Comput. Syst. Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith
2009	—	`conf`	MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor. HiPEAC Kenzo Van Craeynest, Stijn Eyerman, Lieven Eeckhout
2009	J	`jnl`	Memory-level parallelism aware fetch policies for simultaneous multithreading processors. ACM Trans. Archit. Code Optim. Stijn Eyerman, Lieven Eeckhout
2009	A*	`conf`	Per-thread cycle accounting in SMT processors. ASPLOS Stijn Eyerman, Lieven Eeckhout
2008	—	`conf`	Studying Compiler Optimizations on Superscalar Processors Through Interval Analysis. HiPEAC Stijn Eyerman, Lieven Eeckhout, James E. Smith
2008	J	`jnl`	System-Level Performance Metrics for Multiprogram Workloads. IEEE Micro Stijn Eyerman, Lieven Eeckhout
2007	A*	`conf`	A Memory-Level Parallelism Aware Fetch Policy for SMT Processors. HPCA Stijn Eyerman, Lieven Eeckhout
2007	J	`jnl`	A Top-Down Approach to Architecting CPI Component Performance Counters. IEEE Micro Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith
2007	B	`conf`	Studying Compiler-Microarchitecture Interactions through Interval Analysis. PACT Stijn Eyerman, Lieven Eeckhout, James E. Smith
2006	A*	`conf`	A performance counter architecture for computing accurate CPI components. ASPLOS Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith
2006	B	`conf`	Characterizing the branch misprediction penalty. ISPASS Stijn Eyerman, James E. Smith, Lieven Eeckhout
2006	A	`conf`	Efficient design space exploration of high performance embedded out-of-order processors. DATE Stijn Eyerman, Lieven Eeckhout, Koen De Bosschere