Stewart S. Taylor

16 papers Journal 8Unranked 8

Year	Rank	Type	Title / Venue / Authors
2011	—	`conf`	A 2.5GHz 32nm 0.35mm ISSCC Chang-Tsung Fu, Hasnain Lakdawala, Stewart S. Taylor, Krishnamurthy Soumyanath
2011	—	`conf`	A flip-chip-packaged 1.8V 28dBm class-AB power amplifier with shielded concentric transformers in 32nm SoC CMOS. ISSCC Yulin Tan, Hongtao Xu, Mohammed A. El-Tanani, Stewart S. Taylor, Hasnain Lakdawala
2011	—	`conf`	Fully balanced low-noise transconductance amplifiers with P1dB > 0dBm in 45nm CMOS. ESSCIRC Hemasundar Mohan Geddada, José Silva-Martínez, Stewart S. Taylor
2010	—	`conf`	A 10 GHz low phase noise VCO employing current reuse and capacitive power combining. CICC Diptendu Ghosh, Stewart S. Taylor, Yulin Tan, Ranjit Gharpurey
2009	J	`jnl`	A Class-G Supply Modulator and Class-E PA in 130 nm CMOS. IEEE J. Solid State Circuits Jeffrey S. Walling, Stewart S. Taylor, David J. Allstot
2009	J	`jnl`	A Fully Integrated Ultra-Low Insertion Loss T/R Switch for 802.11b/g/n Application in 90 nm CMOS Process. IEEE J. Solid State Circuits Adil A. Kidwai, Chang-Tsung Fu, Jonathan C. Jensen, Stewart S. Taylor
2008	J	`jnl`	A Broadband Low-Cost Direct-Conversion Receiver Front-End in 90 nm CMOS. IEEE J. Solid State Circuits Jing-Hong Conan Zhan, Brent R. Carlton, Stewart S. Taylor
2007	—	`conf`	A 5 GHz, 21 dBm output-IP3 resistive feedback LNA in 90-nm CMOS. ESSCIRC Bevin G. Perumana, Jing-Hong Conan Zhan, Stewart S. Taylor, Joy Laskar
2006	J	`jnl`	A 5-GHz 108-Mb/s 2 $\times$2 MIMO Transceiver RFIC With Fully Integrated 20.5-dBm ${\rm P}_{\rm 1dB}$ Power Amplifiers in 90-nm CMOS. IEEE J. Solid State Circuits Yorgos Palaskas, Ashoke Ravi, Stefano Pellerano, Brent R. Carlton, Mostafa A. Elmala, Ralph E. Bishop, Gaurab Banerjee, Rich B. Nicholls, Stanley K. Ling, Nati Dinur, Stewart S. Taylor, Krishnamurthy Soumyanath
2006	J	`jnl`	A 5-GHz 20-dBm Power Amplifier With Digitally Assisted AM-PM Correction in a 90-nm CMOS Process. IEEE J. Solid State Circuits Yorgos Palaskas, Stewart S. Taylor, Stefano Pellerano, Ian A. Rippke, Ralph E. Bishop, Ashoke Ravi, Hasnain Lakdawala, Krishnamurthy Soumyanath
2006	—	`conf`	A 5GHz 108Mb/s 2x2 MIMO Transceiver with Fully Integrated +16dBm PAs in 90nm CMOS. ISSCC Yorgos Palaskas, Ashoke Ravi, Stefano Pellerano, Brent R. Carlton, Mostafa A. Elmala, Ralph E. Bishop, Gaurab Banerjee, Rich B. Nicholls, Stanley K. Ling, Stewart S. Taylor, Krishnamurthy Soumyanath
2006	—	`conf`	A 5GHz resistive-feedback CMOS LNA for low-cost multi-standard applications. ISSCC Jing-Hong Conan Zhan, Stewart S. Taylor
2005	—	`conf`	A 5 GHz class-AB power amplifier in 90 nm CMOS with digitally-assisted AM-PM correction. CICC Yorgos Palaskas, Stewart S. Taylor, Stefano Pellerano, Ian A. Rippke, Ralph E. Bishop, Ashoke Ravi, Hasnain Lakdawala, Krishnamurthy Soumyanath
1997	J	`jnl`	A GaAs MESFET Schottky diode barrier height reference circuit. IEEE J. Solid State Circuits Stewart S. Taylor
1993	J	`jnl`	A complete 400-Mb/s burst-mode data OEIC receiver. IEEE J. Solid State Circuits I. Ross MacTaggart, Mark Bendett, Stewart S. Taylor
1993	J	`jnl`	A high-performance GaAs pin electronics circuit for automatic test equipment. IEEE J. Solid State Circuits Stewart S. Taylor