Steven M. Burns

50 papers A* 8A 12B 2C 1Journal 18Unranked 9

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	Constructive Place-and-Route for FinFET-Based Transistor Arrays in Analog Circuits Under Nonlinear Gradients. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Arvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Soner Yaldiz, Parijat Mukherjee, Ramesh Harjani, Sachin S. Sapatnekar
2023	J	`jnl`	A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts. ACM Trans. Design Autom. Electr. Syst. Ramprasath Srinivasa Gopalakrishnan, Meghna Madhusudan, Arvind K. Sharma, Jitesh Poojary, Soner Yaldiz, Ramesh Harjani, Steven M. Burns, Sachin S. Sapatnekar
2023	J	`jnl`	GNN-Based Hierarchical Annotation for Analog Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar
2023	—	`conf`	Reusing GEMM Hardware for Efficient Execution of Depthwise Separable Convolution on ASIC-Based DNN Accelerators. ASP-DAC Susmita Dey Manasi, Suvadeep Banerjee, Abhijit Davare, Anton A. Sorokin, Steven M. Burns, Desmond A. Kirkpatrick, Sachin S. Sapatnekar
2022	A	`conf`	A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement. DATE Tonmoy Dhar, Ramprasath S, Jitesh Poojary, Soner Yaldiz, Steven M. Burns, Ramesh Harjani, Sachin S. Sapatnekar
2022	—	`conf`	Analog/Mixed-Signal Layout Optimization using Optimal Well Taps. ISPD Ramprasath S, Meghna Madhusudan, Arvind K. Sharma, Jitesh Poojary, Soner Yaldiz, Ramesh Harjani, Steven M. Burns, Sachin S. Sapatnekar
2021	J	`jnl`	ALIGN: A System for Automating Analog Layout. IEEE Des. Test Tonmoy Dhar, Kishor Kunal, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar
2021	A	`conf`	Common-Centroid Layouts for Analog Circuits: Advantages and Limitations. DATE Arvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Parijat Mukherjee, Soner Yaldiz, Ramesh Harjani, Sachin S. Sapatnekar
2021	—	`conf`	Machine Learning Techniques in Analog Layout Automation. ISPD Tonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar
2021	A	`conf`	Performance-Aware Common-Centroid Placement and Routing of Transistor Arrays in Analog Circuits. ICCAD Arvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Soner Yaldiz, Parijat Mukherjee, Ramesh Harjani, Sachin S. Sapatnekar
2020	J	`jnl`	ALIGN: A System for Automating Analog Layout. CoRR Tonmoy Dhar, Kishor Kunal, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Parijat Mukherjee, Sachin S. Sapatnekar, Soner Yaldiz
2020	A	`conf`	GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits. DATE Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar
2020	—	`conf`	Learning from Experience: Applying ML to Analog Circuit Design. ISPD Kishor Kunal, Tonmoy Dhar, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Sachin S. Sapatnekar
2020	A	`conf`	The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk). ICCAD Tonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar
2019	A*	`conf`	ALIGN: Open-Source Analog Layout Automation from the Ground Up. DAC Kishor Kunal, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Sachin S. Sapatnekar
2019	—	`conf`	Pin Access-Driven Design Rule Clean and DFM Optimized Routing of Standard Cells under Boolean Constraints. ISPD Nikolay Ryzhenko, Steven M. Burns, Anton Sorokin, Mikhail Talalay
2018	B	`conf`	A FPGA Accelerator for Real-Time 3D Non-rigid Registration Using Tree Reweighted Message Passing and Dynamic Markov Random Field Generation. FPL Michael Barrow, Steven M. Burns, Ryan Kastner
2018	J	`jnl`	A Template-Based Design Methodology for Graph-Parallel Hardware Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrey Ayupov, Serif Yesil, Muhammet Mustafa Ozdal, TaeMin Kim, Steven M. Burns, Ozcan Ozturk
2017	J	`jnl`	Graph Analytics Accelerators for Cognitive Systems. IEEE Micro Muhammet Mustafa Ozdal, Serif Yesil, TaeMin Kim, Andrey Ayupov, John Greth, Steven M. Burns, Ozcan Ozturk
2016	A*	`conf`	Energy Efficient Architecture for Graph Analytics Accelerators. ISCA Muhammet Mustafa Ozdal, Serif Yesil, TaeMin Kim, Andrey Ayupov, John Greth, Steven M. Burns, Özcan Özturk
2015	A	`conf`	Architectural Requirements for Energy Efficient Execution of Graph Analytics Applications. ICCAD Muhammet Mustafa Ozdal, Serif Yesil, TaeMin Kim, Andrey Ayupov, Steven M. Burns, Ozcan Ozturk
2015	A	`conf`	Hardware Accelerator Design for Data Centers. ICCAD Serif Yesil, Muhammet Mustafa Ozdal, TaeMin Kim, Andrey Ayupov, Steven M. Burns, Ozcan Ozturk
2015	J	`jnl`	Wavelet-Based Trace Alignment Algorithms for Heterogeneous Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Muhammet Mustafa Ozdal, Aamer Jaleel, Paolo Narváez, Steven M. Burns, Ganapati Srinivasa
2013	—	`conf`	An improved benchmark suite for the ISPD-2013 discrete cell sizing contest. ISPD Muhammet Mustafa Ozdal, Chirayu Amin, Andrey Ayupov, Steven M. Burns, Gustavo R. Wilke, Cheng Zhuo
2013	A	`conf`	Trace alignment algorithms for offline workload analysis of heterogeneous architectures. ICCAD Muhammet Mustafa Ozdal, Aamer Jaleel, Paolo Narváez, Steven M. Burns, Ganapati Srinivasa
2012	J	`jnl`	Algorithms for Gate Sizing and Device Parameter Selection for High-Performance Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Muhammet Mustafa Ozdal, Steven M. Burns, Jiang Hu
2012	A*	`conf`	Standard cell routing via boolean satisfiability. DAC Nikolai Ryzhenko, Steven M. Burns
2012	—	`conf`	The ISPD-2012 discrete cell sizing contest and benchmark suite. ISPD Muhammet Mustafa Ozdal, Chirayu Amin, Andrey Ayupov, Steven M. Burns, Gustavo R. Wilke, Cheng Zhuo
2011	A	`conf`	A trace compression algorithm targeting power estimation of long benchmarks. ICCAD Andrey Ayupov, Steven M. Burns
2011	A	`conf`	Gate sizing and device technology selection algorithms for high-performance industrial designs. ICCAD Muhammet Mustafa Ozdal, Steven M. Burns, Jiang Hu
2011	A*	`conf`	Physical synthesis onto a layout fabric with regular diffusion and polysilicon geometries. DAC Nikolai Ryzhenko, Steven M. Burns
2007	A*	`conf`	Comparative Analysis of Conventional and Statistical Design Techniques. DAC Steven M. Burns, Mahesh Ketkar, Noel Menezes, Keith A. Bowman, James W. Tschanz, Vivek De
2002	J	`jnl`	Lazy transition systems and asynchronous circuit synthesis withrelative timing assumptions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jordi Cortadella, Michael Kishinevsky, Steven M. Burns, Alex Kondratyev, Luciano Lavagno, Ken S. Stevens, Alexander Taubin, Alexandre Yakovlev
2002	A*	`conf`	Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors. DAC Tanay Karnik, Yibin Ye, James W. Tschanz, Liqiong Wei, Steven M. Burns, Venkatesh Govindarajulu, Vivek De, Shekhar Borkar
1999	A*	`conf`	CAD Directions for High Performance Asynchronous Circuits. DAC Ken S. Stevens, Shai Rotem, Steven M. Burns, Jordi Cortadella, Ran Ginosar, Michael Kishinevsky, Marly Roncken
1999	A	`conf`	Synthesis of asynchronous control circuits with automatically generated relative timing assumptions. ICCAD Jordi Cortadella, Michael Kishinevsky, Steven M. Burns, Ken S. Stevens
1997	J	`jnl`	Bounded Delay Timing Analysis of a Class of CSP Programs. Formal Methods Syst. Des. Henrik Hulgaard, Steven M. Burns
1996	—	`conf`	General conditions for the decomposition of state holding elements. ASYNC Steven M. Burns
1995	J	`jnl`	An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems. IEEE Trans. Computers Henrik Hulgaard, Steven M. Burns, Tod Amon, Gaetano Borriello
1995	A*	`conf`	Efficient Timing Analysis of a Class of Petri Nets. CAV Henrik Hulgaard, Steven M. Burns
1995	J	`jnl`	Placement and routing tools for the Triptych FPGA. IEEE Trans. Very Large Scale Integr. Syst. Carl Ebeling, Larry McMurchie, Scott Hauck, Steven M. Burns
1995	J	`jnl`	Testing asynchronous circuits: A survey. Integr. Henrik Hulgaard, Steven M. Burns, Gaetano Borriello
1995	J	`jnl`	The Triptych FPGA architecture. IEEE Trans. Very Large Scale Integr. Syst. Gaetano Borriello, Carl Ebeling, Scott Hauck, Steven M. Burns
1994	J	`jnl`	An FPGA for Implementing Asynchronous Circuits. IEEE Des. Test Comput. Scott Hauck, Steven M. Burns, Gaetano Borriello, Carl Ebeling
1994	—	`conf`	Bounded delay timing analysis of a class of CSP programs with choice. ASYNC Henrik Hulgaard, Steven M. Burns
1993	C	`conf`	An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems. ICCD Tod Amon, Henrik Hulgaard, Steven M. Burns, Gaetano Borriello
1993	A	`conf`	Practical applications of an efficient time separation of events algorithm. ICCAD Henrik Hulgaard, Steven M. Burns, Tod Amon, Gaetano Borriello
1992	B	`conf`	MONTAGNE: An FPL for Synchronous and Asynchronous Circuits. FPL Scott Hauck, Gaetano Borriello, Steven M. Burns, Carl Ebeling
1989	J	`jnl`	The design of an asynchronous microprocessor. SIGARCH Comput. Archit. News Alain J. Martin, Steven M. Burns, Tak-Kwan Lee, Drazen Borkovic, Pieter J. Hazewindus
1989	J	`jnl`	The first asynchronous microprocessor: the test results. SIGARCH Comput. Archit. News Alain J. Martin, Steven M. Burns, Tak-Kwan Lee, Drazen Borkovic, Pieter J. Hazewindus